Fixing the IPF building issue for PeiCore
[mirror_edk2.git] / MdeModulePkg / Core / Pei / Ipf / IpfCpuCore.i
1 //++
2 // Copyright (c) 2006, Intel Corporation
3 // All rights reserved. This program and the accompanying materials
4 // are licensed and made available under the terms and conditions of the BSD License
5 // which accompanies this distribution. The full text of the license may be found at
6 // http://opensource.org/licenses/bsd-license.php
7 //
8 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
10 //
11 // Module Name:
12 //
13 // IpfCpuCore.i
14 //
15 // Abstract:
16 // IPF CPU definitions
17 //
18 //--
19
20 #ifndef _IPF_CPU_CORE_
21 #define _IPF_CPU_CORE_
22
23 #define PEI_BSP_STORE_SIZE 0x4000
24 #define ResetFn 0x00
25 #define MachineCheckFn 0x01
26 #define InitFn 0x02
27 #define RecoveryFn 0x03
28 #define GuardBand 0x10
29
30 //
31 // Define hardware RSE Configuration Register
32 //
33
34 //
35 // RS Configuration (RSC) bit field positions
36 //
37 #define RSC_MODE 0
38 #define RSC_PL 2
39 #define RSC_BE 4
40 //
41 // RSC bits 5-15 reserved
42 //
43 #define RSC_MBZ0 5
44 #define RSC_MBZ0_V 0x3ff
45 #define RSC_LOADRS 16
46 #define RSC_LOADRS_LEN 14
47 //
48 // RSC bits 30-63 reserved
49 //
50 #define RSC_MBZ1 30
51 #define RSC_MBZ1_V 0x3ffffffffULL
52
53 //
54 // RSC modes
55 //
56
57 //
58 // Lazy
59 //
60 #define RSC_MODE_LY (0x0)
61 //
62 // Store intensive
63 //
64 #define RSC_MODE_SI (0x1)
65 //
66 // Load intensive
67 //
68 #define RSC_MODE_LI (0x2)
69 //
70 // Eager
71 //
72 #define RSC_MODE_EA (0x3)
73
74 //
75 // RSC Endian bit values
76 //
77 #define RSC_BE_LITTLE 0
78 #define RSC_BE_BIG 1
79
80 //
81 // RSC while in kernel: enabled, little endian, pl = 0, eager mode
82 //
83 #define RSC_KERNEL ((RSC_MODE_EA<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
84 //
85 // Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode
86 //
87 #define RSC_KERNEL_LAZ ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
88 //
89 // RSE disabled: disabled, pl = 0, little endian, eager mode
90 //
91 #define RSC_KERNEL_DISABLED ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
92
93 #endif