MdeModulePkg/Include/Library/PciHostBridgeLib.h

   1 /** @file
   2   PCI Host Bridge Library consumed by PciHostBridgeDxe driver returning
   3   the platform specific information about the PCI Host Bridge.
   4
   5   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
   6   This program and the accompanying materials are
   7   licensed and made available under the terms and conditions of
   8   the BSD License which accompanies this distribution.  The full
   9   text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php.
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16 #ifndef __PCI_HOST_BRIDGE_LIB_H__
  17 #define __PCI_HOST_BRIDGE_LIB_H__
  18
  19 //
  20 // (Base > Limit) indicates an aperture is not available.
  21 //
  22 typedef struct {
  23   //
  24   // Base and Limit are the device address instead of host address when
  25   // Translation is not zero
  26   //
  27   UINT64 Base;
  28   UINT64 Limit;
  29   //
  30   // According to UEFI 2.7, Device Address = Host Address + Translation,
  31   // so Translation = Device Address - Host Address.
  32   // On platforms where Translation is not zero, the subtraction is probably to
  33   // be performed with UINT64 wrap-around semantics, for we may translate an
  34   // above-4G host address into a below-4G device address for legacy PCIe device
  35   // compatibility.
  36   //
  37   // NOTE: The alignment of Translation is required to be larger than any BAR
  38   // alignment in the same root bridge, so that the same alignment can be
  39   // applied to both device address and host address, which simplifies the
  40   // situation and makes the current resource allocation code in generic PCI
  41   // host bridge driver still work.
  42   //
  43   UINT64 Translation;
  44 } PCI_ROOT_BRIDGE_APERTURE;
  45
  46 typedef struct {
  47   UINT32                   Segment;               ///< Segment number.
  48   UINT64                   Supports;              ///< Supported attributes.
  49                                                   ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()
  50                                                   ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  51   UINT64                   Attributes;            ///< Initial attributes.
  52                                                   ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()
  53                                                   ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  54   BOOLEAN                  DmaAbove4G;            ///< DMA above 4GB memory.
  55                                                   ///< Set to TRUE when root bridge supports DMA above 4GB memory.
  56   BOOLEAN                  NoExtendedConfigSpace; ///< When FALSE, the root bridge supports
  57                                                   ///< Extended (4096-byte) Configuration Space.
  58                                                   ///< When TRUE, the root bridge supports
  59                                                   ///< 256-byte Configuration Space only.
  60   BOOLEAN                  ResourceAssigned;      ///< Resource assignment status of the root bridge.
  61                                                   ///< Set to TRUE if Bus/IO/MMIO resources for root bridge have been assigned.
  62   UINT64                   AllocationAttributes;  ///< Allocation attributes.
  63                                                   ///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and
  64                                                   ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()
  65                                                   ///< in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
  66   PCI_ROOT_BRIDGE_APERTURE Bus;                   ///< Bus aperture which can be used by the root bridge.
  67   PCI_ROOT_BRIDGE_APERTURE Io;                    ///< IO aperture which can be used by the root bridge.
  68   PCI_ROOT_BRIDGE_APERTURE Mem;                   ///< MMIO aperture below 4GB which can be used by the root bridge.
  69   PCI_ROOT_BRIDGE_APERTURE MemAbove4G;            ///< MMIO aperture above 4GB which can be used by the root bridge.
  70   PCI_ROOT_BRIDGE_APERTURE PMem;                  ///< Prefetchable MMIO aperture below 4GB which can be used by the root bridge.
  71   PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;           ///< Prefetchable MMIO aperture above 4GB which can be used by the root bridge.
  72   EFI_DEVICE_PATH_PROTOCOL *DevicePath;           ///< Device path.
  73 } PCI_ROOT_BRIDGE;
  74
  75 /**
  76   Return all the root bridge instances in an array.
  77
  78   @param Count  Return the count of root bridge instances.
  79
  80   @return All the root bridge instances in an array.
  81           The array should be passed into PciHostBridgeFreeRootBridges()
  82           when it's not used.
  83 **/
  84 PCI_ROOT_BRIDGE *
  85 EFIAPI
  86 PciHostBridgeGetRootBridges (
  87   UINTN *Count
  88   );
  89
  90 /**
  91   Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
  92
  93   @param Bridges The root bridge instances array.
  94   @param Count   The count of the array.
  95 **/
  96 VOID
  97 EFIAPI
  98 PciHostBridgeFreeRootBridges (
  99   PCI_ROOT_BRIDGE *Bridges,
 100   UINTN           Count
 101   );
 102
 103 /**
 104   Inform the platform that the resource conflict happens.
 105
 106   @param HostBridgeHandle Handle of the Host Bridge.
 107   @param Configuration    Pointer to PCI I/O and PCI memory resource descriptors.
 108                           The Configuration contains the resources for all the
 109                           root bridges. The resource for each root bridge is
 110                           terminated with END descriptor and an additional END
 111                           is appended indicating the end of the entire resources.
 112                           The resource descriptor field values follow the description
 113                           in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.SubmitResources().
 114 **/
 115 VOID
 116 EFIAPI
 117 PciHostBridgeResourceConflict (
 118   EFI_HANDLE           HostBridgeHandle,
 119   VOID                 *Configuration
 120   );
 121
 122 #endif