MdeModulePkg/Include/Ppi/AtaController.h

   1 /** @file
   2   Define the PPI to abstract the functions that enable IDE and SATA channels, and to retrieve
   3   the base I/O port address for each of the enabled IDE and SATA channels.
   4
   5 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   6
   7 SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 #ifndef _PEI_ATA_CONTROLLER_PPI_H_
  12 #define _PEI_ATA_CONTROLLER_PPI_H_
  13
  14 ///
  15 /// Global ID for the PEI_ATA_CONTROLLER_PPI.
  16 ///
  17 #define PEI_ATA_CONTROLLER_PPI_GUID \
  18   { \
  19     0xa45e60d1, 0xc719, 0x44aa, {0xb0, 0x7a, 0xaa, 0x77, 0x7f, 0x85, 0x90, 0x6d } \
  20   }
  21
  22 ///
  23 /// Forward declaration for the PEI_ATA_CONTROLLER_PPI.
  24 ///
  25 typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI;
  26
  27 ///
  28 /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
  29 /// disable the IDE channels.
  30 /// This is designed for old generation chipset with PATA/SATA controllers.
  31 /// It may be ignored in PPI implementation for new generation chipset without PATA controller.
  32 ///
  33 #define PEI_ICH_IDE_NONE        0x00
  34
  35 ///
  36 /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
  37 /// enable the Primary IDE channel.
  38 /// This is designed for old generation chipset with PATA/SATA controllers.
  39 /// It may be ignored in PPI implementation for new generation chipset without PATA controller.
  40 ///
  41 #define PEI_ICH_IDE_PRIMARY     0x01
  42
  43 ///
  44 /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
  45 /// enable the Secondary IDE channel.
  46 /// This is designed for old generation chipset with PATA/SATA controllers.
  47 /// It may be ignored in PPI implementation for new generation chipset without PATA controller.
  48 ///
  49 #define PEI_ICH_IDE_SECONDARY   0x02
  50
  51 ///
  52 /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
  53 /// disable the SATA channel.
  54 /// This is designed for old generation chipset with PATA/SATA controllers.
  55 /// It may be ignored in PPI implementation for new generation chipset without PATA controller.
  56 ///
  57 #define PEI_ICH_SATA_NONE       0x04
  58
  59 ///
  60 /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
  61 /// enable the Primary SATA channel.
  62 /// This is designed for old generation chipset with PATA/SATA controllers.
  63 /// It may be ignored in PPI implementation for new generation chipset without PATA controller.
  64 ///
  65 #define PEI_ICH_SATA_PRIMARY    0x08
  66
  67 ///
  68 /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to
  69 /// enable the Secondary SATA channel.
  70 /// This is designed for old generation chipset with PATA/SATA controllers.
  71 /// It may be ignored in PPI implementation for new generation chipset without PATA controller.
  72 ///
  73 #define PEI_ICH_SATA_SECONDARY  0x010
  74
  75 ///
  76 /// Structure that contains the base addresses for the IDE registers
  77 ///
  78 typedef struct {
  79   ///
  80   /// Base I/O port address of the IDE controller's command block
  81   ///
  82   UINT16  CommandBlockBaseAddr;
  83   ///
  84   /// Base I/O port address of the IDE controller's control block
  85   ///
  86   UINT16  ControlBlockBaseAddr;
  87 } IDE_REGS_BASE_ADDR;
  88
  89 /**
  90   Sets IDE and SATA channels to an enabled or disabled state.
  91
  92   This service enables or disables the IDE and SATA channels specified by ChannelMask.
  93   It may ignore ChannelMask setting to enable or disable IDE and SATA channels based on the platform policy.
  94   The number of the enabled channels will be returned by GET_IDE_REGS_BASE_ADDR() function.
  95
  96   If the new state is set, then EFI_SUCCESS is returned.  If the new state can
  97   not be set, then EFI_DEVICE_ERROR is returned.
  98
  99   @param[in] PeiServices   The pointer to the PEI Services Table.
 100   @param[in] This          The pointer to this instance of the PEI_ATA_CONTROLLER_PPI.
 101   @param[in] ChannelMask   The bitmask that identifies the IDE and SATA channels to
 102                            enable or disable. This parameter is optional.
 103
 104   @retval EFI_SUCCESS        The IDE or SATA channels were enabled or disabled successfully.
 105   @retval EFI_DEVICE_ERROR   The IDE or SATA channels could not be enabled or disabled.
 106
 107 **/
 108 typedef
 109 EFI_STATUS
 110 (EFIAPI *PEI_ENABLE_ATA)(
 111   IN EFI_PEI_SERVICES        **PeiServices,
 112   IN PEI_ATA_CONTROLLER_PPI  *This,
 113   IN UINT8                   ChannelMask
 114   );
 115
 116 /**
 117   Retrieves the I/O port base addresses for command and control registers of the
 118   enabled IDE/SATA channels.
 119
 120   This service fills in the structure poionted to by IdeRegsBaseAddr with the I/O
 121   port base addresses for the command and control registers of the IDE and SATA
 122   channels that were previously enabled in EnableAtaChannel().  The number of
 123   enabled IDE and SATA channels is returned.
 124
 125   @param[in]  PeiServices       The pointer to the PEI Services Table.
 126   @param[in]  This              The pointer to this instance of the PEI_ATA_CONTROLLER_PPI.
 127   @param[out] IdeRegsBaseAddr   The pointer to caller allocated space to return the
 128                                 I/O port base addresses of the IDE and SATA channels
 129                                 that were previosuly enabled with EnableAtaChannel().
 130
 131   @return   The number of enabled IDE and SATA channels in the platform.
 132
 133 **/
 134 typedef
 135 UINT32
 136 (EFIAPI *GET_IDE_REGS_BASE_ADDR)(
 137   IN  EFI_PEI_SERVICES        **PeiServices,
 138   IN  PEI_ATA_CONTROLLER_PPI  *This,
 139   OUT IDE_REGS_BASE_ADDR      *IdeRegsBaseAddr
 140   );
 141
 142 ///
 143 /// This PPI contains services to enable and disable IDE and SATA channels and
 144 /// retrieves the base I/O port addresses to the enabled IDE and SATA channels.
 145 ///
 146 struct _PEI_ATA_CONTROLLER_PPI {
 147   PEI_ENABLE_ATA          EnableAtaChannel;
 148   GET_IDE_REGS_BASE_ADDR  GetIdeRegsBaseAddr;
 149 };
 150
 151 extern EFI_GUID gPeiAtaControllerPpiGuid;
 152
 153 #endif
 154
 155