MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c

   1 /** @file
   2   Set a IDT entry for debug purpose
   3
   4   Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform
   5
   6 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
   7
   8 This program and the accompanying materials
   9 are licensed and made available under the terms and conditions of the BSD License
  10 which accompanies this distribution.  The full text of the license may be found at
  11 http://opensource.org/licenses/bsd-license.php
  12
  13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  15
  16 **/
  17 #include "ScriptExecute.h"
  18
  19 #define IA32_PG_P                   BIT0
  20 #define IA32_PG_RW                  BIT1
  21 #define IA32_PG_PS                  BIT7
  22
  23 UINT64                             mPhyMask;
  24 BOOLEAN                            mPage1GSupport;
  25 VOID                               *mOriginalHandler;
  26 UINTN                              mS3NvsPageTableAddress;
  27
  28 /**
  29   Page fault handler.
  30
  31 **/
  32 VOID
  33 EFIAPI
  34 PageFaultHandlerHook (
  35   VOID
  36   );
  37
  38 /**
  39   Hook IDT with our page fault handler so that the on-demand paging works on page fault.
  40
  41   @param  IdtEntry  a pointer to IDT entry
  42
  43 **/
  44 VOID
  45 HookPageFaultHandler (
  46   IN IA32_IDT_GATE_DESCRIPTOR                   *IdtEntry
  47   )
  48 {
  49   UINT32         RegEax;
  50   UINT32         RegEdx;
  51
  52   AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
  53   mPhyMask = LShiftU64 (1, (UINT8)RegEax) - 1;
  54   mPhyMask &= (1ull << 48) - SIZE_4KB;
  55
  56   mPage1GSupport = FALSE;
  57   if (PcdGetBool(PcdUse1GPageTable)) {
  58     AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
  59     if (RegEax >= 0x80000001) {
  60       AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
  61       if ((RegEdx & BIT26) != 0) {
  62         mPage1GSupport = TRUE;
  63       }
  64     }
  65   }
  66
  67   //
  68   // Set Page Fault entry to catch >4G access
  69   //
  70   mOriginalHandler = (VOID *)(UINTN)(LShiftU64 (IdtEntry->Bits.OffsetUpper, 32) + IdtEntry->Bits.OffsetLow + (IdtEntry->Bits.OffsetHigh << 16));
  71   IdtEntry->Bits.OffsetLow      = (UINT16)((UINTN)PageFaultHandlerHook);
  72   IdtEntry->Bits.Selector       = (UINT16)AsmReadCs ();
  73   IdtEntry->Bits.Reserved_0     = 0;
  74   IdtEntry->Bits.GateType       = IA32_IDT_GATE_TYPE_INTERRUPT_32;
  75   IdtEntry->Bits.OffsetHigh     = (UINT16)((UINTN)PageFaultHandlerHook >> 16);
  76   IdtEntry->Bits.OffsetUpper    = (UINT32)((UINTN)PageFaultHandlerHook >> 32);
  77   IdtEntry->Bits.Reserved_1     = 0;
  78
  79   if (mPage1GSupport) {
  80     mS3NvsPageTableAddress = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(2);
  81   }else {
  82     mS3NvsPageTableAddress = (UINTN)(AsmReadCr3 () & mPhyMask) + EFI_PAGES_TO_SIZE(6);
  83   }
  84 }
  85
  86 /**
  87   Set a IDT entry for interrupt vector 3 for debug purpose.
  88
  89   @param  AcpiS3Context  a pointer to a structure of ACPI_S3_CONTEXT
  90
  91 **/
  92 VOID
  93 SetIdtEntry (
  94   IN ACPI_S3_CONTEXT     *AcpiS3Context
  95   )
  96 {
  97   IA32_IDT_GATE_DESCRIPTOR                      *IdtEntry;
  98   IA32_DESCRIPTOR                               *IdtDescriptor;
  99   UINTN                                         S3DebugBuffer;
 100
 101   //
 102   // Restore IDT for debug
 103   //
 104   IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);
 105   AsmWriteIdtr (IdtDescriptor);
 106
 107   //
 108   // Setup the default CPU exception handlers
 109   //
 110   SetupCpuExceptionHandlers ();
 111
 112   DEBUG_CODE (
 113     //
 114     // Update IDT entry INT3 if the instruction is valid in it
 115     //
 116     S3DebugBuffer = (UINTN) (AcpiS3Context->S3DebugBufferAddress);
 117     if (*(UINTN *)S3DebugBuffer != (UINTN) -1) {
 118       IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (3 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));
 119       IdtEntry->Bits.OffsetLow      = (UINT16)S3DebugBuffer;
 120       IdtEntry->Bits.Selector       = (UINT16)AsmReadCs ();
 121       IdtEntry->Bits.Reserved_0     = 0;
 122       IdtEntry->Bits.GateType       = IA32_IDT_GATE_TYPE_INTERRUPT_32;
 123       IdtEntry->Bits.OffsetHigh     = (UINT16)(S3DebugBuffer >> 16);
 124       IdtEntry->Bits.OffsetUpper    = (UINT32)(S3DebugBuffer >> 32);
 125       IdtEntry->Bits.Reserved_1     = 0;
 126     }
 127   );
 128
 129   IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (14 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));
 130   HookPageFaultHandler (IdtEntry);
 131 }
 132
 133 /**
 134   Get new page address.
 135
 136   @param  PageNum  new page number needed
 137
 138   @return new page address
 139 **/
 140 UINTN
 141 GetNewPage (
 142   IN UINTN  PageNum
 143   )
 144 {
 145   UINTN  NewPage;
 146   NewPage = mS3NvsPageTableAddress;
 147   ZeroMem ((VOID *)NewPage, EFI_PAGES_TO_SIZE(PageNum));
 148   mS3NvsPageTableAddress += EFI_PAGES_TO_SIZE(PageNum);
 149   return NewPage;
 150 }
 151
 152 /**
 153   The page fault handler that on-demand read >4G memory/MMIO.
 154
 155   @retval TRUE     The page fault is correctly handled.
 156   @retval FALSE    The page fault is not handled and is passed through to original handler.
 157
 158 **/
 159 BOOLEAN
 160 EFIAPI
 161 PageFaultHandler (
 162   VOID
 163   )
 164 {
 165   UINT64         *PageTable;
 166   UINT64         PFAddress;
 167   UINTN          PTIndex;
 168
 169   PFAddress = AsmReadCr2 ();
 170   DEBUG ((EFI_D_ERROR, "BootScript - PageFaultHandler: Cr2 - %lx\n", PFAddress));
 171
 172   if (PFAddress >= mPhyMask + SIZE_4KB) {
 173     return FALSE;
 174   }
 175   PFAddress &= mPhyMask;
 176
 177   PageTable = (UINT64*)(UINTN)(AsmReadCr3 () & mPhyMask);
 178
 179   PTIndex = BitFieldRead64 (PFAddress, 39, 47);
 180   // PML4E
 181   if ((PageTable[PTIndex] & IA32_PG_P) == 0) {
 182     PageTable[PTIndex] = GetNewPage (1) | IA32_PG_P | IA32_PG_RW;
 183   }
 184   PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask);
 185   PTIndex = BitFieldRead64 (PFAddress, 30, 38);
 186   // PDPTE
 187   if (mPage1GSupport) {
 188     PageTable[PTIndex] = PFAddress | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;
 189   } else {
 190     if ((PageTable[PTIndex] & IA32_PG_P) == 0) {
 191       PageTable[PTIndex] = GetNewPage (1) | IA32_PG_P | IA32_PG_RW;
 192     }
 193     PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask);
 194     PTIndex = BitFieldRead64 (PFAddress, 21, 29);
 195     // PD
 196     PageTable[PTIndex] = PFAddress | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;
 197   }
 198
 199   return TRUE;
 200 }