MdeModulePkg/Universal/CapsulePei/Capsule.h

   1 /** @file
   2
   3 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   4
   5 SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #ifndef _CAPSULE_PEIM_H_
  10 #define _CAPSULE_PEIM_H_
  11
  12 #include <PiPei.h>
  13 #include <Uefi/UefiSpec.h>
  14
  15 #include <Ppi/Capsule.h>
  16 #include <Ppi/LoadFile.h>
  17 #include <Ppi/ReadOnlyVariable2.h>
  18 #include <Guid/CapsuleVendor.h>
  19
  20 #include <Library/BaseLib.h>
  21 #include <Library/DebugLib.h>
  22 #include <Library/PeimEntryPoint.h>
  23 #include <Library/PeiServicesLib.h>
  24 #include <Library/BaseMemoryLib.h>
  25 #include <Library/HobLib.h>
  26 #include <Library/PeiServicesTablePointerLib.h>
  27 #include <Library/PrintLib.h>
  28 #include <Library/PeCoffLib.h>
  29 #include <Library/PeCoffGetEntryPointLib.h>
  30 #include <Library/PcdLib.h>
  31 #include <Library/ReportStatusCodeLib.h>
  32 #include <Library/DebugAgentLib.h>
  33 #include <IndustryStandard/PeImage.h>
  34 #include "Common/CommonHeader.h"
  35
  36 #ifdef MDE_CPU_IA32
  37
  38 #pragma pack(1)
  39
  40 //
  41 // Page-Map Level-4 Offset (PML4) and
  42 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
  43 //
  44
  45 typedef union {
  46   struct {
  47     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  48     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  49     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  50     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  51     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  52     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  53     UINT64  Reserved:1;               // Reserved
  54     UINT64  MustBeZero:2;             // Must Be Zero
  55     UINT64  Available:3;              // Available for use by system software
  56     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  57     UINT64  AvabilableHigh:11;        // Available for use by system software
  58     UINT64  Nx:1;                     // No Execute bit
  59   } Bits;
  60   UINT64    Uint64;
  61 } PAGE_MAP_AND_DIRECTORY_POINTER;
  62
  63 //
  64 // Page Table Entry 2MB
  65 //
  66 typedef union {
  67   struct {
  68     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  69     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  70     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  71     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  72     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  73     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  74     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
  75     UINT64  MustBe1:1;                // Must be 1
  76     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
  77     UINT64  Available:3;              // Available for use by system software
  78     UINT64  PAT:1;                    //
  79     UINT64  MustBeZero:8;             // Must be zero;
  80     UINT64  PageTableBaseAddress:31;  // Page Table Base Address
  81     UINT64  AvabilableHigh:11;        // Available for use by system software
  82     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
  83   } Bits;
  84   UINT64    Uint64;
  85 } PAGE_TABLE_ENTRY;
  86
  87 //
  88 // Page Table Entry 1GB
  89 //
  90 typedef union {
  91   struct {
  92     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  93     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  94     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  95     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  96     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  97     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  98     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
  99     UINT64  MustBe1:1;                // Must be 1
 100     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
 101     UINT64  Available:3;              // Available for use by system software
 102     UINT64  PAT:1;                    //
 103     UINT64  MustBeZero:17;            // Must be zero;
 104     UINT64  PageTableBaseAddress:22;  // Page Table Base Address
 105     UINT64  AvabilableHigh:11;        // Available for use by system software
 106     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
 107   } Bits;
 108   UINT64    Uint64;
 109 } PAGE_TABLE_1G_ENTRY;
 110
 111 #pragma pack()
 112
 113 typedef
 114 EFI_STATUS
 115 (*COALESCE_ENTRY) (
 116   SWITCH_32_TO_64_CONTEXT       *EntrypointContext,
 117   SWITCH_64_TO_32_CONTEXT       *ReturnContext
 118   );
 119
 120 #endif
 121
 122 #endif