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1 /// @file
2 /// Low level IPF routines used by the debug support driver
3 ///
4 /// Copyright (c) 2006, Intel Corporation
5 /// All rights reserved. This program and the accompanying materials
6 /// are licensed and made available under the terms and conditions of the BSD License
7 /// which accompanies this distribution. The full text of the license may be found at
8 /// http://opensource.org/licenses/bsd-license.php
9 ///
10 /// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 /// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 ///
13 /// Module Name: AsmFuncs.s
14 ///
15 ///
16
17
18 #include "common.i"
19 #include "Ds64Macros.i"
20
21 .globl PatchSaveBuffer
22 .globl IpfContextBuf
23 .globl CommonHandler
24 .globl ExternalInterruptCount
25
26
27 /////////////////////////////////////////////
28 //
29 // Name:
30 // InstructionCacheFlush
31 //
32 // Description:
33 // Flushes instruction cache for specified number of bytes
34 //
35 .globl InstructionCacheFlush
36 .proc InstructionCacheFlush
37 .align 32
38 InstructionCacheFlush::
39 { .mii
40 alloc r3=2, 0, 0, 0
41 cmp4.leu p0,p6=32, r33;;
42 (p6) mov r33=32;;
43 }
44 { .mii
45 nop.m 0
46 zxt4 r29=r33;;
47 dep.z r30=r29, 0, 5;;
48 }
49 { .mii
50 cmp4.eq p0,p7=r0, r30
51 shr.u r28=r29, 5;;
52 (p7) adds r28=1, r28;;
53 }
54 { .mii
55 nop.m 0
56 shl r27=r28, 5;;
57 zxt4 r26=r27;;
58 }
59 { .mfb
60 add r31=r26, r32
61 nop.f 0
62 nop.b 0
63 }
64 LoopBack: // $L143:
65 { .mii
66 fc r32
67 adds r32=32, r32;;
68 cmp.ltu p14,p15=r32, r31
69 }
70 { .mfb
71 nop.m 0
72 nop.f 0
73 //(p14) br.cond.dptk.few $L143#;;
74 (p14) br.cond.dptk.few LoopBack;;
75 }
76 { .mmi
77 sync.i;;
78 srlz.i
79 nop.i 0;;
80 }
81 { .mfb
82 nop.m 0
83 nop.f 0
84 br.ret.sptk.few b0;;
85 }
86 .endp InstructionCacheFlush
87
88
89 /////////////////////////////////////////////
90 //
91 // Name:
92 // ChainHandler
93 //
94 // Description:
95 // Chains an interrupt handler
96 //
97 // The purpose of this function is to enable chaining of the external interrupt.
98 // Since there's no clean SAL abstraction for doing this, we must do it
99 // surreptitiously.
100 //
101 // The reserved IVT entry at offset 0x3400 is coopted for use by this handler.
102 // According to Itanium architecture, it is reserved. Strictly speaking, this is
103 // not safe, as we're cheating and violating the Itanium architecture. However,
104 // as long as we're the only ones cheating, we should be OK. Without hooks in
105 // the SAL to enable IVT management, there aren't many good options.
106 //
107 // The strategy is to replace the first bundle of the external interrupt handler
108 // with our own that will branch into a piece of code we've supplied and located
109 // in the reserved IVT entry. Only the first bundle of the external interrupt
110 // IVT entry is modified.
111 //
112 // The original bundle is moved and relocated to space
113 // allocated within the reserved IVT entry. The next bundle following is
114 // is generated to go a hard coded branch back to the second bundle of the
115 // external interrupt IVT entry just in case the first bundle had no branch.
116 //
117 // Our new code will execute our handler, and then fall through to the
118 // original bundle after restoring all context appropriately.
119 //
120 // The following is a representation of what the IVT memory map looks like with
121 // our chained handler installed:
122 //
123 //
124 //
125 //
126 //
127 // This IVT entry is Failsafe bundle
128 // reserved by the
129 // Itanium architecture Original bundle 0
130 // and is used for
131 // for locating our
132 // handler and the
133 // original bundle Patch code...
134 // zero of the ext
135 // interrupt handler
136 //
137 // RSVD (3400) Unused
138 //
139 //
140 //
141 //
142 //
143 //
144 //
145 //
146 //
147 //
148 //
149 //
150 // EXT_INT (3000) Bundle 0 Bundle zero - This one is
151 // modified, all other bundles
152 // in the EXT_INT entry are
153 // untouched.
154 //
155 //
156 // Arguments:
157 //
158 // Returns:
159 //
160 // Notes:
161 //
162 //
163 .globl ChainHandler
164 .proc ChainHandler
165 ChainHandler:
166
167 NESTED_SETUP( 0,2+3,3,0 )
168
169 mov r8=1 // r8 = success
170 mov r2=cr.iva;;
171 //
172 // NOTE: There's a potential hazard here in that we're simply stealing a bunch of
173 // bundles (memory) from the IVT and assuming there's no catastrophic side effect.
174 //
175 // First, save IVT area we're taking over with the patch so we can restore it later
176 //
177 addl out0=PATCH_ENTRY_OFFSET, r2 // out0 = source buffer
178 movl out1=PatchSaveBuffer // out1 = destination buffer
179 mov out2=0x40;; // out2 = number of bundles to copy... save entire IDT entry
180 br.call.sptk.few b0 = CopyBundles
181
182 // Next, copy the patch code into the IVT
183 movl out0=PatchCode // out0 = source buffer of patch code
184 addl out1=PATCH_OFFSET, r2 // out1 = destination buffer - in IVT
185 mov out2=NUM_PATCH_BUNDLES;; // out2 = number of bundles to copy
186 br.call.sptk.few b0 = CopyBundles
187
188
189 // copy original bundle 0 from the external interrupt handler to the
190 // appropriate place in the reserved IVT interrupt slot
191 addl out0=EXT_INT_ENTRY_OFFSET, r2 // out0 = source buffer
192 addl out1=RELOCATED_EXT_INT, r2 // out1 = destination buffer - in reserved IVT
193 mov out2=1;; // out2 = copy 1 bundle
194 br.call.sptk.few b0 = CopyBundles
195
196 // Now relocate it there because it very likely had a branch instruction that
197 // that must now be fixed up.
198 addl out0=RELOCATED_EXT_INT, r2 // out0 = new runtime address of bundle - in reserved IVT
199 addl out1=EXT_INT_ENTRY_OFFSET, r2;;// out1 = IP address of previous location
200 mov out2=out0;; // out2 = IP address of new location
201 br.call.sptk.few b0 = RelocateBundle
202
203 // Now copy into the failsafe branch into the next bundle just in case
204 // the original ext int bundle 0 bundle did not contain a branch instruction
205 movl out0=FailsafeBranch // out0 = source buffer
206 addl out1=FAILSAFE_BRANCH_OFFSET, r2 // out1 = destination buffer - in reserved IVT
207 mov out2=1;; // out2 = copy 1 bundle
208 br.call.sptk.few b0 = CopyBundles
209
210 // Last, copy in our replacement for the external interrupt IVT entry bundle 0
211 movl out0=PatchCodeNewBun0 // out0 = source buffer - our replacement bundle 0
212 addl out1=EXT_INT_ENTRY_OFFSET, r2 // out1 = destination buffer - bundle 0 of External interrupt entry
213 mov out2=1;; // out2 = copy 1 bundle
214 br.call.sptk.few b0 = CopyBundles
215
216 ChainHandlerDone:
217 NESTED_RETURN
218
219 .endp ChainHandler
220
221
222 /////////////////////////////////////////////
223 //
224 // Name:
225 // UnchainHandler
226 //
227 // Description:
228 // Unchains an interrupt handler
229 //
230 // Arguments:
231 //
232 // Returns:
233 //
234 // Notes:
235 //
236 //
237 .globl UnchainHandler
238 .proc UnchainHandler
239
240 UnchainHandler:
241
242 NESTED_SETUP( 0,2+3,3,0 )
243
244 mov r8=1 // r8 = success
245 mov r2=cr.iva;; // r2 = interrupt vector address
246
247 // First copy original Ext Int bundle 0 back to it's proper home...
248 addl out0=RELOCATED_EXT_INT, r2 // out0 = source - in reserved IVT
249 addl out1=EXT_INT_ENTRY_OFFSET, r2 // out1 = destination buffer - first bundle of Ext Int entry
250 mov out2=1;; // out2 = copy 1 bundle
251 br.call.sptk.few b0 = CopyBundles
252
253 // Now, relocate it again...
254 addl out0=EXT_INT_ENTRY_OFFSET, r2 // out1 = New runtime address
255 addl out1=RELOCATED_EXT_INT, r2;; // out0 = IP address of previous location
256 mov out2=out0;; // out2 = IP address of new location
257 br.call.sptk.few b0 = RelocateBundle
258
259 // Last, restore the patch area
260 movl out0=PatchSaveBuffer // out0 = source buffer
261 addl out1=PATCH_ENTRY_OFFSET, r2 // out1 = destination buffer
262 mov out2=0x40;; // out2 = number of bundles to copy... save entire IDT entry
263 br.call.sptk.few b0 = CopyBundles
264
265 UnchainHandlerDone:
266 NESTED_RETURN
267
268 .endp UnchainHandler
269
270
271 /////////////////////////////////////////////
272 //
273 // Name:
274 // CopyBundles
275 //
276 // Description:
277 // Copies instruction bundles - flushes icache as necessary
278 //
279 // Arguments:
280 // in0 - Bundle source
281 // in1 - Bundle destination
282 // in2 - Bundle count
283 //
284 // Returns:
285 //
286 // Notes:
287 // This procedure is a leaf routine
288 //
289 .proc CopyBundles
290
291 CopyBundles:
292
293 NESTED_SETUP(3,2+1,0,0)
294
295 shl in2=in2, 1;; // in2 = count of 8 byte blocks to copy
296
297 CopyBundlesLoop:
298
299 cmp.eq p14, p15 = 0, in2;; // Check if done
300 (p14) br.sptk.few CopyBundlesDone;;
301
302 ld8 loc2=[in0], 0x8;; // loc2 = source bytes
303 st8 [in1]=loc2;; // [in1] = destination bytes
304 fc in1;; // Flush instruction cache
305 sync.i;; // Ensure local and remote data/inst caches in sync
306 srlz.i;; // Ensure sync has been observed
307 add in1=0x8, in1;; // in1 = next destination
308 add in2=-1, in2;; // in2 = decrement 8 bytes blocks to copy
309 br.sptk.few CopyBundlesLoop;;
310
311 CopyBundlesDone:
312 NESTED_RETURN
313
314 .endp CopyBundles
315
316
317 /////////////////////////////////////////////
318 //
319 // Name:
320 // RelocateBundle
321 //
322 // Description:
323 // Relocates an instruction bundle by updating any ip-relative branch instructions.
324 //
325 // Arguments:
326 // in0 - Runtime address of bundle
327 // in1 - IP address of previous location of bundle
328 // in2 - IP address of new location of bundle
329 //
330 // Returns:
331 // in0 - 1 if successful or 0 if unsuccessful
332 //
333 // Notes:
334 // This routine examines all slots in the given bundle that are destined for the
335 // branch execution unit. If any of these slots contain an IP-relative branch
336 // namely instructions B1, B2, B3, or B6, the slot is fixed-up with a new relative
337 // address. Errors can occur if a branch cannot be reached.
338 //
339 .proc RelocateBundle
340
341 RelocateBundle:
342
343 NESTED_SETUP(3,2+4,3,0)
344
345 mov loc2=SLOT0 // loc2 = slot index
346 mov loc5=in0;; // loc5 = runtime address of bundle
347 mov in0=1;; // in0 = success
348
349 RelocateBundleNextSlot:
350
351 cmp.ge p14, p15 = SLOT2, loc2;; // Check if maximum slot
352 (p15) br.sptk.few RelocateBundleDone
353
354 mov out0=loc5;; // out0 = runtime address of bundle
355 br.call.sptk.few b0 = GetTemplate
356 mov loc3=out0;; // loc3 = instruction template
357 mov out0=loc5 // out0 = runtime address of bundle
358 mov out1=loc2;; // out1 = instruction slot number
359 br.call.sptk.few b0 = GetSlot
360 mov loc4=out0;; // loc4 = instruction encoding
361 mov out0=loc4 // out0 = instuction encoding
362 mov out1=loc2 // out1 = instruction slot number
363 mov out2=loc3;; // out2 = instruction template
364 br.call.sptk.few b0 = IsSlotBranch
365 cmp.eq p14, p15 = 1, out0;; // Check if branch slot
366 (p15) add loc2=1,loc2 // Increment slot
367 (p15) br.sptk.few RelocateBundleNextSlot
368 mov out0=loc4 // out0 = instuction encoding
369 mov out1=in1 // out1 = IP address of previous location
370 mov out2=in2;; // out2 = IP address of new location
371 br.call.sptk.few b0 = RelocateSlot
372 cmp.eq p14, p15 = 1, out1;; // Check if relocated slot
373 (p15) mov in0=0 // in0 = failure
374 (p15) br.sptk.few RelocateBundleDone
375 mov out2=out0;; // out2 = instruction encoding
376 mov out0=loc5 // out0 = runtime address of bundle
377 mov out1=loc2;; // out1 = instruction slot number
378 br.call.sptk.few b0 = SetSlot
379 add loc2=1,loc2;; // Increment slot
380 br.sptk.few RelocateBundleNextSlot
381
382 RelocateBundleDone:
383 NESTED_RETURN
384
385 .endp RelocateBundle
386
387
388 /////////////////////////////////////////////
389 //
390 // Name:
391 // RelocateSlot
392 //
393 // Description:
394 // Relocates an instruction bundle by updating any ip-relative branch instructions.
395 //
396 // Arguments:
397 // in0 - Instruction encoding (41-bits, right justified)
398 // in1 - IP address of previous location of bundle
399 // in2 - IP address of new location of bundle
400 //
401 // Returns:
402 // in0 - Instruction encoding (41-bits, right justified)
403 // in1 - 1 if successful otherwise 0
404 //
405 // Notes:
406 // This procedure is a leaf routine
407 //
408 .proc RelocateSlot
409
410 RelocateSlot:
411 NESTED_SETUP(3,2+5,0,0)
412 extr.u loc2=in0, 37, 4;; // loc2 = instruction opcode
413 cmp.eq p14, p15 = 4, loc2;; // IP-relative branch (B1) or
414 // IP-relative counted branch (B2)
415 (p15) cmp.eq p14, p15 = 5, loc2;; // IP-relative call (B3)
416 (p15) cmp.eq p14, p15 = 7, loc2;; // IP-relative predict (B6)
417 (p15) mov in1=1 // Instruction did not need to be reencoded
418 (p15) br.sptk.few RelocateSlotDone
419 tbit.nz p14, p15 = in0, 36;; // put relative offset sign bit in p14
420 extr.u loc2=in0, 13, 20;; // loc2 = relative offset in instruction
421 (p14) movl loc3=0xfffffffffff00000;; // extend sign
422 (p14) or loc2=loc2, loc3;;
423 shl loc2=loc2,4;; // convert to byte offset instead of bundle offset
424 add loc3=loc2, in1;; // loc3 = physical address of branch target
425 (p14) sub loc2=r0,loc2;; // flip sign in loc2 if offset is negative
426 sub loc4=loc3,in2;; // loc4 = relative offset from new ip to branch target
427 cmp.lt p15, p14 = 0, loc4;; // get new sign bit
428 (p14) sub loc5=r0,loc4 // get absolute value of offset
429 (p15) mov loc5=loc4;;
430 movl loc6=0x0FFFFFF;; // maximum offset in bytes for ip-rel branch
431 cmp.gt p14, p15 = loc5, loc6;; // check to see we're not out of range for an ip-relative branch
432 (p14) br.sptk.few RelocateSlotError
433 cmp.lt p15, p14 = 0, loc4;; // store sign in p14 again
434 (p14) dep in0=1,in0,36,1 // store sign bit in instruction
435 (p15) dep in0=0,in0,36,1
436 shr loc4=loc4, 4;; // convert back to bundle offset
437 dep in0=loc4,in0,13,16;; // put first 16 bits of new offset into instruction
438 shr loc4=loc4,16;;
439 dep in0=loc4,in0,13+16,4 // put last 4 bits of new offset into instruction
440 mov in1=1;; // in1 = success
441 br.sptk.few RelocateSlotDone;;
442
443 RelocateSlotError:
444 mov in1=0;; // in1 = failure
445
446 RelocateSlotDone:
447 NESTED_RETURN
448
449 .endp RelocateSlot
450
451
452 /////////////////////////////////////////////
453 //
454 // Name:
455 // IsSlotBranch
456 //
457 // Description:
458 // Determines if the given instruction is a branch instruction.
459 //
460 // Arguments:
461 // in0 - Instruction encoding (41-bits, right justified)
462 // in1 - Instruction slot number
463 // in2 - Bundle template
464 //
465 // Returns:
466 // in0 - 1 if branch or 0 if not branch
467 //
468 // Notes:
469 // This procedure is a leaf routine
470 //
471 // IsSlotBranch recognizes all branch instructions by looking at the provided template.
472 // The instruction encoding is only passed to this routine for future expansion.
473 //
474 .proc IsSlotBranch
475
476 IsSlotBranch:
477
478 NESTED_SETUP (3,2+0,0,0)
479
480 mov in0=1;; // in0 = 1 which destroys the instruction
481 andcm in2=in2,in0;; // in2 = even template to reduce compares
482 mov in0=0;; // in0 = not a branch
483 cmp.eq p14, p15 = 0x16, in2;; // Template 0x16 is BBB
484 (p14) br.sptk.few IsSlotBranchTrue
485 cmp.eq p14, p15 = SLOT0, in1;; // Slot 0 has no other possiblities
486 (p14) br.sptk.few IsSlotBranchDone
487 cmp.eq p14, p15 = 0x12, in2;; // Template 0x12 is MBB
488 (p14) br.sptk.few IsSlotBranchTrue
489 cmp.eq p14, p15 = SLOT1, in1;; // Slot 1 has no other possiblities
490 (p14) br.sptk.few IsSlotBranchDone
491 cmp.eq p14, p15 = 0x10, in2;; // Template 0x10 is MIB
492 (p14) br.sptk.few IsSlotBranchTrue
493 cmp.eq p14, p15 = 0x18, in2;; // Template 0x18 is MMB
494 (p14) br.sptk.few IsSlotBranchTrue
495 cmp.eq p14, p15 = 0x1C, in2;; // Template 0x1C is MFB
496 (p14) br.sptk.few IsSlotBranchTrue
497 br.sptk.few IsSlotBranchDone
498
499 IsSlotBranchTrue:
500 mov in0=1;; // in0 = branch
501
502 IsSlotBranchDone:
503 NESTED_RETURN
504
505 .endp IsSlotBranch
506
507
508 /////////////////////////////////////////////
509 //
510 // Name:
511 // GetTemplate
512 //
513 // Description:
514 // Retrieves the instruction template for an instruction bundle
515 //
516 // Arguments:
517 // in0 - Runtime address of bundle
518 //
519 // Returns:
520 // in0 - Instruction template (5-bits, right-justified)
521 //
522 // Notes:
523 // This procedure is a leaf routine
524 //
525 .proc GetTemplate
526
527 GetTemplate:
528
529 NESTED_SETUP (1,2+2,0,0)
530
531 ld8 loc2=[in0], 0x8 // loc2 = first 8 bytes of branch bundle
532 movl loc3=MASK_0_4;; // loc3 = template mask
533 and loc2=loc2,loc3;; // loc2 = template, right justified
534 mov in0=loc2;; // in0 = template, right justified
535
536 NESTED_RETURN
537
538 .endp GetTemplate
539
540
541 /////////////////////////////////////////////
542 //
543 // Name:
544 // GetSlot
545 //
546 // Description:
547 // Gets the instruction encoding for an instruction slot and bundle
548 //
549 // Arguments:
550 // in0 - Runtime address of bundle
551 // in1 - Instruction slot (either 0, 1, or 2)
552 //
553 // Returns:
554 // in0 - Instruction encoding (41-bits, right justified)
555 //
556 // Notes:
557 // This procedure is a leaf routine
558 //
559 // Slot0 - [in0 + 0x8] Bits 45-5
560 // Slot1 - [in0 + 0x8] Bits 63-46 and [in0] Bits 22-0
561 // Slot2 - [in0] Bits 63-23
562 //
563 .proc GetSlot
564
565 GetSlot:
566 NESTED_SETUP (2,2+3,0,0)
567
568 ld8 loc2=[in0], 0x8;; // loc2 = first 8 bytes of branch bundle
569 ld8 loc3=[in0];; // loc3 = second 8 bytes of branch bundle
570 cmp.eq p14, p15 = 2, in1;; // check if slot 2 specified
571 (p14) br.cond.sptk.few GetSlot2;; // get slot 2
572 cmp.eq p14, p15 = 1, in1;; // check if slot 1 specified
573 (p14) br.cond.sptk.few GetSlot1;; // get slot 1
574
575 GetSlot0:
576 extr.u in0=loc2, 5, 45 // in0 = extracted slot 0
577 br.sptk.few GetSlotDone;;
578
579 GetSlot1:
580 extr.u in0=loc2, 46, 18 // in0 = bits 63-46 of loc2 right-justified
581 extr.u loc4=loc3, 0, 23;; // loc4 = bits 22-0 of loc3 right-justified
582 dep in0=loc4, in0, 18, 15;;
583 shr.u loc4=loc4,15;;
584 dep in0=loc4, in0, 33, 8;; // in0 = extracted slot 1
585 br.sptk.few GetSlotDone;;
586
587 GetSlot2:
588 extr.u in0=loc3, 23, 41;; // in0 = extracted slot 2
589
590 GetSlotDone:
591 NESTED_RETURN
592
593 .endp GetSlot
594
595
596 /////////////////////////////////////////////
597 //
598 // Name:
599 // SetSlot
600 //
601 // Description:
602 // Sets the instruction encoding for an instruction slot and bundle
603 //
604 // Arguments:
605 // in0 - Runtime address of bundle
606 // in1 - Instruction slot (either 0, 1, or 2)
607 // in2 - Instruction encoding (41-bits, right justified)
608 //
609 // Returns:
610 //
611 // Notes:
612 // This procedure is a leaf routine
613 //
614 .proc SetSlot
615
616 SetSlot:
617 NESTED_SETUP (3,2+3,0,0)
618
619 ld8 loc2=[in0], 0x8;; // loc2 = first 8 bytes of bundle
620 ld8 loc3=[in0];; // loc3 = second 8 bytes of bundle
621 cmp.eq p14, p15 = 2, in1;; // check if slot 2 specified
622 (p14) br.cond.sptk.few SetSlot2;; // set slot 2
623 cmp.eq p14, p15 = 1, in1;; // check if slot 1 specified
624 (p14) br.cond.sptk.few SetSlot1;; // set slot 1
625
626 SetSlot0:
627 dep loc2=0, loc2, 5, 41;; // remove old instruction from slot 0
628 shl loc4=in2, 5;; // loc4 = new instruction ready to be inserted
629 or loc2=loc2, loc4;; // loc2 = updated first 8 bytes of bundle
630 add loc4=0x8,in0;; // loc4 = address to store first 8 bytes of bundle
631 st8 [loc4]=loc2 // [loc4] = updated bundle
632 br.sptk.few SetSlotDone;;
633 ;;
634
635 SetSlot1:
636 dep loc2=0, loc2, 46, 18 // remove old instruction from slot 1
637 dep loc3=0, loc3, 0, 23;;
638 shl loc4=in2, 46;; // loc4 = partial instruction ready to be inserted
639 or loc2=loc2, loc4;; // loc2 = updated first 8 bytes of bundle
640 add loc4=0x8,in0;; // loc4 = address to store first 8 bytes of bundle
641 st8 [loc4]=loc2;; // [loc4] = updated bundle
642 shr.u loc4=in2, 18;; // loc4 = partial instruction ready to be inserted
643 or loc3=loc3, loc4;; // loc3 = updated second 8 bytes of bundle
644 st8 [in0]=loc3;; // [in0] = updated bundle
645 br.sptk.few SetSlotDone;;
646
647 SetSlot2:
648 dep loc3=0, loc3, 23, 41;; // remove old instruction from slot 2
649 shl loc4=in2, 23;; // loc4 = instruction ready to be inserted
650 or loc3=loc3, loc4;; // loc3 = updated second 8 bytes of bundle
651 st8 [in0]=loc3;; // [in0] = updated bundle
652
653 SetSlotDone:
654
655 NESTED_RETURN
656 .endp SetSlot
657
658
659 /////////////////////////////////////////////
660 //
661 // Name:
662 // GetIva
663 //
664 // Description:
665 // C callable function to obtain the current value of IVA
666 //
667 // Returns:
668 // Current value if IVA
669
670 .globl GetIva
671 .proc GetIva
672 GetIva:
673 mov r8=cr2;;
674 br.ret.sptk.many b0
675
676 .endp GetIva
677
678
679 /////////////////////////////////////////////
680 //
681 // Name:
682 // ProgramInterruptFlags
683 //
684 // Description:
685 // C callable function to enable/disable interrupts
686 //
687 // Returns:
688 // Previous state of psr.ic
689 //
690 .globl ProgramInterruptFlags
691 .proc ProgramInterruptFlags
692 ProgramInterruptFlags:
693 alloc loc0=1,2,0,0;;
694 mov loc0=psr
695 mov loc1=0x6000;;
696 and r8=loc0, loc1 // obtain current psr.ic and psr.i state
697 and in0=in0, loc1 // insure no extra bits set in input
698 andcm loc0=loc0,loc1;; // clear original psr.i and psr.ic
699 or loc0=loc0,in0;; // OR in new psr.ic value
700 mov psr.l=loc0;; // write new psr
701 srlz.d
702 br.ret.sptk.many b0 // return
703
704 .endp ProgramInterruptFlags
705
706
707 /////////////////////////////////////////////
708 //
709 // Name:
710 // SpillContext
711 //
712 // Description:
713 // Saves system context to context record.
714 //
715 // Arguments:
716 // in0 = 512 byte aligned context record address
717 // in1 = original B0
718 // in2 = original ar.bsp
719 // in3 = original ar.bspstore
720 // in4 = original ar.rnat
721 // in5 = original ar.pfs
722 //
723 // Notes:
724 // loc0 - scratch
725 // loc1 - scratch
726 // loc2 - temporary application unat storage
727 // loc3 - temporary exception handler unat storage
728
729 .proc SpillContext
730
731 SpillContext:
732 alloc loc0=6,4,0,0;; // alloc 6 input, 4 locals, 0 outs
733 mov loc2=ar.unat;; // save application context unat (spilled later)
734 mov ar.unat=r0;; // set UNAT=0
735 st8.spill [in0]=r0,8;;
736 st8.spill [in0]=r1,8;; // save R1 - R31
737 st8.spill [in0]=r2,8;;
738 st8.spill [in0]=r3,8;;
739 st8.spill [in0]=r4,8;;
740 st8.spill [in0]=r5,8;;
741 st8.spill [in0]=r6,8;;
742 st8.spill [in0]=r7,8;;
743 st8.spill [in0]=r8,8;;
744 st8.spill [in0]=r9,8;;
745 st8.spill [in0]=r10,8;;
746 st8.spill [in0]=r11,8;;
747 st8.spill [in0]=r12,8;;
748 st8.spill [in0]=r13,8;;
749 st8.spill [in0]=r14,8;;
750 st8.spill [in0]=r15,8;;
751 st8.spill [in0]=r16,8;;
752 st8.spill [in0]=r17,8;;
753 st8.spill [in0]=r18,8;;
754 st8.spill [in0]=r19,8;;
755 st8.spill [in0]=r20,8;;
756 st8.spill [in0]=r21,8;;
757 st8.spill [in0]=r22,8;;
758 st8.spill [in0]=r23,8;;
759 st8.spill [in0]=r24,8;;
760 st8.spill [in0]=r25,8;;
761 st8.spill [in0]=r26,8;;
762 st8.spill [in0]=r27,8;;
763 st8.spill [in0]=r28,8;;
764 st8.spill [in0]=r29,8;;
765 st8.spill [in0]=r30,8;;
766 st8.spill [in0]=r31,8;;
767 mov loc3=ar.unat;; // save debugger context unat (spilled later)
768 stf.spill [in0]=f2,16;; // save f2 - f31
769 stf.spill [in0]=f3,16;;
770 stf.spill [in0]=f4,16;;
771 stf.spill [in0]=f5,16;;
772 stf.spill [in0]=f6,16;;
773 stf.spill [in0]=f7,16;;
774 stf.spill [in0]=f8,16;;
775 stf.spill [in0]=f9,16;;
776 stf.spill [in0]=f10,16;;
777 stf.spill [in0]=f11,16;;
778 stf.spill [in0]=f12,16;;
779 stf.spill [in0]=f13,16;;
780 stf.spill [in0]=f14,16;;
781 stf.spill [in0]=f15,16;;
782 stf.spill [in0]=f16,16;;
783 stf.spill [in0]=f17,16;;
784 stf.spill [in0]=f18,16;;
785 stf.spill [in0]=f19,16;;
786 stf.spill [in0]=f20,16;;
787 stf.spill [in0]=f21,16;;
788 stf.spill [in0]=f22,16;;
789 stf.spill [in0]=f23,16;;
790 stf.spill [in0]=f24,16;;
791 stf.spill [in0]=f25,16;;
792 stf.spill [in0]=f26,16;;
793 stf.spill [in0]=f27,16;;
794 stf.spill [in0]=f28,16;;
795 stf.spill [in0]=f29,16;;
796 stf.spill [in0]=f30,16;;
797 stf.spill [in0]=f31,16;;
798 mov loc0=pr;; // save predicates
799 st8.spill [in0]=loc0,8;;
800 st8.spill [in0]=in1,8;; // save b0 - b7... in1 already equals saved b0
801 mov loc0=b1;;
802 st8.spill [in0]=loc0,8;;
803 mov loc0=b2;;
804 st8.spill [in0]=loc0,8;;
805 mov loc0=b3;;
806 st8.spill [in0]=loc0,8;;
807 mov loc0=b4;;
808 st8.spill [in0]=loc0,8;;
809 mov loc0=b5;;
810 st8.spill [in0]=loc0,8;;
811 mov loc0=b6;;
812 st8.spill [in0]=loc0,8;;
813 mov loc0=b7;;
814 st8.spill [in0]=loc0,8;;
815 mov loc0=ar.rsc;; // save ar.rsc
816 st8.spill [in0]=loc0,8;;
817 st8.spill [in0]=in2,8;; // save ar.bsp (in2)
818 st8.spill [in0]=in3,8;; // save ar.bspstore (in3)
819 st8.spill [in0]=in4,8;; // save ar.rnat (in4)
820 mov loc0=ar.fcr;; // save ar.fcr (ar21 - IA32 floating-point control register)
821 st8.spill [in0]=loc0,8;;
822 mov loc0=ar.eflag;; // save ar.eflag (ar24)
823 st8.spill [in0]=loc0,8;;
824 mov loc0=ar.csd;; // save ar.csd (ar25 - ia32 CS descriptor)
825 st8.spill [in0]=loc0,8;;
826 mov loc0=ar.ssd;; // save ar.ssd (ar26 - ia32 ss descriptor)
827 st8.spill [in0]=loc0,8;;
828 mov loc0=ar.cflg;; // save ar.cflg (ar27 - ia32 cr0 and cr4)
829 st8.spill [in0]=loc0,8;;
830 mov loc0=ar.fsr;; // save ar.fsr (ar28 - ia32 floating-point status register)
831 st8.spill [in0]=loc0,8;;
832 mov loc0=ar.fir;; // save ar.fir (ar29 - ia32 floating-point instruction register)
833 st8.spill [in0]=loc0,8;;
834 mov loc0=ar.fdr;; // save ar.fdr (ar30 - ia32 floating-point data register)
835 st8.spill [in0]=loc0,8;;
836 mov loc0=ar.ccv;; // save ar.ccv
837 st8.spill [in0]=loc0,8;;
838 st8.spill [in0]=loc2,8;; // save ar.unat (saved to loc2 earlier)
839 mov loc0=ar.fpsr;; // save floating point status register
840 st8.spill [in0]=loc0,8;;
841 st8.spill [in0]=in5,8;; // save ar.pfs
842 mov loc0=ar.lc;; // save ar.lc
843 st8.spill [in0]=loc0,8;;
844 mov loc0=ar.ec;; // save ar.ec
845 st8.spill [in0]=loc0,8;;
846
847 // save control registers
848 mov loc0=cr.dcr;; // save dcr
849 st8.spill [in0]=loc0,8;;
850 mov loc0=cr.itm;; // save itm
851 st8.spill [in0]=loc0,8;;
852 mov loc0=cr.iva;; // save iva
853 st8.spill [in0]=loc0,8;;
854 mov loc0=cr.pta;; // save pta
855 st8.spill [in0]=loc0,8;;
856 mov loc0=cr.ipsr;; // save ipsr
857 st8.spill [in0]=loc0,8;;
858 mov loc0=cr.isr;; // save isr
859 st8.spill [in0]=loc0,8;;
860 mov loc0=cr.iip;; // save iip
861 st8.spill [in0]=loc0,8;;
862 mov loc0=cr.ifa;; // save ifa
863 st8.spill [in0]=loc0,8;;
864 mov loc0=cr.itir;; // save itir
865 st8.spill [in0]=loc0,8;;
866 mov loc0=cr.iipa;; // save iipa
867 st8.spill [in0]=loc0,8;;
868 mov loc0=cr.ifs;; // save ifs
869 st8.spill [in0]=loc0,8;;
870 mov loc0=cr.iim;; // save iim
871 st8.spill [in0]=loc0,8;;
872 mov loc0=cr.iha;; // save iha
873 st8.spill [in0]=loc0,8;;
874
875 // save debug registers
876 mov loc0=dbr[r0];; // save dbr0 - dbr7
877 st8.spill [in0]=loc0,8;;
878 movl loc1=1;;
879 mov loc0=dbr[loc1];;
880 st8.spill [in0]=loc0,8;;
881 movl loc1=2;;
882 mov loc0=dbr[loc1];;
883 st8.spill [in0]=loc0,8;;
884 movl loc1=3;;
885 mov loc0=dbr[loc1];;
886 st8.spill [in0]=loc0,8;;
887 movl loc1=4;;
888 mov loc0=dbr[loc1];;
889 st8.spill [in0]=loc0,8;;
890 movl loc1=5;;
891 mov loc0=dbr[loc1];;
892 st8.spill [in0]=loc0,8;;
893 movl loc1=6;;
894 mov loc0=dbr[loc1];;
895 st8.spill [in0]=loc0,8;;
896 movl loc1=7;;
897 mov loc0=dbr[loc1];;
898 st8.spill [in0]=loc0,8;;
899 mov loc0=ibr[r0];; // save ibr0 - ibr7
900 st8.spill [in0]=loc0,8;;
901 movl loc1=1;;
902 mov loc0=ibr[loc1];;
903 st8.spill [in0]=loc0,8;;
904 movl loc1=2;;
905 mov loc0=ibr[loc1];;
906 st8.spill [in0]=loc0,8;;
907 movl loc1=3;;
908 mov loc0=ibr[loc1];;
909 st8.spill [in0]=loc0,8;;
910 movl loc1=4;;
911 mov loc0=ibr[loc1];;
912 st8.spill [in0]=loc0,8;;
913 movl loc1=5;;
914 mov loc0=ibr[loc1];;
915 st8.spill [in0]=loc0,8;;
916 movl loc1=6;;
917 mov loc0=ibr[loc1];;
918 st8.spill [in0]=loc0,8;;
919 movl loc1=7;;
920 mov loc0=ibr[loc1];;
921 st8.spill [in0]=loc0,8;;
922 st8.spill [in0]=loc3;;
923
924 br.ret.sptk.few b0
925
926 .endp SpillContext
927
928
929 /////////////////////////////////////////////
930 //
931 // Name:
932 // FillContext
933 //
934 // Description:
935 // Restores register context from context record.
936 //
937 // Arguments:
938 // in0 = address of last element 512 byte aligned context record address
939 // in1 = modified B0
940 // in2 = modified ar.bsp
941 // in3 = modified ar.bspstore
942 // in4 = modified ar.rnat
943 // in5 = modified ar.pfs
944 //
945 // Notes:
946 // loc0 - scratch
947 // loc1 - scratch
948 // loc2 - temporary application unat storage
949 // loc3 - temporary exception handler unat storage
950
951 .proc FillContext
952 FillContext:
953 alloc loc0=6,4,0,0;; // alloc 6 inputs, 4 locals, 0 outs
954 ld8.fill loc3=[in0],-8;; // int_nat (nat bits for R1-31)
955 movl loc1=7;; // ibr7
956 ld8.fill loc0=[in0],-8;;
957 mov ibr[loc1]=loc0;;
958 movl loc1=6;; // ibr6
959 ld8.fill loc0=[in0],-8;;
960 mov ibr[loc1]=loc0;;
961 movl loc1=5;; // ibr5
962 ld8.fill loc0=[in0],-8;;
963 mov ibr[loc1]=loc0;;
964 movl loc1=4;; // ibr4
965 ld8.fill loc0=[in0],-8;;
966 mov ibr[loc1]=loc0;;
967 movl loc1=3;; // ibr3
968 ld8.fill loc0=[in0],-8;;
969 mov ibr[loc1]=loc0;;
970 movl loc1=2;; // ibr2
971 ld8.fill loc0=[in0],-8;;
972 mov ibr[loc1]=loc0;;
973 movl loc1=1;; // ibr1
974 ld8.fill loc0=[in0],-8;;
975 mov ibr[loc1]=loc0;;
976 ld8.fill loc0=[in0],-8;; // ibr0
977 mov ibr[r0]=loc0;;
978 movl loc1=7;; // dbr7
979 ld8.fill loc0=[in0],-8;;
980 mov dbr[loc1]=loc0;;
981 movl loc1=6;; // dbr6
982 ld8.fill loc0=[in0],-8;;
983 mov dbr[loc1]=loc0;;
984 movl loc1=5;; // dbr5
985 ld8.fill loc0=[in0],-8;;
986 mov dbr[loc1]=loc0;;
987 movl loc1=4;; // dbr4
988 ld8.fill loc0=[in0],-8;;
989 mov dbr[loc1]=loc0;;
990 movl loc1=3;; // dbr3
991 ld8.fill loc0=[in0],-8;;
992 mov dbr[loc1]=loc0;;
993 movl loc1=2;; // dbr2
994 ld8.fill loc0=[in0],-8;;
995 mov dbr[loc1]=loc0;;
996 movl loc1=1;; // dbr1
997 ld8.fill loc0=[in0],-8;;
998 mov dbr[loc1]=loc0;;
999 ld8.fill loc0=[in0],-8;; // dbr0
1000 mov dbr[r0]=loc0;;
1001 ld8.fill loc0=[in0],-8;; // iha
1002 mov cr.iha=loc0;;
1003 ld8.fill loc0=[in0],-8;; // iim
1004 mov cr.iim=loc0;;
1005 ld8.fill loc0=[in0],-8;; // ifs
1006 mov cr.ifs=loc0;;
1007 ld8.fill loc0=[in0],-8;; // iipa
1008 mov cr.iipa=loc0;;
1009 ld8.fill loc0=[in0],-8;; // itir
1010 mov cr.itir=loc0;;
1011 ld8.fill loc0=[in0],-8;; // ifa
1012 mov cr.ifa=loc0;;
1013 ld8.fill loc0=[in0],-8;; // iip
1014 mov cr.iip=loc0;;
1015 ld8.fill loc0=[in0],-8;; // isr
1016 mov cr.isr=loc0;;
1017 ld8.fill loc0=[in0],-8;; // ipsr
1018 mov cr.ipsr=loc0;;
1019 ld8.fill loc0=[in0],-8;; // pta
1020 mov cr.pta=loc0;;
1021 ld8.fill loc0=[in0],-8;; // iva
1022 mov cr.iva=loc0;;
1023 ld8.fill loc0=[in0],-8;; // itm
1024 mov cr.itm=loc0;;
1025 ld8.fill loc0=[in0],-8;; // dcr
1026 mov cr.dcr=loc0;;
1027 ld8.fill loc0=[in0],-8;; // ec
1028 mov ar.ec=loc0;;
1029 ld8.fill loc0=[in0],-8;; // lc
1030 mov ar.lc=loc0;;
1031 ld8.fill in5=[in0],-8;; // ar.pfs
1032 ld8.fill loc0=[in0],-8;; // ar.fpsr
1033 mov ar.fpsr=loc0;;
1034 ld8.fill loc2=[in0],-8;; // ar.unat - restored later...
1035 ld8.fill loc0=[in0],-8;; // ar.ccv
1036 mov ar.ccv=loc0;;
1037 ld8.fill loc0=[in0],-8;; // ar.fdr
1038 mov ar.fdr=loc0;;
1039 ld8.fill loc0=[in0],-8;; // ar.fir
1040 mov ar.fir=loc0;;
1041 ld8.fill loc0=[in0],-8;; // ar.fsr
1042 mov ar.fsr=loc0;;
1043 ld8.fill loc0=[in0],-8;; // ar.cflg
1044 mov ar.cflg=loc0;;
1045 ld8.fill loc0=[in0],-8;; // ar.ssd
1046 mov ar.ssd=loc0;;
1047 ld8.fill loc0=[in0],-8;; // ar.csd
1048 mov ar.csd=loc0;;
1049 ld8.fill loc0=[in0],-8;; // ar.eflag
1050 mov ar.eflag=loc0;;
1051 ld8.fill loc0=[in0],-8;; // ar.fcr
1052 mov ar.fcr=loc0;;
1053 ld8.fill in4=[in0],-8;; // ar.rnat
1054 ld8.fill in3=[in0],-8;; // bspstore
1055 ld8.fill in2=[in0],-8;; // bsp
1056 ld8.fill loc0=[in0],-8;; // ar.rsc
1057 mov ar.rsc=loc0;;
1058 ld8.fill loc0=[in0],-8;; // B7 - B0
1059 mov b7=loc0;;
1060 ld8.fill loc0=[in0],-8;;
1061 mov b6=loc0;;
1062 ld8.fill loc0=[in0],-8;;
1063 mov b5=loc0;;
1064 ld8.fill loc0=[in0],-8;;
1065 mov b4=loc0;;
1066 ld8.fill loc0=[in0],-8;;
1067 mov b3=loc0;;
1068 ld8.fill loc0=[in0],-8;;
1069 mov b2=loc0;;
1070 ld8.fill loc0=[in0],-8;;
1071 mov b1=loc0;;
1072 ld8.fill in1=[in0],-8;; // b0 is temporarily stored in in1
1073 ld8.fill loc0=[in0],-16;; // predicates
1074 mov pr=loc0;;
1075 ldf.fill f31=[in0],-16;;
1076 ldf.fill f30=[in0],-16;;
1077 ldf.fill f29=[in0],-16;;
1078 ldf.fill f28=[in0],-16;;
1079 ldf.fill f27=[in0],-16;;
1080 ldf.fill f26=[in0],-16;;
1081 ldf.fill f25=[in0],-16;;
1082 ldf.fill f24=[in0],-16;;
1083 ldf.fill f23=[in0],-16;;
1084 ldf.fill f22=[in0],-16;;
1085 ldf.fill f21=[in0],-16;;
1086 ldf.fill f20=[in0],-16;;
1087 ldf.fill f19=[in0],-16;;
1088 ldf.fill f18=[in0],-16;;
1089 ldf.fill f17=[in0],-16;;
1090 ldf.fill f16=[in0],-16;;
1091 ldf.fill f15=[in0],-16;;
1092 ldf.fill f14=[in0],-16;;
1093 ldf.fill f13=[in0],-16;;
1094 ldf.fill f12=[in0],-16;;
1095 ldf.fill f11=[in0],-16;;
1096 ldf.fill f10=[in0],-16;;
1097 ldf.fill f9=[in0],-16;;
1098 ldf.fill f8=[in0],-16;;
1099 ldf.fill f7=[in0],-16;;
1100 ldf.fill f6=[in0],-16;;
1101 ldf.fill f5=[in0],-16;;
1102 ldf.fill f4=[in0],-16;;
1103 ldf.fill f3=[in0],-16;;
1104 ldf.fill f2=[in0],-8;;
1105 mov ar.unat=loc3;; // restore unat (int_nat) before fill of general registers
1106 ld8.fill r31=[in0],-8;;
1107 ld8.fill r30=[in0],-8;;
1108 ld8.fill r29=[in0],-8;;
1109 ld8.fill r28=[in0],-8;;
1110 ld8.fill r27=[in0],-8;;
1111 ld8.fill r26=[in0],-8;;
1112 ld8.fill r25=[in0],-8;;
1113 ld8.fill r24=[in0],-8;;
1114 ld8.fill r23=[in0],-8;;
1115 ld8.fill r22=[in0],-8;;
1116 ld8.fill r21=[in0],-8;;
1117 ld8.fill r20=[in0],-8;;
1118 ld8.fill r19=[in0],-8;;
1119 ld8.fill r18=[in0],-8;;
1120 ld8.fill r17=[in0],-8;;
1121 ld8.fill r16=[in0],-8;;
1122 ld8.fill r15=[in0],-8;;
1123 ld8.fill r14=[in0],-8;;
1124 ld8.fill r13=[in0],-8;;
1125 ld8.fill r12=[in0],-8;;
1126 ld8.fill r11=[in0],-8;;
1127 ld8.fill r10=[in0],-8;;
1128 ld8.fill r9=[in0],-8;;
1129 ld8.fill r8=[in0],-8;;
1130 ld8.fill r7=[in0],-8;;
1131 ld8.fill r6=[in0],-8;;
1132 ld8.fill r5=[in0],-8;;
1133 ld8.fill r4=[in0],-8;;
1134 ld8.fill r3=[in0],-8;;
1135 ld8.fill r2=[in0],-8;;
1136 ld8.fill r1=[in0],-8;;
1137 mov ar.unat=loc2;; // restore application context unat
1138
1139 br.ret.sptk.many b0
1140
1141 .endp FillContext
1142
1143
1144 /////////////////////////////////////////////
1145 //
1146 // Name:
1147 // HookHandler
1148 //
1149 // Description:
1150 // Common branch target from hooked IVT entries. Runs in interrupt context.
1151 // Responsible for saving and restoring context and calling common C
1152 // handler. Banked registers running on bank 0 at entry.
1153 //
1154 // Arguments:
1155 // All arguments are passed in banked registers:
1156 // B0_REG = Original B0
1157 // SCRATCH_REG1 = IVT entry index
1158 //
1159 // Returns:
1160 // Returns via rfi
1161 //
1162 // Notes:
1163 // loc0 - scratch
1164 // loc1 - scratch
1165 // loc2 - vector number / mask
1166 // loc3 - 16 byte aligned context record address
1167 // loc4 - temporary storage of last address in context record
1168
1169 HookHandler:
1170 flushrs;; // Synch RSE with backing store
1171 mov SCRATCH_REG2=ar.bsp // save interrupted context bsp
1172 mov SCRATCH_REG3=ar.bspstore // save interrupted context bspstore
1173 mov SCRATCH_REG4=ar.rnat // save interrupted context rnat
1174 mov SCRATCH_REG6=cr.ifs;; // save IFS in case we need to chain...
1175 cover;; // creates new frame, moves old
1176 // CFM to IFS.
1177 alloc SCRATCH_REG5=0,5,6,0 // alloc 5 locals, 6 outs
1178 ;;
1179 // save banked registers to locals
1180 mov out1=B0_REG // out1 = Original B0
1181 mov out2=SCRATCH_REG2 // out2 = original ar.bsp
1182 mov out3=SCRATCH_REG3 // out3 = original ar.bspstore
1183 mov out4=SCRATCH_REG4 // out4 = original ar.rnat
1184 mov out5=SCRATCH_REG5 // out5 = original ar.pfs
1185 mov loc2=SCRATCH_REG1;; // loc2 = vector number + chain flag
1186 bsw.1;; // switch banked registers to bank 1
1187 srlz.d // explicit serialize required
1188 // now fill in context record structure
1189 movl loc3=IpfContextBuf // Insure context record is aligned
1190 add loc0=-0x200,r0;; // mask the lower 9 bits (align on 512 byte boundary)
1191 and loc3=loc3,loc0;;
1192 add loc3=0x200,loc3;; // move to next 512 byte boundary
1193 // loc3 now contains the 512 byte aligned context record
1194 // spill register context into context record
1195 mov out0=loc3;; // Context record base in out0
1196 // original B0 in out1 already
1197 // original ar.bsp in out2 already
1198 // original ar.bspstore in out3 already
1199 br.call.sptk.few b0=SpillContext;; // spill context
1200 mov loc4=out0 // save modified address
1201
1202 // At this point, the context has been saved to the context record and we're
1203 // ready to call the C part of the handler...
1204
1205 movl loc0=CommonHandler;; // obtain address of plabel
1206 ld8 loc1=[loc0];; // get entry point of CommonHandler
1207 mov b6=loc1;; // put it in a branch register
1208 adds loc1= 8, loc0;; // index to GP in plabel
1209 ld8 r1=[loc1];; // set up gp for C call
1210 mov loc1=0xfffff;; // mask off so only vector bits are present
1211 and out0=loc2,loc1;; // pass vector number (exception type)
1212 mov out1=loc3;; // pass context record address
1213 br.call.sptk.few b0=b6;; // call C handler
1214
1215 // We've returned from the C call, so restore the context and either rfi
1216 // back to interrupted thread, or chain into the SAL if this was an external interrupt
1217 mov out0=loc4;; // pass address of last element in context record
1218 br.call.sptk.few b0=FillContext;; // Fill context
1219 mov b0=out1 // fill in b0
1220 mov ar.rnat=out4
1221 mov ar.pfs=out5
1222
1223 // Loadrs is necessary because the debugger may have changed some values in
1224 // the backing store. The processor, however may not be aware that the
1225 // stacked registers need to be reloaded from the backing store. Therefore,
1226 // we explicitly cause the RSE to refresh the stacked register's contents
1227 // from the backing store.
1228 mov loc0=ar.rsc // get RSC value
1229 mov loc1=ar.rsc // save it so we can restore it
1230 movl loc3=0xffffffffc000ffff;; // create mask for clearing RSC.loadrs
1231 and loc0=loc0,loc3;; // create value for RSC with RSC.loadrs==0
1232 mov ar.rsc=loc0;; // modify RSC
1233 loadrs;; // invalidate register stack
1234 mov ar.rsc=loc1;; // restore original RSC
1235
1236 bsw.0;; // switch banked registers back to bank 0
1237 srlz.d;; // explicit serialize required
1238 mov PR_REG=pr // save predicates - to be restored after chaining decision
1239 mov B0_REG=b0 // save b0 - required by chain code
1240 mov loc2=EXCPT_EXTERNAL_INTERRUPT;;
1241 cmp.eq p7,p0=SCRATCH_REG1,loc2;; // check to see if this is the timer tick
1242 (p7) br.cond.dpnt.few DO_CHAIN;;
1243
1244 NO_CHAIN:
1245 mov pr=PR_REG;;
1246 rfi;; // we're outa here.
1247
1248 DO_CHAIN:
1249 mov pr=PR_REG
1250 mov SCRATCH_REG1=cr.iva
1251 mov SCRATCH_REG2=PATCH_RETURN_OFFSET;;
1252 add SCRATCH_REG1=SCRATCH_REG1, SCRATCH_REG2;;
1253 mov b0=SCRATCH_REG1;;
1254 br.cond.sptk.few b0;;
1255
1256 EndHookHandler:
1257
1258
1259 /////////////////////////////////////////////
1260 //
1261 // Name:
1262 // HookStub
1263 //
1264 // Description:
1265 // HookStub will be copied from it's loaded location into the IVT when
1266 // an IVT entry is hooked. The IVT entry does an indirect jump via B0 to
1267 // HookHandler, which in turn calls into the default C handler, which calls
1268 // the user-installed C handler. The calls return and HookHandler executes
1269 // an rfi.
1270 //
1271 // Notes:
1272 // Saves B0 to B0_REG
1273 // Saves IVT index to SCRATCH_REG1 (immediate value is fixed up when code is copied
1274 // to the IVT entry.
1275
1276 .globl HookStub
1277 .proc HookStub
1278 HookStub:
1279
1280 mov B0_REG=b0
1281 movl SCRATCH_REG1=HookHandler;;
1282 mov b0=SCRATCH_REG1;;
1283 mov SCRATCH_REG1=0;;// immediate value is fixed up during install of handler to be the vector number
1284 br.cond.sptk.few b0
1285
1286 .endp HookStub
1287
1288
1289 /////////////////////////////////////////////
1290 // The following code is moved into IVT entry 14 (offset 3400) which is reserved
1291 // in the Itanium architecture. The patch code is located at the end of the
1292 // IVT entry.
1293
1294 PatchCode:
1295 mov SCRATCH_REG0=psr
1296 mov SCRATCH_REG6=cr.ipsr
1297 mov PR_REG=pr
1298 mov B0_REG=b0;;
1299
1300 // turn off any virtual translations
1301 movl SCRATCH_REG1 = ~( MASK(PSR_DT,1) | MASK(PSR_RT,1));;
1302 and SCRATCH_REG1 = SCRATCH_REG0, SCRATCH_REG1;;
1303 mov psr.l = SCRATCH_REG1;;
1304 srlz.d
1305 tbit.z p14, p15 = SCRATCH_REG6, PSR_IS;; // Check to see if we were
1306 // interrupted from IA32
1307 // context. If so, bail out
1308 // and chain to SAL immediately
1309 (p15) br.cond.sptk.few Stub_IVT_Passthru;;
1310 // we only want to take 1 out of 32 external interrupts to minimize the
1311 // impact to system performance. Check our interrupt count and bail
1312 // out if we're not up to 32
1313 movl SCRATCH_REG1=ExternalInterruptCount;;
1314 ld8 SCRATCH_REG2=[SCRATCH_REG1];; // ExternalInterruptCount
1315 tbit.z p14, p15 = SCRATCH_REG2, 5;; // bit 5 set?
1316 (p14) add SCRATCH_REG2=1, SCRATCH_REG2;; // No? Then increment
1317 // ExternalInterruptCount
1318 // and Chain to SAL
1319 // immediately
1320 (p14) st8 [SCRATCH_REG1]=SCRATCH_REG2;;
1321 (p14) br.cond.sptk.few Stub_IVT_Passthru;;
1322 (p15) mov SCRATCH_REG2=0;; // Yes? Then reset
1323 // ExternalInterruptCount
1324 // and branch to
1325 // HookHandler
1326 (p15) st8 [SCRATCH_REG1]=SCRATCH_REG2;;
1327 mov pr=PR_REG
1328 movl SCRATCH_REG1=HookHandler;; // SCRATCH_REG1 = entrypoint of HookHandler
1329 mov b0=SCRATCH_REG1;; // b0 = entrypoint of HookHandler
1330 mov SCRATCH_REG1=EXCPT_EXTERNAL_INTERRUPT;;
1331 br.sptk.few b0;; // branch to HookHandler
1332
1333 PatchCodeRet:
1334 // fake-up an rfi to get RSE back to being coherent and insure psr has
1335 // original contents when interrupt occured, then exit to SAL
1336 // at this point:
1337 // cr.ifs has been modified by previous "cover"
1338 // SCRATCH_REG6 has original cr.ifs
1339
1340 mov SCRATCH_REG5=cr.ipsr
1341 mov SCRATCH_REG4=cr.iip;;
1342 mov cr.ipsr=SCRATCH_REG0
1343 mov SCRATCH_REG1=ip;;
1344 add SCRATCH_REG1=0x30, SCRATCH_REG1;;
1345 mov cr.iip=SCRATCH_REG1;;
1346 rfi;; // rfi to next instruction
1347
1348 Stub_RfiTarget:
1349 mov cr.ifs=SCRATCH_REG6
1350 mov cr.ipsr=SCRATCH_REG5
1351 mov cr.iip=SCRATCH_REG4;;
1352
1353 Stub_IVT_Passthru:
1354 mov pr=PR_REG // pr = saved predicate registers
1355 mov b0=B0_REG;; // b0 = saved b0
1356 EndPatchCode:
1357
1358
1359 /////////////////////////////////////////////
1360 // The following bundle is moved into IVT entry 14 (offset 0x3400) which is reserved
1361 // in the Itanium architecture. This bundle will be the last bundle and will
1362 // be located at offset 0x37F0 in the IVT.
1363
1364 FailsafeBranch:
1365 {
1366 .mib
1367 nop.m 0
1368 nop.i 0
1369 br.sptk.few -(FAILSAFE_BRANCH_OFFSET - EXT_INT_ENTRY_OFFSET - 0x10)
1370 }
1371
1372
1373 /////////////////////////////////////////////
1374 // The following bundle is moved into IVT entry 13 (offset 0x3000) which is the
1375 // external interrupt. It branches to the patch code.
1376
1377 PatchCodeNewBun0:
1378 {
1379 .mib
1380 nop.m 0
1381 nop.i 0
1382 br.cond.sptk.few PATCH_BRANCH
1383 }
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