MdePkg/Include/IndustryStandard/Nvme.h

   1 /** @file
   2   Definitions based on NVMe spec. version 1.1.
   3
   4   (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
   5   Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14   @par Specification Reference:
  15   NVMe Specification 1.1
  16
  17 **/
  18
  19 #ifndef __NVM_E_H__
  20 #define __NVM_E_H__
  21
  22 #pragma pack(1)
  23
  24 //
  25 // controller register offsets
  26 //
  27 #define NVME_CAP_OFFSET          0x0000  // Controller Capabilities
  28 #define NVME_VER_OFFSET          0x0008  // Version
  29 #define NVME_INTMS_OFFSET        0x000c  // Interrupt Mask Set
  30 #define NVME_INTMC_OFFSET        0x0010  // Interrupt Mask Clear
  31 #define NVME_CC_OFFSET           0x0014  // Controller Configuration
  32 #define NVME_CSTS_OFFSET         0x001c  // Controller Status
  33 #define NVME_NSSR_OFFSET         0x0020  // NVM Subsystem Reset
  34 #define NVME_AQA_OFFSET          0x0024  // Admin Queue Attributes
  35 #define NVME_ASQ_OFFSET          0x0028  // Admin Submission Queue Base Address
  36 #define NVME_ACQ_OFFSET          0x0030  // Admin Completion Queue Base Address
  37 #define NVME_SQ0_OFFSET          0x1000  // Submission Queue 0 (admin) Tail Doorbell
  38 #define NVME_CQ0_OFFSET          0x1004  // Completion Queue 0 (admin) Head Doorbell
  39
  40 //
  41 // These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
  42 // Get the doorbell stride bit shift value from the controller capabilities.
  43 //
  44 #define NVME_SQTDBL_OFFSET(QID, DSTRD)    0x1000 + ((2 * (QID)) * (4 << (DSTRD)))       // Submission Queue y (NVM) Tail Doorbell
  45 #define NVME_CQHDBL_OFFSET(QID, DSTRD)    0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell
  46
  47
  48 #pragma pack(1)
  49
  50 //
  51 // 3.1.1 Offset 00h: CAP - Controller Capabilities
  52 //
  53 typedef struct {
  54   UINT16 Mqes;      // Maximum Queue Entries Supported
  55   UINT8  Cqr:1;     // Contiguous Queues Required
  56   UINT8  Ams:2;     // Arbitration Mechanism Supported
  57   UINT8  Rsvd1:5;
  58   UINT8  To;        // Timeout
  59   UINT16 Dstrd:4;
  60   UINT16 Nssrs:1;   // NVM Subsystem Reset Supported NSSRS
  61   UINT16 Css:4;     // Command Sets Supported - Bit 37
  62   UINT16 Rsvd3:7;
  63   UINT8  Mpsmin:4;
  64   UINT8  Mpsmax:4;
  65   UINT8  Rsvd4;
  66 } NVME_CAP;
  67
  68 //
  69 // 3.1.2 Offset 08h: VS - Version
  70 //
  71 typedef struct {
  72   UINT16 Mnr;       // Minor version number
  73   UINT16 Mjr;       // Major version number
  74 } NVME_VER;
  75
  76 //
  77 // 3.1.5 Offset 14h: CC - Controller Configuration
  78 //
  79 typedef struct {
  80   UINT16 En:1;       // Enable
  81   UINT16 Rsvd1:3;
  82   UINT16 Css:3;      // I/O Command Set Selected
  83   UINT16 Mps:4;      // Memory Page Size
  84   UINT16 Ams:3;      // Arbitration Mechanism Selected
  85   UINT16 Shn:2;      // Shutdown Notification
  86   UINT8  Iosqes:4;   // I/O Submission Queue Entry Size
  87   UINT8  Iocqes:4;   // I/O Completion Queue Entry Size
  88   UINT8  Rsvd2;
  89 } NVME_CC;
  90 #define NVME_CC_SHN_NORMAL_SHUTDOWN    1
  91 #define NVME_CC_SHN_ABRUPT_SHUTDOWN    2
  92
  93 //
  94 // 3.1.6 Offset 1Ch: CSTS - Controller Status
  95 //
  96 typedef struct {
  97   UINT32 Rdy:1;      // Ready
  98   UINT32 Cfs:1;      // Controller Fatal Status
  99   UINT32 Shst:2;     // Shutdown Status
 100   UINT32 Nssro:1;    // NVM Subsystem Reset Occurred
 101   UINT32 Rsvd1:27;
 102 } NVME_CSTS;
 103 #define NVME_CSTS_SHST_SHUTDOWN_OCCURRING 1
 104 #define NVME_CSTS_SHST_SHUTDOWN_COMPLETED 2
 105 //
 106 // 3.1.8 Offset 24h: AQA - Admin Queue Attributes
 107 //
 108 typedef struct {
 109   UINT16 Asqs:12;    // Submission Queue Size
 110   UINT16 Rsvd1:4;
 111   UINT16 Acqs:12;    // Completion Queue Size
 112   UINT16 Rsvd2:4;
 113 } NVME_AQA;
 114
 115 //
 116 // 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address
 117 //
 118 #define NVME_ASQ      UINT64
 119 //
 120 // 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address
 121 //
 122 #define NVME_ACQ      UINT64
 123
 124 //
 125 // 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
 126 //
 127 typedef struct {
 128   UINT16 Sqt;
 129   UINT16 Rsvd1;
 130 } NVME_SQTDBL;
 131
 132 //
 133 // 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell
 134 //
 135 typedef struct {
 136   UINT16 Cqh;
 137   UINT16 Rsvd1;
 138 } NVME_CQHDBL;
 139
 140 //
 141 // NVM command set structures
 142 //
 143 // Read Command
 144 //
 145 typedef struct {
 146   //
 147   // CDW 10, 11
 148   //
 149   UINT64 Slba;                /* Starting Sector Address */
 150   //
 151   // CDW 12
 152   //
 153   UINT16 Nlb;                 /* Number of Sectors */
 154   UINT16 Rsvd1:10;
 155   UINT16 Prinfo:4;            /* Protection Info Check */
 156   UINT16 Fua:1;               /* Force Unit Access */
 157   UINT16 Lr:1;                /* Limited Retry */
 158   //
 159   // CDW 13
 160   //
 161   UINT32 Af:4;                /* Access Frequency */
 162   UINT32 Al:2;                /* Access Latency */
 163   UINT32 Sr:1;                /* Sequential Request */
 164   UINT32 In:1;                /* Incompressible */
 165   UINT32 Rsvd2:24;
 166   //
 167   // CDW 14
 168   //
 169   UINT32 Eilbrt;              /* Expected Initial Logical Block Reference Tag */
 170   //
 171   // CDW 15
 172   //
 173   UINT16 Elbat;               /* Expected Logical Block Application Tag */
 174   UINT16 Elbatm;              /* Expected Logical Block Application Tag Mask */
 175 } NVME_READ;
 176
 177 //
 178 // Write Command
 179 //
 180 typedef struct {
 181   //
 182   // CDW 10, 11
 183   //
 184   UINT64 Slba;                /* Starting Sector Address */
 185   //
 186   // CDW 12
 187   //
 188   UINT16 Nlb;                 /* Number of Sectors */
 189   UINT16 Rsvd1:10;
 190   UINT16 Prinfo:4;            /* Protection Info Check */
 191   UINT16 Fua:1;               /* Force Unit Access */
 192   UINT16 Lr:1;                /* Limited Retry */
 193   //
 194   // CDW 13
 195   //
 196   UINT32 Af:4;                /* Access Frequency */
 197   UINT32 Al:2;                /* Access Latency */
 198   UINT32 Sr:1;                /* Sequential Request */
 199   UINT32 In:1;                /* Incompressible */
 200   UINT32 Rsvd2:24;
 201   //
 202   // CDW 14
 203   //
 204   UINT32 Ilbrt;               /* Initial Logical Block Reference Tag */
 205   //
 206   // CDW 15
 207   //
 208   UINT16 Lbat;                /* Logical Block Application Tag */
 209   UINT16 Lbatm;               /* Logical Block Application Tag Mask */
 210 } NVME_WRITE;
 211
 212 //
 213 // Flush
 214 //
 215 typedef struct {
 216   //
 217   // CDW 10
 218   //
 219   UINT32 Flush;               /* Flush */
 220 } NVME_FLUSH;
 221
 222 //
 223 // Write Uncorrectable command
 224 //
 225 typedef struct {
 226   //
 227   // CDW 10, 11
 228   //
 229   UINT64 Slba;                /* Starting LBA */
 230   //
 231   // CDW 12
 232   //
 233   UINT32 Nlb:16;              /* Number of  Logical Blocks */
 234   UINT32 Rsvd1:16;
 235 } NVME_WRITE_UNCORRECTABLE;
 236
 237 //
 238 // Write Zeroes command
 239 //
 240 typedef struct {
 241   //
 242   // CDW 10, 11
 243   //
 244   UINT64 Slba;                /* Starting LBA */
 245   //
 246   // CDW 12
 247   //
 248   UINT16 Nlb;                 /* Number of Logical Blocks */
 249   UINT16 Rsvd1:10;
 250   UINT16 Prinfo:4;            /* Protection Info Check */
 251   UINT16 Fua:1;               /* Force Unit Access */
 252   UINT16 Lr:1;                /* Limited Retry */
 253   //
 254   // CDW 13
 255   //
 256   UINT32 Rsvd2;
 257   //
 258   // CDW 14
 259   //
 260   UINT32 Ilbrt;               /* Initial Logical Block Reference Tag */
 261   //
 262   // CDW 15
 263   //
 264   UINT16 Lbat;                /* Logical Block Application Tag */
 265   UINT16 Lbatm;               /* Logical Block Application Tag Mask */
 266 } NVME_WRITE_ZEROES;
 267
 268 //
 269 // Compare command
 270 //
 271 typedef struct {
 272   //
 273   // CDW 10, 11
 274   //
 275   UINT64 Slba;                /* Starting LBA */
 276   //
 277   // CDW 12
 278   //
 279   UINT16 Nlb;                 /* Number of Logical Blocks */
 280   UINT16 Rsvd1:10;
 281   UINT16 Prinfo:4;            /* Protection Info Check */
 282   UINT16 Fua:1;               /* Force Unit Access */
 283   UINT16 Lr:1;                /* Limited Retry */
 284   //
 285   // CDW 13
 286   //
 287   UINT32 Rsvd2;
 288   //
 289   // CDW 14
 290   //
 291   UINT32 Eilbrt;              /* Expected Initial Logical Block Reference Tag */
 292   //
 293   // CDW 15
 294   //
 295   UINT16 Elbat;               /* Expected Logical Block Application Tag */
 296   UINT16 Elbatm;              /* Expected Logical Block Application Tag Mask */
 297 } NVME_COMPARE;
 298
 299 typedef union {
 300   NVME_READ                   Read;
 301   NVME_WRITE                  Write;
 302   NVME_FLUSH                  Flush;
 303   NVME_WRITE_UNCORRECTABLE    WriteUncorrectable;
 304   NVME_WRITE_ZEROES           WriteZeros;
 305   NVME_COMPARE                Compare;
 306 } NVME_CMD;
 307
 308 typedef struct {
 309   UINT16 Mp;                /* Maximum Power */
 310   UINT8  Rsvd1;             /* Reserved as of Nvm Express 1.1 Spec */
 311   UINT8  Mps:1;             /* Max Power Scale */
 312   UINT8  Nops:1;            /* Non-Operational State */
 313   UINT8  Rsvd2:6;           /* Reserved as of Nvm Express 1.1 Spec */
 314   UINT32 Enlat;             /* Entry Latency */
 315   UINT32 Exlat;             /* Exit Latency */
 316   UINT8  Rrt:5;             /* Relative Read Throughput */
 317   UINT8  Rsvd3:3;           /* Reserved as of Nvm Express 1.1 Spec */
 318   UINT8  Rrl:5;             /* Relative Read Leatency */
 319   UINT8  Rsvd4:3;           /* Reserved as of Nvm Express 1.1 Spec */
 320   UINT8  Rwt:5;             /* Relative Write Throughput */
 321   UINT8  Rsvd5:3;           /* Reserved as of Nvm Express 1.1 Spec */
 322   UINT8  Rwl:5;             /* Relative Write Leatency */
 323   UINT8  Rsvd6:3;           /* Reserved as of Nvm Express 1.1 Spec */
 324   UINT8  Rsvd7[16];         /* Reserved as of Nvm Express 1.1 Spec */
 325 } NVME_PSDESCRIPTOR;
 326
 327 //
 328 //  Identify Controller Data
 329 //
 330 typedef struct {
 331   //
 332   // Controller Capabilities and Features 0-255
 333   //
 334   UINT16 Vid;                 /* PCI Vendor ID */
 335   UINT16 Ssvid;               /* PCI sub-system vendor ID */
 336   UINT8  Sn[20];              /* Product serial number */
 337
 338   UINT8  Mn[40];              /* Proeduct model number */
 339   UINT8  Fr[8];               /* Firmware Revision */
 340   UINT8  Rab;                 /* Recommended Arbitration Burst */
 341   UINT8  Ieee_oui[3];         /* Organization Unique Identifier */
 342   UINT8  Cmic;                /* Multi-interface Capabilities */
 343   UINT8  Mdts;                /* Maximum Data Transfer Size */
 344   UINT8  Cntlid[2];           /* Controller ID */
 345   UINT8  Rsvd1[176];          /* Reserved as of Nvm Express 1.1 Spec */
 346   //
 347   // Admin Command Set Attributes
 348   //
 349   UINT16 Oacs;                /* Optional Admin Command Support */
 350     #define NAMESPACE_MANAGEMENT_SUPPORTED  BIT3
 351     #define FW_DOWNLOAD_ACTIVATE_SUPPORTED  BIT2
 352     #define FORMAT_NVM_SUPPORTED            BIT1
 353     #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0
 354   UINT8  Acl;                 /* Abort Command Limit */
 355   UINT8  Aerl;                /* Async Event Request Limit */
 356   UINT8  Frmw;                /* Firmware updates */
 357   UINT8  Lpa;                 /* Log Page Attributes */
 358   UINT8  Elpe;                /* Error Log Page Entries */
 359   UINT8  Npss;                /* Number of Power States Support */
 360   UINT8  Avscc;               /* Admin Vendor Specific Command Configuration */
 361   UINT8  Apsta;               /* Autonomous Power State Transition Attributes */
 362   UINT8  Rsvd2[246];          /* Reserved as of Nvm Express 1.1 Spec */
 363   //
 364   // NVM Command Set Attributes
 365   //
 366   UINT8  Sqes;                /* Submission Queue Entry Size */
 367   UINT8  Cqes;                /* Completion Queue Entry Size */
 368   UINT16 Rsvd3;               /* Reserved as of Nvm Express 1.1 Spec */
 369   UINT32 Nn;                  /* Number of Namespaces */
 370   UINT16 Oncs;                /* Optional NVM Command Support */
 371   UINT16 Fuses;               /* Fused Operation Support */
 372   UINT8  Fna;                 /* Format NVM Attributes */
 373   UINT8  Vwc;                 /* Volatile Write Cache */
 374   UINT16 Awun;                /* Atomic Write Unit Normal */
 375   UINT16 Awupf;               /* Atomic Write Unit Power Fail */
 376   UINT8  Nvscc;               /* NVM Vendor Specific Command Configuration */
 377   UINT8  Rsvd4;               /* Reserved as of Nvm Express 1.1 Spec */
 378   UINT16 Acwu;                /* Atomic Compare & Write Unit */
 379   UINT16 Rsvd5;               /* Reserved as of Nvm Express 1.1 Spec */
 380   UINT32 Sgls;                /* SGL Support  */
 381   UINT8  Rsvd6[164];          /* Reserved as of Nvm Express 1.1 Spec */
 382   //
 383   // I/O Command set Attributes
 384   //
 385   UINT8 Rsvd7[1344];          /* Reserved as of Nvm Express 1.1 Spec */
 386   //
 387   // Power State Descriptors
 388   //
 389   NVME_PSDESCRIPTOR PsDescriptor[32];
 390
 391   UINT8  VendorData[1024];    /* Vendor specific data */
 392 } NVME_ADMIN_CONTROLLER_DATA;
 393
 394 typedef struct {
 395   UINT16 Ms;                /* Metadata Size */
 396   UINT8  Lbads;             /* LBA Data Size */
 397   UINT8  Rp:2;              /* Relative Performance */
 398     #define LBAF_RP_BEST      00b
 399     #define LBAF_RP_BETTER    01b
 400     #define LBAF_RP_GOOD      10b
 401     #define LBAF_RP_DEGRADED  11b
 402   UINT8  Rsvd1:6;           /* Reserved as of Nvm Express 1.1 Spec */
 403 } NVME_LBAFORMAT;
 404
 405 //
 406 // Identify Namespace Data
 407 //
 408 typedef struct {
 409   //
 410   // NVM Command Set Specific
 411   //
 412   UINT64 Nsze;                /* Namespace Size (total number of blocks in formatted namespace) */
 413   UINT64 Ncap;                /* Namespace Capacity (max number of logical blocks) */
 414   UINT64 Nuse;                /* Namespace Utilization */
 415   UINT8  Nsfeat;              /* Namespace Features */
 416   UINT8  Nlbaf;               /* Number of LBA Formats */
 417   UINT8  Flbas;               /* Formatted LBA size */
 418   UINT8  Mc;                  /* Metadata Capabilities */
 419   UINT8  Dpc;                 /* End-to-end Data Protection capabilities */
 420   UINT8  Dps;                 /* End-to-end Data Protection Type Settings */
 421   UINT8  Nmic;                /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
 422   UINT8  Rescap;              /* Reservation Capabilities */
 423   UINT8  Rsvd1[88];           /* Reserved as of Nvm Express 1.1 Spec */
 424   UINT64 Eui64;               /* IEEE Extended Unique Identifier */
 425   //
 426   // LBA Format
 427   //
 428   NVME_LBAFORMAT LbaFormat[16];
 429
 430   UINT8 Rsvd2[192];           /* Reserved as of Nvm Express 1.1 Spec */
 431   UINT8 VendorData[3712];     /* Vendor specific data */
 432 } NVME_ADMIN_NAMESPACE_DATA;
 433
 434 //
 435 // NvmExpress Admin Identify Cmd
 436 //
 437 typedef struct {
 438   //
 439   // CDW 10
 440   //
 441   UINT32 Cns:2;
 442   UINT32 Rsvd1:30;
 443 } NVME_ADMIN_IDENTIFY;
 444
 445 //
 446 // NvmExpress Admin Create I/O Completion Queue
 447 //
 448 typedef struct {
 449   //
 450   // CDW 10
 451   //
 452   UINT32 Qid:16;              /* Queue Identifier */
 453   UINT32 Qsize:16;            /* Queue Size */
 454
 455   //
 456   // CDW 11
 457   //
 458   UINT32 Pc:1;                /* Physically Contiguous */
 459   UINT32 Ien:1;               /* Interrupts Enabled */
 460   UINT32 Rsvd1:14;            /* reserved as of Nvm Express 1.1 Spec */
 461   UINT32 Iv:16;               /* Interrupt Vector for MSI-X or MSI*/
 462 } NVME_ADMIN_CRIOCQ;
 463
 464 //
 465 // NvmExpress Admin Create I/O Submission Queue
 466 //
 467 typedef struct {
 468   //
 469   // CDW 10
 470   //
 471   UINT32 Qid:16;              /* Queue Identifier */
 472   UINT32 Qsize:16;            /* Queue Size */
 473
 474   //
 475   // CDW 11
 476   //
 477   UINT32 Pc:1;                /* Physically Contiguous */
 478   UINT32 Qprio:2;             /* Queue Priority */
 479   UINT32 Rsvd1:13;            /* Reserved as of Nvm Express 1.1 Spec */
 480   UINT32 Cqid:16;             /* Completion Queue ID */
 481 } NVME_ADMIN_CRIOSQ;
 482
 483 //
 484 // NvmExpress Admin Delete I/O Completion Queue
 485 //
 486 typedef struct {
 487   //
 488   // CDW 10
 489   //
 490   UINT16 Qid;
 491   UINT16 Rsvd1;
 492 } NVME_ADMIN_DEIOCQ;
 493
 494 //
 495 // NvmExpress Admin Delete I/O Submission Queue
 496 //
 497 typedef struct {
 498   //
 499   // CDW 10
 500   //
 501   UINT16 Qid;
 502   UINT16 Rsvd1;
 503 } NVME_ADMIN_DEIOSQ;
 504
 505 //
 506 // NvmExpress Admin Abort Command
 507 //
 508 typedef struct {
 509   //
 510   // CDW 10
 511   //
 512   UINT32 Sqid:16;             /* Submission Queue identifier */
 513   UINT32 Cid:16;              /* Command Identifier */
 514 } NVME_ADMIN_ABORT;
 515
 516 //
 517 // NvmExpress Admin Firmware Activate Command
 518 //
 519 typedef struct {
 520   //
 521   // CDW 10
 522   //
 523   UINT32 Fs:3;                /* Submission Queue identifier */
 524   UINT32 Aa:2;                /* Command Identifier */
 525   UINT32 Rsvd1:27;
 526 } NVME_ADMIN_FIRMWARE_ACTIVATE;
 527
 528 //
 529 // NvmExpress Admin Firmware Image Download Command
 530 //
 531 typedef struct {
 532   //
 533   // CDW 10
 534   //
 535   UINT32 Numd;                /* Number of Dwords */
 536   //
 537   // CDW 11
 538   //
 539   UINT32 Ofst;                /* Offset */
 540 } NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;
 541
 542 //
 543 // NvmExpress Admin Get Features Command
 544 //
 545 typedef struct {
 546   //
 547   // CDW 10
 548   //
 549   UINT32 Fid:8;                /* Feature Identifier */
 550   UINT32 Sel:3;                /* Select */
 551   UINT32 Rsvd1:21;
 552 } NVME_ADMIN_GET_FEATURES;
 553
 554 //
 555 // NvmExpress Admin Get Log Page Command
 556 //
 557 typedef struct {
 558   //
 559   // CDW 10
 560   //
 561   UINT32 Lid:8;               /* Log Page Identifier */
 562     #define LID_ERROR_INFO   0x1
 563     #define LID_SMART_INFO   0x2
 564     #define LID_FW_SLOT_INFO 0x3
 565   UINT32 Rsvd1:8;
 566   UINT32 Numd:12;             /* Number of Dwords */
 567   UINT32 Rsvd2:4;             /* Reserved as of Nvm Express 1.1 Spec */
 568 } NVME_ADMIN_GET_LOG_PAGE;
 569
 570 //
 571 // NvmExpress Admin Set Features Command
 572 //
 573 typedef struct {
 574   //
 575   // CDW 10
 576   //
 577   UINT32 Fid:8;               /* Feature Identifier */
 578   UINT32 Rsvd1:23;
 579   UINT32 Sv:1;                /* Save */
 580 } NVME_ADMIN_SET_FEATURES;
 581
 582 //
 583 // NvmExpress Admin Format NVM Command
 584 //
 585 typedef struct {
 586   //
 587   // CDW 10
 588   //
 589   UINT32 Lbaf:4;              /* LBA Format */
 590   UINT32 Ms:1;                /* Metadata Settings */
 591   UINT32 Pi:3;                /* Protection Information */
 592   UINT32 Pil:1;               /* Protection Information Location */
 593   UINT32 Ses:3;               /* Secure Erase Settings */
 594   UINT32 Rsvd1:20;
 595 } NVME_ADMIN_FORMAT_NVM;
 596
 597 //
 598 // NvmExpress Admin Security Receive Command
 599 //
 600 typedef struct {
 601   //
 602   // CDW 10
 603   //
 604   UINT32 Rsvd1:8;
 605   UINT32 Spsp:16;             /* SP Specific */
 606   UINT32 Secp:8;              /* Security Protocol */
 607   //
 608   // CDW 11
 609   //
 610   UINT32 Al;                  /* Allocation Length */
 611 } NVME_ADMIN_SECURITY_RECEIVE;
 612
 613 //
 614 // NvmExpress Admin Security Send Command
 615 //
 616 typedef struct {
 617   //
 618   // CDW 10
 619   //
 620   UINT32 Rsvd1:8;
 621   UINT32 Spsp:16;             /* SP Specific */
 622   UINT32 Secp:8;              /* Security Protocol */
 623   //
 624   // CDW 11
 625   //
 626   UINT32 Tl;                  /* Transfer Length */
 627 } NVME_ADMIN_SECURITY_SEND;
 628
 629 typedef union {
 630   NVME_ADMIN_IDENTIFY                   Identify;
 631   NVME_ADMIN_CRIOCQ                     CrIoCq;
 632   NVME_ADMIN_CRIOSQ                     CrIoSq;
 633   NVME_ADMIN_DEIOCQ                     DeIoCq;
 634   NVME_ADMIN_DEIOSQ                     DeIoSq;
 635   NVME_ADMIN_ABORT                      Abort;
 636   NVME_ADMIN_FIRMWARE_ACTIVATE          Activate;
 637   NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD    FirmwareImageDownload;
 638   NVME_ADMIN_GET_FEATURES               GetFeatures;
 639   NVME_ADMIN_GET_LOG_PAGE               GetLogPage;
 640   NVME_ADMIN_SET_FEATURES               SetFeatures;
 641   NVME_ADMIN_FORMAT_NVM                 FormatNvm;
 642   NVME_ADMIN_SECURITY_RECEIVE           SecurityReceive;
 643   NVME_ADMIN_SECURITY_SEND              SecuritySend;
 644 } NVME_ADMIN_CMD;
 645
 646 typedef struct {
 647   UINT32 Cdw10;
 648   UINT32 Cdw11;
 649   UINT32 Cdw12;
 650   UINT32 Cdw13;
 651   UINT32 Cdw14;
 652   UINT32 Cdw15;
 653 } NVME_RAW;
 654
 655 typedef union {
 656   NVME_ADMIN_CMD Admin;   // Union of Admin commands
 657   NVME_CMD       Nvm;     // Union of Nvm commands
 658   NVME_RAW       Raw;
 659 } NVME_PAYLOAD;
 660
 661 //
 662 // Submission Queue
 663 //
 664 typedef struct {
 665   //
 666   // CDW 0, Common to all comnmands
 667   //
 668   UINT8  Opc;               // Opcode
 669   UINT8  Fuse:2;            // Fused Operation
 670   UINT8  Rsvd1:5;
 671   UINT8  Psdt:1;            // PRP or SGL for Data Transfer
 672   UINT16 Cid;               // Command Identifier
 673
 674   //
 675   // CDW 1
 676   //
 677   UINT32 Nsid;              // Namespace Identifier
 678
 679   //
 680   // CDW 2,3
 681   //
 682   UINT64 Rsvd2;
 683
 684   //
 685   // CDW 4,5
 686   //
 687   UINT64 Mptr;              // Metadata Pointer
 688
 689   //
 690   // CDW 6-9
 691   //
 692   UINT64 Prp[2];            // First and second PRP entries
 693
 694   NVME_PAYLOAD Payload;
 695
 696 } NVME_SQ;
 697
 698 //
 699 // Completion Queue
 700 //
 701 typedef struct {
 702   //
 703   // CDW 0
 704   //
 705   UINT32 Dword0;
 706   //
 707   // CDW 1
 708   //
 709   UINT32 Rsvd1;
 710   //
 711   // CDW 2
 712   //
 713   UINT16 Sqhd;              // Submission Queue Head Pointer
 714   UINT16 Sqid;              // Submission Queue Identifier
 715   //
 716   // CDW 3
 717   //
 718   UINT16 Cid;               // Command Identifier
 719   UINT16 Pt:1;              // Phase Tag
 720   UINT16 Sc:8;              // Status Code
 721   UINT16 Sct:3;             // Status Code Type
 722   UINT16 Rsvd2:2;
 723   UINT16 Mo:1;              // More
 724   UINT16 Dnr:1;             // Do Not Retry
 725 } NVME_CQ;
 726
 727 //
 728 // Nvm Express Admin cmd opcodes
 729 //
 730 #define NVME_ADMIN_DEIOSQ_CMD                0x00
 731 #define NVME_ADMIN_CRIOSQ_CMD                0x01
 732 #define NVME_ADMIN_GET_LOG_PAGE_CMD          0x02
 733 #define NVME_ADMIN_DEIOCQ_CMD                0x04
 734 #define NVME_ADMIN_CRIOCQ_CMD                0x05
 735 #define NVME_ADMIN_IDENTIFY_CMD              0x06
 736 #define NVME_ADMIN_ABORT_CMD                 0x08
 737 #define NVME_ADMIN_SET_FEATURES_CMD          0x09
 738 #define NVME_ADMIN_GET_FEATURES_CMD          0x0A
 739 #define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD   0x0C
 740 #define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD   0x0D
 741 #define NVME_ADMIN_FW_COMMIT_CMD             0x10
 742 #define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD     0x11
 743 #define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD   0x15
 744 #define NVME_ADMIN_FORMAT_NVM_CMD            0x80
 745 #define NVME_ADMIN_SECURITY_SEND_CMD         0x81
 746 #define NVME_ADMIN_SECURITY_RECEIVE_CMD      0x82
 747
 748 #define NVME_IO_FLUSH_OPC                    0
 749 #define NVME_IO_WRITE_OPC                    1
 750 #define NVME_IO_READ_OPC                     2
 751
 752 typedef enum {
 753   DeleteIOSubmissionQueueOpcode = NVME_ADMIN_DEIOSQ_CMD,
 754   CreateIOSubmissionQueueOpcode = NVME_ADMIN_CRIOSQ_CMD,
 755   GetLogPageOpcode = NVME_ADMIN_GET_LOG_PAGE_CMD,
 756   DeleteIOCompletionQueueOpcode = NVME_ADMIN_DEIOCQ_CMD,
 757   CreateIOCompletionQueueOpcode = NVME_ADMIN_CRIOCQ_CMD,
 758   IdentifyOpcode = NVME_ADMIN_IDENTIFY_CMD,
 759   AbortOpcode = NVME_ADMIN_ABORT_CMD,
 760   SetFeaturesOpcode = NVME_ADMIN_SET_FEATURES_CMD,
 761   GetFeaturesOpcode = NVME_ADMIN_GET_FEATURES_CMD,
 762   AsyncEventRequestOpcode = NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD,
 763   NamespaceManagementOpcode = NVME_ADMIN_NAMESACE_MANAGEMENT_CMD,
 764   FirmwareCommitOpcode = NVME_ADMIN_FW_COMMIT_CMD,
 765   FirmwareImageDownloadOpcode = NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD,
 766   NamespaceAttachmentOpcode = NVME_ADMIN_NAMESACE_ATTACHMENT_CMD,
 767   FormatNvmOpcode = NVME_ADMIN_FORMAT_NVM_CMD,
 768   SecuritySendOpcode = NVME_ADMIN_SECURITY_SEND_CMD,
 769   SecurityReceiveOpcode = NVME_ADMIN_SECURITY_RECEIVE_CMD
 770 } NVME_ADMIN_COMMAND_OPCODE;
 771
 772 //
 773 // Controller or Namespace Structure (CNS) field
 774 // (ref. spec. v1.1 figure 82).
 775 //
 776 typedef enum {
 777 IdentifyNamespaceCns = 0x0,
 778 IdentifyControllerCns = 0x1,
 779 IdentifyActiveNsListCns = 0x2
 780 } NVME_ADMIN_IDENTIFY_CNS;
 781
 782 //
 783 // Commit Action
 784 // (ref. spec. 1.1 figure 60).
 785 //
 786 typedef enum {
 787   ActivateActionReplace = 0x0,
 788   ActivateActionReplaceActivate = 0x1,
 789   ActivateActionActivate = 0x2
 790 } NVME_FW_ACTIVATE_ACTION;
 791
 792 //
 793 // Firmware Slot
 794 // (ref. spec. 1.1 Figure 60).
 795 //
 796 typedef enum {
 797   FirmwareSlotCtrlChooses = 0x0,
 798   FirmwareSlot1 = 0x1,
 799   FirmwareSlot2 = 0x2,
 800   FirmwareSlot3 = 0x3,
 801   FirmwareSlot4 = 0x4,
 802   FirmwareSlot5 = 0x5,
 803   FirmwareSlot6 = 0x6,
 804   FirmwareSlot7 = 0x7
 805 } NVME_FW_ACTIVATE_SLOT;
 806
 807 //
 808 // Get Log Page ? Log Page Identifiers
 809 // (ref. spec. v1.1 Figure 73).
 810 //
 811 typedef enum {
 812   ErrorInfoLogID = LID_ERROR_INFO,
 813   SmartHealthInfoLogID = LID_SMART_INFO,
 814   FirmwareSlotInfoLogID = LID_FW_SLOT_INFO
 815 } NVME_LOG_ID;
 816
 817 //
 818 // Get Log Page ? Firmware Slot Information Log
 819 // (ref. spec. v1.1 Figure 77).
 820 //
 821 typedef struct {
 822   //
 823   // Indicates the firmware slot from which the actively running firmware revision was loaded.
 824   //
 825   UINT8 ActivelyRunningFwSlot:3;
 826   UINT8 :1;
 827   //
 828   // Indicates the firmware slot that is going to be activated at the next controller reset. If this field is 0h, then the controller does not indicate the firmware slot that is going to be activated at the next controller reset.
 829   //
 830   UINT8 NextActiveFwSlot:3;
 831   UINT8 :1;
 832 } NVME_ACTIVE_FW_INFO;
 833
 834 //
 835 // Get Log Page ? Firmware Slot Information Log
 836 // (ref. spec. v1.1 Figure 77).
 837 //
 838 typedef struct {
 839   //
 840   // Specifies information about the active firmware revision.
 841   //s
 842   NVME_ACTIVE_FW_INFO  ActiveFwInfo;
 843   UINT8                Reserved1[7];
 844   //
 845   // Contains the revision of the firmware downloaded to firmware slot 1/7. If no valid firmware revision is present or if this slot is unsupported, all zeros shall be returned.
 846   //
 847   CHAR8                FwRevisionSlot[7][8];
 848   UINT8                Reserved2[448];
 849 } NVME_FW_SLOT_INFO_LOG;
 850
 851 //
 852 // SMART / Health Information (Log Identifier 02h)
 853 // (ref. spec. v1.1 5.10.1.2)
 854 //
 855 typedef struct {
 856   //
 857   // This field indicates critical warnings for the state of the controller.
 858   //
 859   UINT8  CriticalWarningAvailableSpare:1;
 860   UINT8  CriticalWarningTemperature:1;
 861   UINT8  CriticalWarningReliability:1;
 862   UINT8  CriticalWarningMediaReadOnly:1;
 863   UINT8  CriticalWarningVolatileBackup:1;
 864   UINT8  CriticalWarningReserved:3;
 865   //
 866   // Contains a value corresponding to a temperature in degrees Kelvin that represents the current composite temperature of the controller and namespace(s) associated with that controller. The manner in which this value is computed is implementation specific and may not represent the actual temperature of any physical point in the NVM subsystem.
 867   //
 868   UINT16 CompositeTemp;
 869   //
 870   // Contains a normalized percentage (0 to 100%) of the remaining spare capacity available.
 871   //
 872   UINT8  AvailableSpare;
 873   //
 874   // When the Available Spare falls below the threshold indicated in this field, an asynchronous event completion may occur. The value is indicated as a normalized percentage (0 to 100%).
 875   //
 876   UINT8  AvailableSpareThreshold;
 877   //
 878   // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer?s prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).
 879   //
 880   UINT8  PercentageUsed;
 881   UINT8  Reserved1[26];
 882   //
 883   // Contains the number of 512 byte data units the host has read from the controller; this value does not include metadata.
 884   //
 885   UINT8  DataUnitsRead[16];
 886   //
 887   // Contains the number of 512 byte data units the host has written to the controller; this value does not include metadata.
 888   //
 889   UINT8  DataUnitsWritten[16];
 890   //
 891   // Contains the number of read commands completed by the controller.
 892   //
 893   UINT8  HostReadCommands[16];
 894   //
 895   // Contains the number of write commands completed by the controller.
 896   //
 897   UINT8  HostWriteCommands[16];
 898   //
 899   // Contains the amount of time the controller is busy with I/O commands. This value is reported in minutes.
 900   //
 901   UINT8  ControllerBusyTime[16];
 902   //
 903   // Contains the number of power cycles.
 904   //
 905   UINT8  PowerCycles[16];
 906   //
 907   // Contains the number of power-on hours.
 908   //
 909   UINT8  PowerOnHours[16];
 910   //
 911   // Contains the number of unsafe shutdowns.
 912   //
 913   UINT8  UnsafeShutdowns[16];
 914   //
 915   // Contains the number of occurrences where the controller detected an unrecovered data integrity error.
 916   //
 917   UINT8  MediaAndDataIntegrityErrors[16];
 918   //
 919   // Contains the number of Error Information log entries over the life of the controller.
 920   //
 921   UINT8  NumberErrorInformationLogEntries[16];
 922   //
 923   // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater than or equal to the Warning Composite Temperature Threshold (WCTEMP) field and less than the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
 924   //
 925   UINT32 WarningCompositeTemperatureTime;
 926   //
 927   // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
 928   //
 929   UINT32 CriticalCompositeTemperatureTime;
 930   //
 931   // Contains the current temperature in degrees Kelvin reported by the temperature sensor.  An implementation that does not implement the temperature sensor reports a temperature of zero degrees Kelvin.
 932   //
 933   UINT16 TemperatureSensor[8];
 934   UINT8  Reserved2[296];
 935 } NVME_SMART_HEALTH_INFO_LOG;
 936
 937 #pragma pack()
 938
 939 #endif