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2 Main PAL API's defined in IPF PAL Spec.
4 Copyright (c) 2006 - 2007, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
21 // IPF Specific Functions
25 // Disabling bitfield type checking warnings.
27 #pragma warning ( disable : 4214 )
40 // CacheType of PAL_CACHE_FLUSH.
42 #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1
43 #define PAL_CACHE_FLUSH_DATA_ALL 2
44 #define PAL_CACHE_FLUSH_ALL 3
45 #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4
49 // Bitmask of Opearation of PAL_CACHE_FLUSH.
51 #define PAL_CACHE_FLUSH_INVIDED_LINES BIT0
52 #define PAL_CACHE_FLUSH_PROBE_INTERRUPT BIT1
56 Flush the instruction or data caches. It is required by IPF.
57 The PAL procedure supports the Static Registers calling
58 convention. It could be called at virtual mode and physical
61 @param Index Index of PAL_CACHE_FLUSH within the
62 list of PAL procedures.
64 @param CacheType Unsigned 64-bit integer indicating
67 @param Operation Formatted bit vector indicating the
68 operation of this call.
70 @param ProgressIndicator Unsigned 64-bit integer specifying
71 the starting position of the flush
74 @return R9 Unsigned 64-bit integer specifying the vector
75 number of the pending interrupt.
77 @return R10 Unsigned 64-bit integer specifying the
78 starting position of the flush operation.
80 @return R11 Unsigned 64-bit integer specifying the vector
81 number of the pending interrupt.
83 @return Status 2 - Call completed without error, but a PMI
84 was taken during the execution of this
87 @return Status 1 - Call has not completed flushing due to
90 @return Status 0 - Call completed without error
92 @return Status -2 - Invalid argument
94 @return Status -3 - Call completed with error
97 #define PAL_CACHE_FLUSH 1
101 // Attributes of PAL_CACHE_CONFIG_INFO1
103 #define PAL_CACHE_ATTR_WT 0
104 #define PAL_CACHE_ATTR_WB 1
107 // PAL_CACHE_CONFIG_INFO1.StoreHint
109 #define PAL_CACHE_STORE_TEMPORAL 0
110 #define PAL_CACHE_STORE_NONE_TEMPORAL 3
113 // PAL_CACHE_CONFIG_INFO1.StoreHint
115 #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0
116 #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3
119 // PAL_CACHE_CONFIG_INFO1.StoreHint
121 #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0
122 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1
123 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3
126 // Detail the characteristics of a given processor controlled
127 // cache in the cache hierarchy.
130 UINT64 IsUnified
: 1;
131 UINT64 Attributes
: 2;
132 UINT64 Associativity
:8;
135 UINT64 StoreLatency
:8;
138 } PAL_CACHE_INFO_RETURN1
;
141 // Detail the characteristics of a given processor controlled
142 // cache in the cache hierarchy.
146 UINT64 AliasBoundary
:8;
149 } PAL_CACHE_INFO_RETURN2
;
153 Return detailed instruction or data cache information. It is
154 required by IPF. The PAL procedure supports the Static
155 Registers calling convention. It could be called at virtual
156 mode and physical mode.
158 @param Index Index of PAL_CACHE_INFO within the list of
161 @param CacheLevel Unsigned 64-bit integer specifying the
162 level in the cache hierarchy for which
163 information is requested. This value must
164 be between 0 and one less than the value
165 returned in the cache_levels return value
166 from PAL_CACHE_SUMMARY.
168 @param CacheType Unsigned 64-bit integer with a value of 1
169 for instruction cache and 2 for data or
170 unified cache. All other values are
173 @param Reserved Should be 0.
176 @return R9 Detail the characteristics of a given
177 processor controlled cache in the cache
178 hierarchy. See PAL_CACHE_INFO_RETURN1.
180 @return R10 Detail the characteristics of a given
181 processor controlled cache in the cache
182 hierarchy. See PAL_CACHE_INFO_RETURN2.
184 @return R11 Reserved with 0.
187 @return Status 0 - Call completed without error
189 @return Status -2 - Invalid argument
191 @return Status -3 - Call completed with error
194 #define PAL_CACHE_INFO 2
199 // Level of PAL_CACHE_INIT.
201 #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL
204 // Restrict of PAL_CACHE_INIT.
206 #define PAL_CACHE_INIT_NO_RESTRICT 0
207 #define PAL_CACHE_INIT_RESTRICTED 1
211 Initialize the instruction or data caches. It is required by
212 IPF. The PAL procedure supports the Static Registers calling
213 convention. It could be called at physical mode.
215 @param Index Index of PAL_CACHE_INIT within the list of PAL
218 @param Level Unsigned 64-bit integer containing the level of
219 cache to initialize. If the cache level can be
220 initialized independently, only that level will
221 be initialized. Otherwise
222 implementation-dependent side-effects will
225 @param CacheType Unsigned 64-bit integer with a value of 1 to
226 initialize the instruction cache, 2 to
227 initialize the data cache, or 3 to
228 initialize both. All other values are
231 @param Restrict Unsigned 64-bit integer with a value of 0 or
232 1. All other values are reserved. If
233 restrict is 1 and initializing the specified
234 level and cache_type of the cache would
235 cause side-effects, PAL_CACHE_INIT will
236 return -4 instead of initializing the cache.
239 @return Status 0 - Call completed without error
241 @return Status -2 - Invalid argument
243 @return Status -3 - Call completed with error.
245 @return Status -4 - Call could not initialize the specified
246 level and cache_type of the cache without
247 side-effects and restrict was 1.
250 #define PAL_CACHE_INIT 3
254 // PAL_CACHE_PROTECTION.Method.
256 #define PAL_CACHE_PROTECTION_NONE_PROTECT 0
257 #define PAL_CACHE_PROTECTION_ODD_PROTECT 1
258 #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2
259 #define PAL_CACHE_PROTECTION_ECC_PROTECT 3
264 // PAL_CACHE_PROTECTION.TagOrData.
266 #define PAL_CACHE_PROTECTION_PROTECT_DATA 0
267 #define PAL_CACHE_PROTECTION_PROTECT_TAG 1
268 #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2
269 #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3
272 // 32-bit protection information structures.
281 } PAL_CACHE_PROTECTION
;
285 Return instruction or data cache protection information. It is
286 required by IPF. The PAL procedure supports the Static
287 Registers calling convention. It could be called at physical
288 mode and Virtual mode.
290 @param Index Index of PAL_CACHE_PROT_INFO within the list of
293 @param CacheLevel Unsigned 64-bit integer specifying the level
294 in the cache hierarchy for which information
295 is requested. This value must be between 0
296 and one less than the value returned in the
297 cache_levels return value from
300 @param CacheType Unsigned 64-bit integer with a value of 1
301 for instruction cache and 2 for data or
302 unified cache. All other values are
305 @return R9 Detail the characteristics of a given
306 processor controlled cache in the cache
307 hierarchy. See PAL_CACHE_PROTECTION[0..1].
309 @return R10 Detail the characteristics of a given
310 processor controlled cache in the cache
311 hierarchy. See PAL_CACHE_PROTECTION[2..3].
313 @return R11 Detail the characteristics of a given
314 processor controlled cache in the cache
315 hierarchy. See PAL_CACHE_PROTECTION[4..5].
318 @return Status 0 - Call completed without error
320 @return Status -2 - Invalid argument
322 @return Status -3 - Call completed with error.
325 #define PAL_CACHE_PROT_INFO 38
340 Returns information on which logical processors share caches.
343 @param CallingConvention Static Registers
345 @param Mode Physical/Virtual
348 #define PAL_CACHE_SHARED_INFO 43
353 Return a summary of the cache hierarchy. It is required by
356 @param CallingConvention Static Registers
358 @param Mode Physical/Virtual
361 #define PAL_CACHE_SUMMARY 4
365 Return a list of supported memory attributes.. It is required
368 @param CallingConvention Static Registers
370 @param Mode Physical/Virtual
373 #define PAL_MEM_ATTRIB 5
377 Used in architected sequence to transition pages from a
378 cacheable, speculative attribute to an uncacheable attribute.
379 It is required by IPF.
381 @param CallingConvention Static Registers
383 @param Mode Physical/Virtual
386 #define PAL_PREFETCH_VISIBILITY 41
390 Return information needed for ptc.e instruction to purge
391 entire TC. It is required by IPF.
393 @param CallingConvention Static Registers
395 @param Mode Physical/Virtual
398 #define PAL_PTCE_INFO 6
402 Return detailed information about virtual memory features
403 supported in the processor. It is required by IPF.
405 @param CallingConvention Static Registers
407 @param Mode Physical/Virtual
410 #define PAL_VM_INFO 7
415 Return virtual memory TC and hardware walker page sizes
416 supported in the processor. It is required by IPF.
418 @param CallingConvention Static Registers
423 #define PAL_VM_PAGE_SIZE 34
427 Return summary information about virtual memory features
428 supported in the processor. It is required by IPF.
430 @param CallingConvention Static Registers
432 @param Mode Physical/Virtual
435 #define PAL_VM_SUMMARY 8
439 Read contents of a translation register. It is required by
442 @param CallingConvention Stacked Register
447 #define PAL_VM_TR_READ 261
451 Return configurable processor bus interface features and their
452 current settings. It is required by IPF.
454 @param CallingConvention Static Registers
459 #define PAL_BUS_GET_FEATURES 9
464 Enable or disable configurable features in processor bus
465 interface. It is required by IPF.
467 @param CallingConvention Static Registers
472 #define PAL_BUS_SET_FEATURES 10
477 Return the number of instruction and data breakpoint
478 registers. It is required by IPF.
480 @param CallingConvention Static Registers
482 @param Mode Physical/Virtual
485 #define PAL_DEBUG_INFO 11
489 Return the fixed component of a processor¡¯s directed address.
490 It is required by IPF.
492 @param CallingConvention Static Registers
494 @param Mode Physical/Virtual
497 #define PAL_FIXED_ADDR 12
501 Return the frequency of the output clock for use by the
502 platform, if generated by the processor. It is optinal.
504 @param CallingConvention Static Registers
506 @param Mode Physical/Virtual
509 #define PAL_FREQ_BASE 13
513 Return ratio of processor, bus, and interval time counter to
514 processor input clock or output clock for platform use, if
515 generated by the processor. It is required by IPF.
517 @param CallingConvention Static Registers
519 @param Mode Physical/Virtual
522 #define PAL_FREQ_RATIOS 14
526 Return information on which logical processors map to a
527 physical processor die. It is optinal.
529 @param CallingConvention Static Registers
531 @param Mode Physical/Virtual
534 #define PAL_LOGICAL_TO_PHYSICAL 42
538 Return the number and type of performance monitors. It is
541 @param CallingConvention Static Registers
543 @param Mode Physical/Virtual
546 #define PAL_PERF_MON_INFO 15
550 Specify processor interrupt block address and I/O port space
551 address. It is required by IPF.
553 @param CallingConvention Static Registers
555 @param Mode Physical/Virtual
558 #define PAL_PLATFORM_ADDR 16
563 Return configurable processor features and their current
564 setting. It is required by IPF.
566 @param CallingConvention Static Registers
568 @param Mode Physical/Virtual
571 #define PAL_PROC_GET_FEATURES 17
576 Enable or disable configurable processor features. It is
579 @param CallingConvention Static Registers
584 #define PAL_PROC_SET_FEATURES 18
588 Return AR and CR register information. It is required by IPF.
590 @param CallingConvention Static Registers
592 @param Mode Physical/Virtual
595 #define PAL_REGISTER_INFO 39
599 Return RSE information. It is required by
602 @param CallingConvention Static Registers
604 @param Mode Physical/Virtual
607 #define PAL_RSE_INFO 19
611 Return version of PAL code. It is required by IPF.
613 @param CallingConvention Static Registers
615 @param Mode Physical/Virtual
618 #define PAL_VERSION 20
622 Clear all error information from processor error logging
623 registers. It is required by IPF.
625 @param CallingConvention Static Registers
627 @param Mode Physical/Virtual
630 #define PAL_MC_CLEAR_LOG 21
634 Ensure that all operations that could cause an MCA have
635 completed. It is required by IPF.
637 @param CallingConvention Static Registers
639 @param Mode Physical/Virtual
642 #define PAL_MC_DRAIN 22
646 Return Processor Dynamic State for logging by SAL. It is
649 @param CallingConvention Static Registers
654 #define PAL_MC_DYNAMIC_STATE 24
658 Return Processor Machine Check Information and Processor
659 Static State for logging by SAL. It is required by IPF.
661 @param CallingConvention Static Registers
663 @param Mode Physical/Virtual
666 #define PAL_MC_ERROR_INFO 25 Req. Static Both
670 Set/Reset Expected Machine Check Indicator. It is required by
673 @param CallingConvention Static Registers
678 #define PAL_MC_EXPECTED 23
682 Register min-state save area with PAL for machine checks and
683 inits. It is required by IPF.
685 @param CallingConvention Static Registers
690 #define PAL_MC_REGISTER_MEM 27
694 Restore minimal architected state and return to interrupted
695 process. It is required by IPF.
697 @param CallingConvention Static Registers
702 #define PAL_MC_RESUME 26
706 Enter the low-power HALT state or an implementation-dependent
707 low-power state. It is optinal.
709 @param CallingConvention Static Registers
719 Return the low power capabilities of the processor. It is
722 @param CallingConvention Stacked Register
724 @param Mode Physical/Virtual
727 #define PAL_HALT_INFO 257
732 Enter the low power LIGHT HALT state. It is required by
735 @param CallingConvention Static Registers
737 @param Mode Physical/Virtual
740 #define PAL_HALT_LIGHT 29
744 Initialize tags and data of a cache line for processor
745 testing. It is required by IPF.
747 @param CallingConvention Static Registers
752 #define PAL_CACHE_LINE_INIT 31
756 Read tag and data of a cache line for diagnostic testing. It
759 @param CallingConvention Satcked Register
764 #define PAL_CACHE_READ 259
768 Write tag and data of a cache for diagnostic testing. It is
771 @param CallingConvention Satcked Registers
776 #define PAL_CACHE_WRITE 260
780 Returns alignment and size requirements needed for the memory
781 buffer passed to the PAL_TEST_PROC procedure as well as
782 information on self-test control words for the processor self
783 tests. It is required by IPF.
785 @param CallingConvention Static Registers
790 #define PAL_TEST_INFO 37
794 Perform late processor self test. It is required by
797 @param CallingConvention Stacked Registers
802 #define PAL_TEST_PROC 258
806 Return information needed to relocate PAL procedures and PAL
807 PMI code to memory. It is required by IPF.
809 @param CallingConvention Static Registers
814 #define PAL_COPY_INFO 30
818 Relocate PAL procedures and PAL PMI code to memory. It is
821 @param CallingConvention Stacked Registers
826 #define PAL_COPY_PAL 256
830 Enter IA-32 System environment. It is optional.
832 @param CallingConvention Static Registers
837 #define PAL_ENTER_IA_32_ENV 33
841 Register PMI memory entrypoints with processor. It is required
844 @param CallingConvention Static Registers
849 #define PAL_PMI_ENTRYPOINT 32