2 Main PAL API's defined in IPF PAL Spec.
4 Copyright (c) 2006 - 2007, Intel Corporation
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11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
21 // IPF Specific Functions
25 // Disabling bitfield type checking warnings.
27 #pragma warning ( disable : 4214 )
40 // CacheType of PAL_CACHE_FLUSH.
42 #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1
43 #define PAL_CACHE_FLUSH_DATA_ALL 2
44 #define PAL_CACHE_FLUSH_ALL 3
45 #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4
49 // Bitmask of Opearation of PAL_CACHE_FLUSH.
51 #define PAL_CACHE_FLUSH_INVIDED_LINES BIT0
52 #define PAL_CACHE_FLUSH_PROBE_INTERRUPT BIT1
56 Flush the instruction or data caches. It is required by IPF.
57 The PAL procedure supports the Static Registers calling
58 convention. It could be called at virtual mode and physical
61 @param Index Index of PAL_CACHE_FLUSH within the
62 list of PAL procedures.
64 @param CacheType Unsigned 64-bit integer indicating
67 @param Operation Formatted bit vector indicating the
68 operation of this call.
70 @param ProgressIndicator Unsigned 64-bit integer specifying
71 the starting position of the flush
74 @return R9 Unsigned 64-bit integer specifying the vector
75 number of the pending interrupt.
77 @return R10 Unsigned 64-bit integer specifying the
78 starting position of the flush operation.
80 @return R11 Unsigned 64-bit integer specifying the vector
81 number of the pending interrupt.
83 @return Status 2 - Call completed without error, but a PMI
84 was taken during the execution of this
87 @return Status 1 - Call has not completed flushing due to
90 @return Status 0 - Call completed without error
92 @return Status -2 - Invalid argument
94 @return Status -3 - Call completed with error
97 #define PAL_CACHE_FLUSH 1
101 // Attributes of PAL_CACHE_CONFIG_INFO1
103 #define PAL_CACHE_ATTR_WT 0
104 #define PAL_CACHE_ATTR_WB 1
107 // PAL_CACHE_CONFIG_INFO1.StoreHint
109 #define PAL_CACHE_STORE_TEMPORAL 0
110 #define PAL_CACHE_STORE_NONE_TEMPORAL 3
113 // PAL_CACHE_CONFIG_INFO1.StoreHint
115 #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0
116 #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3
119 // PAL_CACHE_CONFIG_INFO1.StoreHint
121 #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0
122 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1
123 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3
126 // Detail the characteristics of a given processor controlled
127 // cache in the cache hierarchy.
130 UINT64 IsUnified
: 1;
131 UINT64 Attributes
: 2;
132 UINT64 Associativity
:8;
135 UINT64 StoreLatency
:8;
138 } PAL_CACHE_INFO_RETURN1
;
141 // Detail the characteristics of a given processor controlled
142 // cache in the cache hierarchy.
146 UINT64 AliasBoundary
:8;
150 } PAL_CACHE_INFO_RETURN2
;
154 Return detailed instruction or data cache information. It is
155 required by IPF. The PAL procedure supports the Static
156 Registers calling convention. It could be called at virtual
157 mode and physical mode.
159 @param Index Index of PAL_CACHE_INFO within the list of
162 @param CacheLevel Unsigned 64-bit integer specifying the
163 level in the cache hierarchy for which
164 information is requested. This value must
165 be between 0 and one less than the value
166 returned in the cache_levels return value
167 from PAL_CACHE_SUMMARY.
169 @param CacheType Unsigned 64-bit integer with a value of 1
170 for instruction cache and 2 for data or
171 unified cache. All other values are
174 @param Reserved Should be 0.
177 @return R9 Detail the characteristics of a given
178 processor controlled cache in the cache
179 hierarchy. See PAL_CACHE_INFO_RETURN1.
181 @return R10 Detail the characteristics of a given
182 processor controlled cache in the cache
183 hierarchy. See PAL_CACHE_INFO_RETURN2.
185 @return R11 Reserved with 0.
188 @return Status 0 - Call completed without error
190 @return Status -2 - Invalid argument
192 @return Status -3 - Call completed with error
195 #define PAL_CACHE_INFO 2
200 // Level of PAL_CACHE_INIT.
202 #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL
205 // Restrict of PAL_CACHE_INIT.
207 #define PAL_CACHE_INIT_NO_RESTRICT 0
208 #define PAL_CACHE_INIT_RESTRICTED 1
212 Initialize the instruction or data caches. It is required by
213 IPF. The PAL procedure supports the Static Registers calling
214 convention. It could be called at physical mode.
216 @param Index Index of PAL_CACHE_INIT within the list of PAL
219 @param Level Unsigned 64-bit integer containing the level of
220 cache to initialize. If the cache level can be
221 initialized independently, only that level will
222 be initialized. Otherwise
223 implementation-dependent side-effects will
226 @param CacheType Unsigned 64-bit integer with a value of 1 to
227 initialize the instruction cache, 2 to
228 initialize the data cache, or 3 to
229 initialize both. All other values are
232 @param Restrict Unsigned 64-bit integer with a value of 0 or
233 1. All other values are reserved. If
234 restrict is 1 and initializing the specified
235 level and cache_type of the cache would
236 cause side-effects, PAL_CACHE_INIT will
237 return -4 instead of initializing the cache.
240 @return Status 0 - Call completed without error
242 @return Status -2 - Invalid argument
244 @return Status -3 - Call completed with error.
246 @return Status -4 - Call could not initialize the specified
247 level and cache_type of the cache without
248 side-effects and restrict was 1.
251 #define PAL_CACHE_INIT 3
255 // PAL_CACHE_PROTECTION.Method.
257 #define PAL_CACHE_PROTECTION_NONE_PROTECT 0
258 #define PAL_CACHE_PROTECTION_ODD_PROTECT 1
259 #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2
260 #define PAL_CACHE_PROTECTION_ECC_PROTECT 3
265 // PAL_CACHE_PROTECTION.TagOrData.
267 #define PAL_CACHE_PROTECTION_PROTECT_DATA 0
268 #define PAL_CACHE_PROTECTION_PROTECT_TAG 1
269 #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2
270 #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3
273 // 32-bit protection information structures.
282 } PAL_CACHE_PROTECTION
;
286 Return instruction or data cache protection information. It is
287 required by IPF. The PAL procedure supports the Static
288 Registers calling convention. It could be called at physical
289 mode and Virtual mode.
291 @param Index Index of PAL_CACHE_PROT_INFO within the list of
294 @param CacheLevel Unsigned 64-bit integer specifying the level
295 in the cache hierarchy for which information
296 is requested. This value must be between 0
297 and one less than the value returned in the
298 cache_levels return value from
301 @param CacheType Unsigned 64-bit integer with a value of 1
302 for instruction cache and 2 for data or
303 unified cache. All other values are
306 @return R9 Detail the characteristics of a given
307 processor controlled cache in the cache
308 hierarchy. See PAL_CACHE_PROTECTION[0..1].
310 @return R10 Detail the characteristics of a given
311 processor controlled cache in the cache
312 hierarchy. See PAL_CACHE_PROTECTION[2..3].
314 @return R11 Detail the characteristics of a given
315 processor controlled cache in the cache
316 hierarchy. See PAL_CACHE_PROTECTION[4..5].
319 @return Status 0 - Call completed without error
321 @return Status -2 - Invalid argument
323 @return Status -3 - Call completed with error.
326 #define PAL_CACHE_PROT_INFO 38
341 Returns information on which logical processors share caches.
344 @param CallingConvention Static Registers
346 @param Mode Physical/Virtual
349 #define PAL_CACHE_SHARED_INFO 43
354 Return a summary of the cache hierarchy. It is required by
357 @param CallingConvention Static Registers
359 @param Mode Physical/Virtual
362 #define PAL_CACHE_SUMMARY 4
366 Return a list of supported memory attributes.. It is required
369 @param CallingConvention Static Registers
371 @param Mode Physical/Virtual
374 #define PAL_MEM_ATTRIB 5
378 Used in architected sequence to transition pages from a
379 cacheable, speculative attribute to an uncacheable attribute.
380 It is required by IPF.
382 @param CallingConvention Static Registers
384 @param Mode Physical/Virtual
387 #define PAL_PREFETCH_VISIBILITY 41
391 Return information needed for ptc.e instruction to purge
392 entire TC. It is required by IPF.
394 @param CallingConvention Static Registers
396 @param Mode Physical/Virtual
399 #define PAL_PTCE_INFO 6
403 Return detailed information about virtual memory features
404 supported in the processor. It is required by IPF.
406 @param CallingConvention Static Registers
408 @param Mode Physical/Virtual
411 #define PAL_VM_INFO 7
416 Return virtual memory TC and hardware walker page sizes
417 supported in the processor. It is required by IPF.
419 @param CallingConvention Static Registers
424 #define PAL_VM_PAGE_SIZE 34
428 Return summary information about virtual memory features
429 supported in the processor. It is required by IPF.
431 @param CallingConvention Static Registers
433 @param Mode Physical/Virtual
436 #define PAL_VM_SUMMARY 8
440 Read contents of a translation register. It is required by
443 @param CallingConvention Stacked Register
448 #define PAL_VM_TR_READ 261
452 Return configurable processor bus interface features and their
453 current settings. It is required by IPF.
455 @param CallingConvention Static Registers
460 #define PAL_BUS_GET_FEATURES 9
465 Enable or disable configurable features in processor bus
466 interface. It is required by IPF.
468 @param CallingConvention Static Registers
473 #define PAL_BUS_SET_FEATURES 10
478 Return the number of instruction and data breakpoint
479 registers. It is required by IPF.
481 @param CallingConvention Static Registers
483 @param Mode Physical/Virtual
486 #define PAL_DEBUG_INFO 11
490 Return the fixed component of a processor¡¯s directed address.
491 It is required by IPF.
493 @param CallingConvention Static Registers
495 @param Mode Physical/Virtual
498 #define PAL_FIXED_ADDR 12
502 Return the frequency of the output clock for use by the
503 platform, if generated by the processor. It is optinal.
505 @param CallingConvention Static Registers
507 @param Mode Physical/Virtual
510 #define PAL_FREQ_BASE 13
514 Return ratio of processor, bus, and interval time counter to
515 processor input clock or output clock for platform use, if
516 generated by the processor. It is required by IPF.
518 @param CallingConvention Static Registers
520 @param Mode Physical/Virtual
523 #define PAL_FREQ_RATIOS 14
527 Return information on which logical processors map to a
528 physical processor die. It is optinal.
530 @param CallingConvention Static Registers
532 @param Mode Physical/Virtual
535 #define PAL_LOGICAL_TO_PHYSICAL 42
539 Return the number and type of performance monitors. It is
542 @param CallingConvention Static Registers
544 @param Mode Physical/Virtual
547 #define PAL_PERF_MON_INFO 15
551 Specify processor interrupt block address and I/O port space
552 address. It is required by IPF.
554 @param CallingConvention Static Registers
556 @param Mode Physical/Virtual
559 #define PAL_PLATFORM_ADDR 16
564 Return configurable processor features and their current
565 setting. It is required by IPF.
567 @param CallingConvention Static Registers
569 @param Mode Physical/Virtual
572 #define PAL_PROC_GET_FEATURES 17
577 Enable or disable configurable processor features. It is
580 @param CallingConvention Static Registers
585 #define PAL_PROC_SET_FEATURES 18
589 Return AR and CR register information. It is required by IPF.
591 @param CallingConvention Static Registers
593 @param Mode Physical/Virtual
596 #define PAL_REGISTER_INFO 39
600 Return RSE information. It is required by
603 @param CallingConvention Static Registers
605 @param Mode Physical/Virtual
608 #define PAL_RSE_INFO 19
612 Return version of PAL code. It is required by IPF.
614 @param CallingConvention Static Registers
616 @param Mode Physical/Virtual
619 #define PAL_VERSION 20
623 Clear all error information from processor error logging
624 registers. It is required by IPF.
626 @param CallingConvention Static Registers
628 @param Mode Physical/Virtual
631 #define PAL_MC_CLEAR_LOG 21
635 Ensure that all operations that could cause an MCA have
636 completed. It is required by IPF.
638 @param CallingConvention Static Registers
640 @param Mode Physical/Virtual
643 #define PAL_MC_DRAIN 22
647 Return Processor Dynamic State for logging by SAL. It is
650 @param CallingConvention Static Registers
655 #define PAL_MC_DYNAMIC_STATE 24
659 Return Processor Machine Check Information and Processor
660 Static State for logging by SAL. It is required by IPF.
662 @param CallingConvention Static Registers
664 @param Mode Physical/Virtual
667 #define PAL_MC_ERROR_INFO 25 Req. Static Both
671 Set/Reset Expected Machine Check Indicator. It is required by
674 @param CallingConvention Static Registers
679 #define PAL_MC_EXPECTED 23
683 Register min-state save area with PAL for machine checks and
684 inits. It is required by IPF.
686 @param CallingConvention Static Registers
691 #define PAL_MC_REGISTER_MEM 27
695 Restore minimal architected state and return to interrupted
696 process. It is required by IPF.
698 @param CallingConvention Static Registers
703 #define PAL_MC_RESUME 26
707 Enter the low-power HALT state or an implementation-dependent
708 low-power state. It is optinal.
710 @param CallingConvention Static Registers
720 Return the low power capabilities of the processor. It is
723 @param CallingConvention Stacked Register
725 @param Mode Physical/Virtual
728 #define PAL_HALT_INFO 257
733 Enter the low power LIGHT HALT state. It is required by
736 @param CallingConvention Static Registers
738 @param Mode Physical/Virtual
741 #define PAL_HALT_LIGHT 29
745 Initialize tags and data of a cache line for processor
746 testing. It is required by IPF.
748 @param CallingConvention Static Registers
753 #define PAL_CACHE_LINE_INIT 31
757 Read tag and data of a cache line for diagnostic testing. It
760 @param CallingConvention Satcked Register
765 #define PAL_CACHE_READ 259
769 Write tag and data of a cache for diagnostic testing. It is
772 @param CallingConvention Satcked Registers
777 #define PAL_CACHE_WRITE 260
781 Returns alignment and size requirements needed for the memory
782 buffer passed to the PAL_TEST_PROC procedure as well as
783 information on self-test control words for the processor self
784 tests. It is required by IPF.
786 @param CallingConvention Static Registers
791 #define PAL_TEST_INFO 37
795 Perform late processor self test. It is required by
798 @param CallingConvention Stacked Registers
803 #define PAL_TEST_PROC 258
807 Return information needed to relocate PAL procedures and PAL
808 PMI code to memory. It is required by IPF.
810 @param CallingConvention Static Registers
815 #define PAL_COPY_INFO 30
819 Relocate PAL procedures and PAL PMI code to memory. It is
822 @param CallingConvention Stacked Registers
827 #define PAL_COPY_PAL 256
831 Enter IA-32 System environment. It is optional.
833 @param CallingConvention Static Registers
838 #define PAL_ENTER_IA_32_ENV 33
842 Register PMI memory entrypoints with processor. It is required
845 @param CallingConvention Static Registers
850 #define PAL_PMI_ENTRYPOINT 32