MdePkg/Pci22.h: Remove deprecated macros
[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Pci22.h
1 /** @file
2 Support for PCI 2.2 standard.
3
4 This file includes the definitions in the following specifications,
5 PCI Local Bus Specification, 2.2
6 PCI-to-PCI Bridge Architecture Specification, Revision 1.2
7 PC Card Standard, 8.0
8 PCI Power Management Interface Specifiction, Revision 1.2
9
10 Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
11 Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>
12 This program and the accompanying materials
13 are licensed and made available under the terms and conditions of the BSD License
14 which accompanies this distribution. The full text of the license may be found at
15 http://opensource.org/licenses/bsd-license.php
16
17 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
18 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19
20 **/
21
22 #ifndef _PCI22_H_
23 #define _PCI22_H_
24
25 #define PCI_MAX_BUS 255
26 #define PCI_MAX_DEVICE 31
27 #define PCI_MAX_FUNC 7
28
29 #pragma pack(1)
30
31 ///
32 /// Common header region in PCI Configuration Space
33 /// Section 6.1, PCI Local Bus Specification, 2.2
34 ///
35 typedef struct {
36 UINT16 VendorId;
37 UINT16 DeviceId;
38 UINT16 Command;
39 UINT16 Status;
40 UINT8 RevisionID;
41 UINT8 ClassCode[3];
42 UINT8 CacheLineSize;
43 UINT8 LatencyTimer;
44 UINT8 HeaderType;
45 UINT8 BIST;
46 } PCI_DEVICE_INDEPENDENT_REGION;
47
48 ///
49 /// PCI Device header region in PCI Configuration Space
50 /// Section 6.1, PCI Local Bus Specification, 2.2
51 ///
52 typedef struct {
53 UINT32 Bar[6];
54 UINT32 CISPtr;
55 UINT16 SubsystemVendorID;
56 UINT16 SubsystemID;
57 UINT32 ExpansionRomBar;
58 UINT8 CapabilityPtr;
59 UINT8 Reserved1[3];
60 UINT32 Reserved2;
61 UINT8 InterruptLine;
62 UINT8 InterruptPin;
63 UINT8 MinGnt;
64 UINT8 MaxLat;
65 } PCI_DEVICE_HEADER_TYPE_REGION;
66
67 ///
68 /// PCI Device Configuration Space
69 /// Section 6.1, PCI Local Bus Specification, 2.2
70 ///
71 typedef struct {
72 PCI_DEVICE_INDEPENDENT_REGION Hdr;
73 PCI_DEVICE_HEADER_TYPE_REGION Device;
74 } PCI_TYPE00;
75
76 ///
77 /// PCI-PCI Bridge header region in PCI Configuration Space
78 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
79 ///
80 typedef struct {
81 UINT32 Bar[2];
82 UINT8 PrimaryBus;
83 UINT8 SecondaryBus;
84 UINT8 SubordinateBus;
85 UINT8 SecondaryLatencyTimer;
86 UINT8 IoBase;
87 UINT8 IoLimit;
88 UINT16 SecondaryStatus;
89 UINT16 MemoryBase;
90 UINT16 MemoryLimit;
91 UINT16 PrefetchableMemoryBase;
92 UINT16 PrefetchableMemoryLimit;
93 UINT32 PrefetchableBaseUpper32;
94 UINT32 PrefetchableLimitUpper32;
95 UINT16 IoBaseUpper16;
96 UINT16 IoLimitUpper16;
97 UINT8 CapabilityPtr;
98 UINT8 Reserved[3];
99 UINT32 ExpansionRomBAR;
100 UINT8 InterruptLine;
101 UINT8 InterruptPin;
102 UINT16 BridgeControl;
103 } PCI_BRIDGE_CONTROL_REGISTER;
104
105 ///
106 /// PCI-to-PCI Bridge Configuration Space
107 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
108 ///
109 typedef struct {
110 PCI_DEVICE_INDEPENDENT_REGION Hdr;
111 PCI_BRIDGE_CONTROL_REGISTER Bridge;
112 } PCI_TYPE01;
113
114 typedef union {
115 PCI_TYPE00 Device;
116 PCI_TYPE01 Bridge;
117 } PCI_TYPE_GENERIC;
118
119 ///
120 /// CardBus Conroller Configuration Space,
121 /// Section 4.5.1, PC Card Standard. 8.0
122 ///
123 typedef struct {
124 UINT32 CardBusSocketReg; ///< Cardus Socket/ExCA Base
125 UINT8 Cap_Ptr;
126 UINT8 Reserved;
127 UINT16 SecondaryStatus; ///< Secondary Status
128 UINT8 PciBusNumber; ///< PCI Bus Number
129 UINT8 CardBusBusNumber; ///< CardBus Bus Number
130 UINT8 SubordinateBusNumber; ///< Subordinate Bus Number
131 UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer
132 UINT32 MemoryBase0; ///< Memory Base Register 0
133 UINT32 MemoryLimit0; ///< Memory Limit Register 0
134 UINT32 MemoryBase1;
135 UINT32 MemoryLimit1;
136 UINT32 IoBase0;
137 UINT32 IoLimit0; ///< I/O Base Register 0
138 UINT32 IoBase1; ///< I/O Limit Register 0
139 UINT32 IoLimit1;
140 UINT8 InterruptLine; ///< Interrupt Line
141 UINT8 InterruptPin; ///< Interrupt Pin
142 UINT16 BridgeControl; ///< Bridge Control
143 } PCI_CARDBUS_CONTROL_REGISTER;
144
145 //
146 // Definitions of PCI class bytes and manipulation macros.
147 //
148 #define PCI_CLASS_OLD 0x00
149 #define PCI_CLASS_OLD_OTHER 0x00
150 #define PCI_CLASS_OLD_VGA 0x01
151
152 #define PCI_CLASS_MASS_STORAGE 0x01
153 #define PCI_CLASS_MASS_STORAGE_SCSI 0x00
154 #define PCI_CLASS_MASS_STORAGE_IDE 0x01
155 #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
156 #define PCI_CLASS_MASS_STORAGE_IPI 0x03
157 #define PCI_CLASS_MASS_STORAGE_RAID 0x04
158 #define PCI_CLASS_MASS_STORAGE_OTHER 0x80
159
160 #define PCI_CLASS_NETWORK 0x02
161 #define PCI_CLASS_NETWORK_ETHERNET 0x00
162 #define PCI_CLASS_NETWORK_TOKENRING 0x01
163 #define PCI_CLASS_NETWORK_FDDI 0x02
164 #define PCI_CLASS_NETWORK_ATM 0x03
165 #define PCI_CLASS_NETWORK_ISDN 0x04
166 #define PCI_CLASS_NETWORK_OTHER 0x80
167
168 #define PCI_CLASS_DISPLAY 0x03
169 #define PCI_CLASS_DISPLAY_VGA 0x00
170 #define PCI_IF_VGA_VGA 0x00
171 #define PCI_IF_VGA_8514 0x01
172 #define PCI_CLASS_DISPLAY_XGA 0x01
173 #define PCI_CLASS_DISPLAY_3D 0x02
174 #define PCI_CLASS_DISPLAY_OTHER 0x80
175
176 #define PCI_CLASS_MEDIA 0x04
177 #define PCI_CLASS_MEDIA_VIDEO 0x00
178 #define PCI_CLASS_MEDIA_AUDIO 0x01
179 #define PCI_CLASS_MEDIA_TELEPHONE 0x02
180 #define PCI_CLASS_MEDIA_OTHER 0x80
181
182 #define PCI_CLASS_MEMORY_CONTROLLER 0x05
183 #define PCI_CLASS_MEMORY_RAM 0x00
184 #define PCI_CLASS_MEMORY_FLASH 0x01
185 #define PCI_CLASS_MEMORY_OTHER 0x80
186
187 #define PCI_CLASS_BRIDGE 0x06
188 #define PCI_CLASS_BRIDGE_HOST 0x00
189 #define PCI_CLASS_BRIDGE_ISA 0x01
190 #define PCI_CLASS_BRIDGE_EISA 0x02
191 #define PCI_CLASS_BRIDGE_MCA 0x03
192 #define PCI_CLASS_BRIDGE_P2P 0x04
193 #define PCI_IF_BRIDGE_P2P 0x00
194 #define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
195 #define PCI_CLASS_BRIDGE_PCMCIA 0x05
196 #define PCI_CLASS_BRIDGE_NUBUS 0x06
197 #define PCI_CLASS_BRIDGE_CARDBUS 0x07
198 #define PCI_CLASS_BRIDGE_RACEWAY 0x08
199 #define PCI_CLASS_BRIDGE_OTHER 0x80
200 #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
201
202 #define PCI_CLASS_SCC 0x07 ///< Simple communications controllers
203 #define PCI_SUBCLASS_SERIAL 0x00
204 #define PCI_IF_GENERIC_XT 0x00
205 #define PCI_IF_16450 0x01
206 #define PCI_IF_16550 0x02
207 #define PCI_IF_16650 0x03
208 #define PCI_IF_16750 0x04
209 #define PCI_IF_16850 0x05
210 #define PCI_IF_16950 0x06
211 #define PCI_SUBCLASS_PARALLEL 0x01
212 #define PCI_IF_PARALLEL_PORT 0x00
213 #define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
214 #define PCI_IF_ECP_PARALLEL_PORT 0x02
215 #define PCI_IF_1284_CONTROLLER 0x03
216 #define PCI_IF_1284_DEVICE 0xFE
217 #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
218 #define PCI_SUBCLASS_MODEM 0x03
219 #define PCI_IF_GENERIC_MODEM 0x00
220 #define PCI_IF_16450_MODEM 0x01
221 #define PCI_IF_16550_MODEM 0x02
222 #define PCI_IF_16650_MODEM 0x03
223 #define PCI_IF_16750_MODEM 0x04
224 #define PCI_SUBCLASS_SCC_OTHER 0x80
225
226 #define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
227 #define PCI_SUBCLASS_PIC 0x00
228 #define PCI_IF_8259_PIC 0x00
229 #define PCI_IF_ISA_PIC 0x01
230 #define PCI_IF_EISA_PIC 0x02
231 #define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.
232 #define PCI_IF_APIC_CONTROLLER2 0x20
233 #define PCI_SUBCLASS_DMA 0x01
234 #define PCI_IF_8237_DMA 0x00
235 #define PCI_IF_ISA_DMA 0x01
236 #define PCI_IF_EISA_DMA 0x02
237 #define PCI_SUBCLASS_TIMER 0x02
238 #define PCI_IF_8254_TIMER 0x00
239 #define PCI_IF_ISA_TIMER 0x01
240 #define PCI_IF_EISA_TIMER 0x02
241 #define PCI_SUBCLASS_RTC 0x03
242 #define PCI_IF_GENERIC_RTC 0x00
243 #define PCI_IF_ISA_RTC 0x01
244 #define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller
245 #define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
246
247 #define PCI_CLASS_INPUT_DEVICE 0x09
248 #define PCI_SUBCLASS_KEYBOARD 0x00
249 #define PCI_SUBCLASS_PEN 0x01
250 #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
251 #define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
252 #define PCI_SUBCLASS_GAMEPORT 0x04
253 #define PCI_IF_GAMEPORT 0x00
254 #define PCI_IF_GAMEPORT1 0x10
255 #define PCI_SUBCLASS_INPUT_OTHER 0x80
256
257 #define PCI_CLASS_DOCKING_STATION 0x0A
258 #define PCI_SUBCLASS_DOCKING_GENERIC 0x00
259 #define PCI_SUBCLASS_DOCKING_OTHER 0x80
260
261 #define PCI_CLASS_PROCESSOR 0x0B
262 #define PCI_SUBCLASS_PROC_386 0x00
263 #define PCI_SUBCLASS_PROC_486 0x01
264 #define PCI_SUBCLASS_PROC_PENTIUM 0x02
265 #define PCI_SUBCLASS_PROC_ALPHA 0x10
266 #define PCI_SUBCLASS_PROC_POWERPC 0x20
267 #define PCI_SUBCLASS_PROC_MIPS 0x30
268 #define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor
269
270 #define PCI_CLASS_SERIAL 0x0C
271 #define PCI_CLASS_SERIAL_FIREWIRE 0x00
272 #define PCI_IF_1394 0x00
273 #define PCI_IF_1394_OPEN_HCI 0x10
274 #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
275 #define PCI_CLASS_SERIAL_SSA 0x02
276 #define PCI_CLASS_SERIAL_USB 0x03
277 #define PCI_IF_UHCI 0x00
278 #define PCI_IF_OHCI 0x10
279 #define PCI_IF_USB_OTHER 0x80
280 #define PCI_IF_USB_DEVICE 0xFE
281 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
282 #define PCI_CLASS_SERIAL_SMB 0x05
283
284 #define PCI_CLASS_WIRELESS 0x0D
285 #define PCI_SUBCLASS_IRDA 0x00
286 #define PCI_SUBCLASS_IR 0x01
287 #define PCI_SUBCLASS_RF 0x10
288 #define PCI_SUBCLASS_WIRELESS_OTHER 0x80
289
290 #define PCI_CLASS_INTELLIGENT_IO 0x0E
291
292 #define PCI_CLASS_SATELLITE 0x0F
293 #define PCI_SUBCLASS_TV 0x01
294 #define PCI_SUBCLASS_AUDIO 0x02
295 #define PCI_SUBCLASS_VOICE 0x03
296 #define PCI_SUBCLASS_DATA 0x04
297
298 #define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller
299 #define PCI_SUBCLASS_NET_COMPUT 0x00
300 #define PCI_SUBCLASS_ENTERTAINMENT 0x10
301 #define PCI_SUBCLASS_SECURITY_OTHER 0x80
302
303 #define PCI_CLASS_DPIO 0x11
304 #define PCI_SUBCLASS_DPIO 0x00
305 #define PCI_SUBCLASS_DPIO_OTHER 0x80
306
307 /**
308 Macro that checks whether the Base Class code of device matched.
309
310 @param _p Specified device.
311 @param c Base Class code needs matching.
312
313 @retval TRUE Base Class code matches the specified device.
314 @retval FALSE Base Class code doesn't match the specified device.
315
316 **/
317 #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
318 /**
319 Macro that checks whether the Base Class code and Sub-Class code of device matched.
320
321 @param _p Specified device.
322 @param c Base Class code needs matching.
323 @param s Sub-Class code needs matching.
324
325 @retval TRUE Base Class code and Sub-Class code match the specified device.
326 @retval FALSE Base Class code and Sub-Class code don't match the specified device.
327
328 **/
329 #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
330 /**
331 Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
332
333 @param _p Specified device.
334 @param c Base Class code needs matching.
335 @param s Sub-Class code needs matching.
336 @param p Interface code needs matching.
337
338 @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.
339 @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.
340
341 **/
342 #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
343
344 /**
345 Macro that checks whether device is a display controller.
346
347 @param _p Specified device.
348
349 @retval TRUE Device is a display controller.
350 @retval FALSE Device is not a display controller.
351
352 **/
353 #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
354 /**
355 Macro that checks whether device is a VGA-compatible controller.
356
357 @param _p Specified device.
358
359 @retval TRUE Device is a VGA-compatible controller.
360 @retval FALSE Device is not a VGA-compatible controller.
361
362 **/
363 #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
364 /**
365 Macro that checks whether device is an 8514-compatible controller.
366
367 @param _p Specified device.
368
369 @retval TRUE Device is an 8514-compatible controller.
370 @retval FALSE Device is not an 8514-compatible controller.
371
372 **/
373 #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
374 /**
375 Macro that checks whether device is built before the Class Code field was defined.
376
377 @param _p Specified device.
378
379 @retval TRUE Device is an old device.
380 @retval FALSE Device is not an old device.
381
382 **/
383 #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
384 /**
385 Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
386
387 @param _p Specified device.
388
389 @retval TRUE Device is an old VGA-compatible device.
390 @retval FALSE Device is not an old VGA-compatible device.
391
392 **/
393 #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
394 /**
395 Macro that checks whether device is an IDE controller.
396
397 @param _p Specified device.
398
399 @retval TRUE Device is an IDE controller.
400 @retval FALSE Device is not an IDE controller.
401
402 **/
403 #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
404 /**
405 Macro that checks whether device is a SCSI bus controller.
406
407 @param _p Specified device.
408
409 @retval TRUE Device is a SCSI bus controller.
410 @retval FALSE Device is not a SCSI bus controller.
411
412 **/
413 #define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
414 /**
415 Macro that checks whether device is a RAID controller.
416
417 @param _p Specified device.
418
419 @retval TRUE Device is a RAID controller.
420 @retval FALSE Device is not a RAID controller.
421
422 **/
423 #define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
424 /**
425 Macro that checks whether device is an ISA bridge.
426
427 @param _p Specified device.
428
429 @retval TRUE Device is an ISA bridge.
430 @retval FALSE Device is not an ISA bridge.
431
432 **/
433 #define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
434 /**
435 Macro that checks whether device is a PCI-to-PCI bridge.
436
437 @param _p Specified device.
438
439 @retval TRUE Device is a PCI-to-PCI bridge.
440 @retval FALSE Device is not a PCI-to-PCI bridge.
441
442 **/
443 #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
444 /**
445 Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
446
447 @param _p Specified device.
448
449 @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.
450 @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.
451
452 **/
453 #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
454 /**
455 Macro that checks whether device is a 16550-compatible serial controller.
456
457 @param _p Specified device.
458
459 @retval TRUE Device is a 16550-compatible serial controller.
460 @retval FALSE Device is not a 16550-compatible serial controller.
461
462 **/
463 #define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
464 /**
465 Macro that checks whether device is a Universal Serial Bus controller.
466
467 @param _p Specified device.
468
469 @retval TRUE Device is a Universal Serial Bus controller.
470 @retval FALSE Device is not a Universal Serial Bus controller.
471
472 **/
473 #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
474
475 //
476 // the definition of Header Type
477 //
478 #define HEADER_TYPE_DEVICE 0x00
479 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
480 #define HEADER_TYPE_CARDBUS_BRIDGE 0x02
481 #define HEADER_TYPE_MULTI_FUNCTION 0x80
482 //
483 // Mask of Header type
484 //
485 #define HEADER_LAYOUT_CODE 0x7f
486 /**
487 Macro that checks whether device is a PCI-PCI bridge.
488
489 @param _p Specified device.
490
491 @retval TRUE Device is a PCI-PCI bridge.
492 @retval FALSE Device is not a PCI-PCI bridge.
493
494 **/
495 #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
496 /**
497 Macro that checks whether device is a CardBus bridge.
498
499 @param _p Specified device.
500
501 @retval TRUE Device is a CardBus bridge.
502 @retval FALSE Device is not a CardBus bridge.
503
504 **/
505 #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
506 /**
507 Macro that checks whether device is a multiple functions device.
508
509 @param _p Specified device.
510
511 @retval TRUE Device is a multiple functions device.
512 @retval FALSE Device is not a multiple functions device.
513
514 **/
515 #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
516
517 ///
518 /// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,
519 ///
520 #define PCI_BRIDGE_ROMBAR 0x38
521
522 #define PCI_MAX_BAR 0x0006
523 #define PCI_MAX_CONFIG_OFFSET 0x0100
524
525 #define PCI_VENDOR_ID_OFFSET 0x00
526 #define PCI_DEVICE_ID_OFFSET 0x02
527 #define PCI_COMMAND_OFFSET 0x04
528 #define PCI_PRIMARY_STATUS_OFFSET 0x06
529 #define PCI_REVISION_ID_OFFSET 0x08
530 #define PCI_CLASSCODE_OFFSET 0x09
531 #define PCI_CACHELINE_SIZE_OFFSET 0x0C
532 #define PCI_LATENCY_TIMER_OFFSET 0x0D
533 #define PCI_HEADER_TYPE_OFFSET 0x0E
534 #define PCI_BIST_OFFSET 0x0F
535 #define PCI_BASE_ADDRESSREG_OFFSET 0x10
536 #define PCI_CARDBUS_CIS_OFFSET 0x28
537 #define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id
538 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
539 #define PCI_SID_OFFSET 0x2E ///< SubSystem ID
540 #define PCI_SUBSYSTEM_ID_OFFSET 0x2E
541 #define PCI_EXPANSION_ROM_BASE 0x30
542 #define PCI_CAPBILITY_POINTER_OFFSET 0x34
543 #define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register
544 #define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register
545 #define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register
546 #define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register
547
548 //
549 // defined in PCI-to-PCI Bridge Architecture Specification
550 //
551 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
552 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
553 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
554 #define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b
555 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
556 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
557
558 ///
559 /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
560 ///
561 #define PCI_INT_LINE_UNKNOWN 0xFF
562
563 ///
564 /// PCI Access Data Format
565 ///
566 typedef union {
567 struct {
568 UINT32 Reg : 8;
569 UINT32 Func : 3;
570 UINT32 Dev : 5;
571 UINT32 Bus : 8;
572 UINT32 Reserved : 7;
573 UINT32 Enable : 1;
574 } Bits;
575 UINT32 Uint32;
576 } PCI_CONFIG_ACCESS_CF8;
577
578 #pragma pack()
579
580 #define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001
581 #define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002
582 #define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004
583 #define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008
584 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010
585 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020
586 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040
587 #define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080
588 #define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100
589 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200
590
591 //
592 // defined in PCI-to-PCI Bridge Architecture Specification
593 //
594 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001
595 #define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002
596 #define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004
597 #define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008
598 #define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010
599 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020
600 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040
601 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080
602 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100
603 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200
604 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400
605 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800
606
607 //
608 // Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
609 //
610 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080
611 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100
612 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200
613 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400
614
615 //
616 // Following are the PCI status control bit
617 //
618 #define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010
619 #define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020
620 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080
621 #define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100
622
623 ///
624 /// defined in PC Card Standard
625 ///
626 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
627
628 #pragma pack(1)
629 //
630 // PCI Capability List IDs and records
631 //
632 #define EFI_PCI_CAPABILITY_ID_PMI 0x01
633 #define EFI_PCI_CAPABILITY_ID_AGP 0x02
634 #define EFI_PCI_CAPABILITY_ID_VPD 0x03
635 #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
636 #define EFI_PCI_CAPABILITY_ID_MSI 0x05
637 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
638 #define EFI_PCI_CAPABILITY_ID_SHPC 0x0C
639
640 ///
641 /// Capabilities List Header
642 /// Section 6.7, PCI Local Bus Specification, 2.2
643 ///
644 typedef struct {
645 UINT8 CapabilityID;
646 UINT8 NextItemPtr;
647 } EFI_PCI_CAPABILITY_HDR;
648
649 ///
650 /// PMC - Power Management Capabilities
651 /// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2
652 ///
653 typedef union {
654 struct {
655 UINT16 Version : 3;
656 UINT16 PmeClock : 1;
657 UINT16 Reserved : 1;
658 UINT16 DeviceSpecificInitialization : 1;
659 UINT16 AuxCurrent : 3;
660 UINT16 D1Support : 1;
661 UINT16 D2Support : 1;
662 UINT16 PmeSupport : 5;
663 } Bits;
664 UINT16 Data;
665 } EFI_PCI_PMC;
666
667 #define EFI_PCI_PMC_D3_COLD_MASK (BIT15)
668
669 ///
670 /// PMCSR - Power Management Control/Status
671 /// Section 3.2.4, PCI Power Management Interface Specifiction, Revision 1.2
672 ///
673 typedef union {
674 struct {
675 UINT16 PowerState : 2;
676 UINT16 ReservedForPciExpress : 1;
677 UINT16 NoSoftReset : 1;
678 UINT16 Reserved : 4;
679 UINT16 PmeEnable : 1;
680 UINT16 DataSelect : 4;
681 UINT16 DataScale : 2;
682 UINT16 PmeStatus : 1;
683 } Bits;
684 UINT16 Data;
685 } EFI_PCI_PMCSR;
686
687 #define PCI_POWER_STATE_D0 0
688 #define PCI_POWER_STATE_D1 1
689 #define PCI_POWER_STATE_D2 2
690 #define PCI_POWER_STATE_D3_HOT 3
691
692 ///
693 /// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions
694 /// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2
695 ///
696 typedef union {
697 struct {
698 UINT8 Reserved : 6;
699 UINT8 B2B3 : 1;
700 UINT8 BusPowerClockControl : 1;
701 } Bits;
702 UINT8 Uint8;
703 } EFI_PCI_PMCSR_BSE;
704
705 ///
706 /// Power Management Register Block Definition
707 /// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2
708 ///
709 typedef struct {
710 EFI_PCI_CAPABILITY_HDR Hdr;
711 EFI_PCI_PMC PMC;
712 EFI_PCI_PMCSR PMCSR;
713 EFI_PCI_PMCSR_BSE BridgeExtention;
714 UINT8 Data;
715 } EFI_PCI_CAPABILITY_PMI;
716
717 ///
718 /// A.G.P Capability
719 /// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0
720 ///
721 typedef struct {
722 EFI_PCI_CAPABILITY_HDR Hdr;
723 UINT8 Rev;
724 UINT8 Reserved;
725 UINT32 Status;
726 UINT32 Command;
727 } EFI_PCI_CAPABILITY_AGP;
728
729 ///
730 /// VPD Capability Structure
731 /// Appendix I, PCI Local Bus Specification, 2.2
732 ///
733 typedef struct {
734 EFI_PCI_CAPABILITY_HDR Hdr;
735 UINT16 AddrReg;
736 UINT32 DataReg;
737 } EFI_PCI_CAPABILITY_VPD;
738
739 ///
740 /// Slot Numbering Capabilities Register
741 /// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2
742 ///
743 typedef struct {
744 EFI_PCI_CAPABILITY_HDR Hdr;
745 UINT8 ExpnsSlotReg;
746 UINT8 ChassisNo;
747 } EFI_PCI_CAPABILITY_SLOTID;
748
749 ///
750 /// Message Capability Structure for 32-bit Message Address
751 /// Section 6.8.1, PCI Local Bus Specification, 2.2
752 ///
753 typedef struct {
754 EFI_PCI_CAPABILITY_HDR Hdr;
755 UINT16 MsgCtrlReg;
756 UINT32 MsgAddrReg;
757 UINT16 MsgDataReg;
758 } EFI_PCI_CAPABILITY_MSI32;
759
760 ///
761 /// Message Capability Structure for 64-bit Message Address
762 /// Section 6.8.1, PCI Local Bus Specification, 2.2
763 ///
764 typedef struct {
765 EFI_PCI_CAPABILITY_HDR Hdr;
766 UINT16 MsgCtrlReg;
767 UINT32 MsgAddrRegLsdw;
768 UINT32 MsgAddrRegMsdw;
769 UINT16 MsgDataReg;
770 } EFI_PCI_CAPABILITY_MSI64;
771
772 ///
773 /// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,
774 /// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
775 ///
776 typedef struct {
777 EFI_PCI_CAPABILITY_HDR Hdr;
778 ///
779 /// not finished - fields need to go here
780 ///
781 } EFI_PCI_CAPABILITY_HOTPLUG;
782
783 #define PCI_BAR_IDX0 0x00
784 #define PCI_BAR_IDX1 0x01
785 #define PCI_BAR_IDX2 0x02
786 #define PCI_BAR_IDX3 0x03
787 #define PCI_BAR_IDX4 0x04
788 #define PCI_BAR_IDX5 0x05
789
790 ///
791 /// EFI PCI Option ROM definitions
792 ///
793 #define EFI_ROOT_BRIDGE_LIST 'eprb'
794 #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.
795
796 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
797 #define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')
798 #define PCI_CODE_TYPE_PCAT_IMAGE 0x00
799 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.
800
801 ///
802 /// Standard PCI Expansion ROM Header
803 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
804 ///
805 typedef struct {
806 UINT16 Signature; ///< 0xaa55
807 UINT8 Reserved[0x16];
808 UINT16 PcirOffset;
809 } PCI_EXPANSION_ROM_HEADER;
810
811 ///
812 /// Legacy ROM Header Extensions
813 /// Section 6.3.3.1, PCI Local Bus Specification, 2.2
814 ///
815 typedef struct {
816 UINT16 Signature; ///< 0xaa55
817 UINT8 Size512;
818 UINT8 InitEntryPoint[3];
819 UINT8 Reserved[0x12];
820 UINT16 PcirOffset;
821 } EFI_LEGACY_EXPANSION_ROM_HEADER;
822
823 ///
824 /// PCI Data Structure Format
825 /// Section 6.3.1.2, PCI Local Bus Specification, 2.2
826 ///
827 typedef struct {
828 UINT32 Signature; ///< "PCIR"
829 UINT16 VendorId;
830 UINT16 DeviceId;
831 UINT16 Reserved0;
832 UINT16 Length;
833 UINT8 Revision;
834 UINT8 ClassCode[3];
835 UINT16 ImageLength;
836 UINT16 CodeRevision;
837 UINT8 CodeType;
838 UINT8 Indicator;
839 UINT16 Reserved1;
840 } PCI_DATA_STRUCTURE;
841
842 ///
843 /// EFI PCI Expansion ROM Header
844 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
845 ///
846 typedef struct {
847 UINT16 Signature; ///< 0xaa55
848 UINT16 InitializationSize;
849 UINT32 EfiSignature; ///< 0x0EF1
850 UINT16 EfiSubsystem;
851 UINT16 EfiMachineType;
852 UINT16 CompressionType;
853 UINT8 Reserved[8];
854 UINT16 EfiImageHeaderOffset;
855 UINT16 PcirOffset;
856 } EFI_PCI_EXPANSION_ROM_HEADER;
857
858 typedef union {
859 UINT8 *Raw;
860 PCI_EXPANSION_ROM_HEADER *Generic;
861 EFI_PCI_EXPANSION_ROM_HEADER *Efi;
862 EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;
863 } EFI_PCI_ROM_HEADER;
864
865 #pragma pack()
866
867 #endif