MdePkg/Include/IndustryStandard/Pci22.h

   1 /** @file
   2   Support for PCI 2.2 standard.
   3
   4   This file includes the definitions in the following specifications,
   5     PCI Local Bus Specification, 2.2
   6     PCI-to-PCI Bridge Architecture Specification, Revision 1.2
   7     PC Card Standard, 8.0
   8
   9   Copyright (c) 2006 - 2008, Intel Corporation
  10   All rights reserved. This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18 **/
  19
  20 #ifndef _PCI22_H_
  21 #define _PCI22_H_
  22
  23 #define PCI_MAX_SEGMENT 0
  24 #define PCI_MAX_BUS     255
  25 #define PCI_MAX_DEVICE  31
  26 #define PCI_MAX_FUNC    7
  27
  28 #pragma pack(1)
  29
  30 ///
  31 /// Common header region in PCI Configuration Space
  32 /// Section 6.1, PCI Local Bus Specification, 2.2
  33 ///
  34 typedef struct {
  35   UINT16  VendorId;
  36   UINT16  DeviceId;
  37   UINT16  Command;
  38   UINT16  Status;
  39   UINT8   RevisionID;
  40   UINT8   ClassCode[3];
  41   UINT8   CacheLineSize;
  42   UINT8   LatencyTimer;
  43   UINT8   HeaderType;
  44   UINT8   BIST;
  45 } PCI_DEVICE_INDEPENDENT_REGION;
  46
  47 ///
  48 /// PCI Device header region in PCI Configuration Space
  49 /// Section 6.1, PCI Local Bus Specification, 2.2
  50 ///
  51 typedef struct {
  52   UINT32  Bar[6];
  53   UINT32  CISPtr;
  54   UINT16  SubsystemVendorID;
  55   UINT16  SubsystemID;
  56   UINT32  ExpansionRomBar;
  57   UINT8   CapabilityPtr;
  58   UINT8   Reserved1[3];
  59   UINT32  Reserved2;
  60   UINT8   InterruptLine;
  61   UINT8   InterruptPin;
  62   UINT8   MinGnt;
  63   UINT8   MaxLat;
  64 } PCI_DEVICE_HEADER_TYPE_REGION;
  65
  66 ///
  67 /// PCI Device Configuration Space
  68 /// Section 6.1, PCI Local Bus Specification, 2.2
  69 ///
  70 typedef struct {
  71   PCI_DEVICE_INDEPENDENT_REGION Hdr;
  72   PCI_DEVICE_HEADER_TYPE_REGION Device;
  73 } PCI_TYPE00;
  74
  75 ///
  76 /// PCI-PCI Bridge header region in PCI Configuration Space
  77 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
  78 ///
  79 typedef struct {
  80   UINT32  Bar[2];
  81   UINT8   PrimaryBus;
  82   UINT8   SecondaryBus;
  83   UINT8   SubordinateBus;
  84   UINT8   SecondaryLatencyTimer;
  85   UINT8   IoBase;
  86   UINT8   IoLimit;
  87   UINT16  SecondaryStatus;
  88   UINT16  MemoryBase;
  89   UINT16  MemoryLimit;
  90   UINT16  PrefetchableMemoryBase;
  91   UINT16  PrefetchableMemoryLimit;
  92   UINT32  PrefetchableBaseUpper32;
  93   UINT32  PrefetchableLimitUpper32;
  94   UINT16  IoBaseUpper16;
  95   UINT16  IoLimitUpper16;
  96   UINT8   CapabilityPtr;
  97   UINT8   Reserved[3];
  98   UINT32  ExpansionRomBAR;
  99   UINT8   InterruptLine;
 100   UINT8   InterruptPin;
 101   UINT16  BridgeControl;
 102 } PCI_BRIDGE_CONTROL_REGISTER;
 103
 104 ///
 105 /// PCI-to-PCI Bridge Configuration Space
 106 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
 107 ///
 108 typedef struct {
 109   PCI_DEVICE_INDEPENDENT_REGION Hdr;
 110   PCI_BRIDGE_CONTROL_REGISTER   Bridge;
 111 } PCI_TYPE01;
 112
 113 typedef union {
 114   PCI_TYPE00  Device;
 115   PCI_TYPE01  Bridge;
 116 } PCI_TYPE_GENERIC;
 117
 118 ///
 119 /// CardBus Conroller Configuration Space,
 120 /// Section 4.5.1, PC Card Standard. 8.0
 121 ///
 122 typedef struct {
 123   UINT32  CardBusSocketReg;     ///< Cardus Socket/ExCA Base
 124   UINT8   Cap_Ptr;
 125   UINT8   Reserved;
 126   UINT16  SecondaryStatus;      ///< Secondary Status
 127   UINT8   PciBusNumber;         ///< PCI Bus Number
 128   UINT8   CardBusBusNumber;     ///< CardBus Bus Number
 129   UINT8   SubordinateBusNumber; ///< Subordinate Bus Number
 130   UINT8   CardBusLatencyTimer;  ///< CardBus Latency Timer
 131   UINT32  MemoryBase0;          ///< Memory Base Register 0
 132   UINT32  MemoryLimit0;         ///< Memory Limit Register 0
 133   UINT32  MemoryBase1;
 134   UINT32  MemoryLimit1;
 135   UINT32  IoBase0;
 136   UINT32  IoLimit0;             ///< I/O Base Register 0
 137   UINT32  IoBase1;              ///< I/O Limit Register 0
 138   UINT32  IoLimit1;
 139   UINT8   InterruptLine;        ///< Interrupt Line
 140   UINT8   InterruptPin;         ///< Interrupt Pin
 141   UINT16  BridgeControl;        ///< Bridge Control
 142 } PCI_CARDBUS_CONTROL_REGISTER;
 143
 144 //
 145 // Definitions of PCI class bytes and manipulation macros.
 146 //
 147 #define PCI_CLASS_OLD                 0x00
 148 #define   PCI_CLASS_OLD_OTHER           0x00
 149 #define   PCI_CLASS_OLD_VGA             0x01
 150
 151 #define PCI_CLASS_MASS_STORAGE        0x01
 152 #define   PCI_CLASS_MASS_STORAGE_SCSI   0x00
 153 #define   PCI_CLASS_MASS_STORAGE_IDE    0x01
 154 #define   PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
 155 #define   PCI_CLASS_MASS_STORAGE_IPI    0x03
 156 #define   PCI_CLASS_MASS_STORAGE_RAID   0x04
 157 #define   PCI_CLASS_MASS_STORAGE_OTHER  0x80
 158
 159 #define PCI_CLASS_NETWORK             0x02
 160 #define   PCI_CLASS_NETWORK_ETHERNET    0x00
 161 #define   PCI_CLASS_NETWORK_TOKENRING   0x01
 162 #define   PCI_CLASS_NETWORK_FDDI        0x02
 163 #define   PCI_CLASS_NETWORK_ATM         0x03
 164 #define   PCI_CLASS_NETWORK_ISDN        0x04
 165 #define   PCI_CLASS_NETWORK_OTHER       0x80
 166
 167 #define PCI_CLASS_DISPLAY             0x03
 168 #define   PCI_CLASS_DISPLAY_VGA         0x00
 169 #define     PCI_IF_VGA_VGA                0x00
 170 #define     PCI_IF_VGA_8514               0x01
 171 #define   PCI_CLASS_DISPLAY_XGA         0x01
 172 #define   PCI_CLASS_DISPLAY_3D          0x02
 173 #define   PCI_CLASS_DISPLAY_OTHER       0x80
 174
 175 #define PCI_CLASS_MEDIA               0x04
 176 #define   PCI_CLASS_MEDIA_VIDEO         0x00
 177 #define   PCI_CLASS_MEDIA_AUDIO         0x01
 178 #define   PCI_CLASS_MEDIA_TELEPHONE     0x02
 179 #define   PCI_CLASS_MEDIA_OTHER         0x80
 180
 181 #define PCI_CLASS_MEMORY_CONTROLLER   0x05
 182 #define   PCI_CLASS_MEMORY_RAM          0x00
 183 #define   PCI_CLASS_MEMORY_FLASH        0x01
 184 #define   PCI_CLASS_MEMORY_OTHER        0x80
 185
 186 #define PCI_CLASS_BRIDGE              0x06
 187 #define   PCI_CLASS_BRIDGE_HOST         0x00
 188 #define   PCI_CLASS_BRIDGE_ISA          0x01
 189 #define   PCI_CLASS_BRIDGE_EISA         0x02
 190 #define   PCI_CLASS_BRIDGE_MCA          0x03
 191 #define   PCI_CLASS_BRIDGE_P2P          0x04
 192 #define     PCI_IF_BRIDGE_P2P             0x00
 193 #define     PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
 194 #define   PCI_CLASS_BRIDGE_PCMCIA       0x05
 195 #define   PCI_CLASS_BRIDGE_NUBUS        0x06
 196 #define   PCI_CLASS_BRIDGE_CARDBUS      0x07
 197 #define   PCI_CLASS_BRIDGE_RACEWAY      0x08
 198 #define   PCI_CLASS_BRIDGE_OTHER        0x80
 199 #define   PCI_CLASS_BRIDGE_ISA_PDECODE  0x80
 200
 201 #define PCI_CLASS_SCC                 0x07  ///< Simple communications controllers
 202 #define   PCI_SUBCLASS_SERIAL           0x00
 203 #define     PCI_IF_GENERIC_XT             0x00
 204 #define     PCI_IF_16450                  0x01
 205 #define     PCI_IF_16550                  0x02
 206 #define     PCI_IF_16650                  0x03
 207 #define     PCI_IF_16750                  0x04
 208 #define     PCI_IF_16850                  0x05
 209 #define     PCI_IF_16950                  0x06
 210 #define   PCI_SUBCLASS_PARALLEL         0x01
 211 #define     PCI_IF_PARALLEL_PORT          0x00
 212 #define     PCI_IF_BI_DIR_PARALLEL_PORT   0x01
 213 #define     PCI_IF_ECP_PARALLEL_PORT      0x02
 214 #define     PCI_IF_1284_CONTROLLER        0x03
 215 #define     PCI_IF_1284_DEVICE            0xFE
 216 #define   PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
 217 #define   PCI_SUBCLASS_MODEM            0x03
 218 #define     PCI_IF_GENERIC_MODEM          0x00
 219 #define     PCI_IF_16450_MODEM            0x01
 220 #define     PCI_IF_16550_MODEM            0x02
 221 #define     PCI_IF_16650_MODEM            0x03
 222 #define     PCI_IF_16750_MODEM            0x04
 223 #define   PCI_SUBCLASS_SCC_OTHER          0x80
 224
 225 #define PCI_CLASS_SYSTEM_PERIPHERAL   0x08
 226 #define   PCI_SUBCLASS_PIC              0x00
 227 #define     PCI_IF_8259_PIC               0x00
 228 #define     PCI_IF_ISA_PIC                0x01
 229 #define     PCI_IF_EISA_PIC               0x02
 230 #define     PCI_IF_APIC_CONTROLLER        0x10  ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.
 231 #define     PCI_IF_APIC_CONTROLLER2       0x20
 232 #define   PCI_SUBCLASS_DMA              0x01
 233 #define     PCI_IF_8237_DMA               0x00
 234 #define     PCI_IF_ISA_DMA                0x01
 235 #define     PCI_IF_EISA_DMA               0x02
 236 #define   PCI_SUBCLASS_TIMER            0x02
 237 #define     PCI_IF_8254_TIMER             0x00
 238 #define     PCI_IF_ISA_TIMER              0x01
 239 #define     PCI_IF_EISA_TIMER             0x02
 240 #define   PCI_SUBCLASS_RTC              0x03
 241 #define     PCI_IF_GENERIC_RTC            0x00
 242 #define     PCI_IF_ISA_RTC                0x00
 243 #define   PCI_SUBCLASS_PNP_CONTROLLER   0x04    ///< HotPlug Controller
 244 #define   PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
 245
 246 #define PCI_CLASS_INPUT_DEVICE        0x09
 247 #define   PCI_SUBCLASS_KEYBOARD         0x00
 248 #define   PCI_SUBCLASS_PEN              0x01
 249 #define   PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
 250 #define   PCI_SUBCLASS_SCAN_CONTROLLER  0x03
 251 #define   PCI_SUBCLASS_GAMEPORT         0x04
 252 #define     PCI_IF_GAMEPORT               0x00
 253 #define     PCI_IF_GAMEPORT1              0x01
 254 #define   PCI_SUBCLASS_INPUT_OTHER      0x80
 255
 256 #define PCI_CLASS_DOCKING_STATION     0x0A
 257
 258 #define PCI_CLASS_PROCESSOR           0x0B
 259 #define   PCI_SUBCLASS_PROC_386         0x00
 260 #define   PCI_SUBCLASS_PROC_486         0x01
 261 #define   PCI_SUBCLASS_PROC_PENTIUM     0x02
 262 #define   PCI_SUBCLASS_PROC_ALPHA       0x10
 263 #define   PCI_SUBCLASS_PROC_POWERPC     0x20
 264 #define   PCI_SUBCLASS_PROC_MIPS        0x30
 265 #define   PCI_SUBCLASS_PROC_CO_PORC     0x40 ///< Co-Processor
 266
 267 #define PCI_CLASS_SERIAL              0x0C
 268 #define   PCI_CLASS_SERIAL_FIREWIRE     0x00
 269 #define     PCI_IF_1394                   0x00
 270 #define     PCI_IF_1394_OPEN_HCI          0x10
 271 #define   PCI_CLASS_SERIAL_ACCESS_BUS   0x01
 272 #define   PCI_CLASS_SERIAL_SSA          0x02
 273 #define   PCI_CLASS_SERIAL_USB          0x03
 274 #define     PCI_IF_UHCI                   0x00
 275 #define     PCI_IF_OHCI                   0x10
 276 #define     PCI_IF_USB_OTHER              0x80
 277 #define     PCI_IF_USB_DEVICE             0xFE
 278 #define   PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
 279 #define   PCI_CLASS_SERIAL_SMB          0x05
 280
 281 #define PCI_CLASS_WIRELESS            0x0D
 282 #define   PCI_SUBCLASS_IRDA             0x00
 283 #define   PCI_SUBCLASS_IR               0x01
 284 #define   PCI_SUBCLASS_RF               0x02
 285 #define   PCI_SUBCLASS_WIRELESS_OTHER   0x80
 286
 287 #define PCI_CLASS_INTELLIGENT_IO      0x0E
 288
 289 #define PCI_CLASS_SATELLITE           0x0F
 290 #define   PCI_SUBCLASS_TV               0x01
 291 #define   PCI_SUBCLASS_AUDIO            0x02
 292 #define   PCI_SUBCLASS_VOICE            0x03
 293 #define   PCI_SUBCLASS_DATA             0x04
 294
 295 #define PCI_SECURITY_CONTROLLER       0x10   ///< Encryption and decryption controller
 296 #define   PCI_SUBCLASS_NET_COMPUT       0x00
 297 #define   PCI_SUBCLASS_ENTERTAINMENT    0x10
 298 #define   PCI_SUBCLASS_SECURITY_OTHER   0x80
 299
 300 #define PCI_CLASS_DPIO                0x11
 301 #define   PCI_SUBCLASS_DPIO             0x00
 302 #define   PCI_SUBCLASS_DPIO_OTHER       0x80
 303
 304 /**
 305   Macro that checks whether the Base Class code of device matched.
 306
 307   @param  _p      Specified device.
 308   @param  c       Base Class code needs matching.
 309
 310   @retval TRUE    Base Class code matches the specified device.
 311   @retval FALSE   Base Class code doesn't match the specified device.
 312
 313 **/
 314 #define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))
 315 /**
 316   Macro that checks whether the Base Class code and Sub-Class code of device matched.
 317
 318   @param  _p      Specified device.
 319   @param  c       Base Class code needs matching.
 320   @param  s       Sub-Class code needs matching.
 321
 322   @retval TRUE    Base Class code and Sub-Class code match the specified device.
 323   @retval FALSE   Base Class code and Sub-Class code don't match the specified device.
 324
 325 **/
 326 #define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
 327 /**
 328   Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
 329
 330   @param  _p      Specified device.
 331   @param  c       Base Class code needs matching.
 332   @param  s       Sub-Class code needs matching.
 333   @param  p       Interface code needs matching.
 334
 335   @retval TRUE    Base Class code, Sub-Class code and Interface code match the specified device.
 336   @retval FALSE   Base Class code, Sub-Class code and Interface code don't match the specified device.
 337
 338 **/
 339 #define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
 340
 341 /**
 342   Macro that checks whether device is a display controller.
 343
 344   @param  _p      Specified device.
 345
 346   @retval TRUE    Device is a display controller.
 347   @retval FALSE   Device is not a display controller.
 348
 349 **/
 350 #define IS_PCI_DISPLAY(_p)            IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
 351 /**
 352   Macro that checks whether device is a VGA-compatible controller.
 353
 354   @param  _p      Specified device.
 355
 356   @retval TRUE    Device is a VGA-compatible controller.
 357   @retval FALSE   Device is not a VGA-compatible controller.
 358
 359 **/
 360 #define IS_PCI_VGA(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
 361 /**
 362   Macro that checks whether device is an 8514-compatible controller.
 363
 364   @param  _p      Specified device.
 365
 366   @retval TRUE    Device is an 8514-compatible controller.
 367   @retval FALSE   Device is not an 8514-compatible controller.
 368
 369 **/
 370 #define IS_PCI_8514(_p)               IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
 371 /**
 372   Macro that checks whether device is built before the Class Code field was defined.
 373
 374   @param  _p      Specified device.
 375
 376   @retval TRUE    Device is an old device.
 377   @retval FALSE   Device is not an old device.
 378
 379 **/
 380 #define IS_PCI_OLD(_p)                IS_CLASS1 (_p, PCI_CLASS_OLD)
 381 /**
 382   Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
 383
 384   @param  _p      Specified device.
 385
 386   @retval TRUE    Device is an old VGA-compatible device.
 387   @retval FALSE   Device is not an old VGA-compatible device.
 388
 389 **/
 390 #define IS_PCI_OLD_VGA(_p)            IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
 391 /**
 392   Macro that checks whether device is an IDE controller.
 393
 394   @param  _p      Specified device.
 395
 396   @retval TRUE    Device is an IDE controller.
 397   @retval FALSE   Device is not an IDE controller.
 398
 399 **/
 400 #define IS_PCI_IDE(_p)                IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
 401 /**
 402   Macro that checks whether device is a SCSI bus controller.
 403
 404   @param  _p      Specified device.
 405
 406   @retval TRUE    Device is a SCSI bus controller.
 407   @retval FALSE   Device is not a SCSI bus controller.
 408
 409 **/
 410 #define IS_PCI_SCSI(_p)               IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
 411 /**
 412   Macro that checks whether device is a RAID controller.
 413
 414   @param  _p      Specified device.
 415
 416   @retval TRUE    Device is a RAID controller.
 417   @retval FALSE   Device is not a RAID controller.
 418
 419 **/
 420 #define IS_PCI_RAID(_p)               IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
 421 /**
 422   Macro that checks whether device is an ISA bridge.
 423
 424   @param  _p      Specified device.
 425
 426   @retval TRUE    Device is an ISA bridge.
 427   @retval FALSE   Device is not an ISA bridge.
 428
 429 **/
 430 #define IS_PCI_LPC(_p)                IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
 431 /**
 432   Macro that checks whether device is a PCI-to-PCI bridge.
 433
 434   @param  _p      Specified device.
 435
 436   @retval TRUE    Device is a PCI-to-PCI bridge.
 437   @retval FALSE   Device is not a PCI-to-PCI bridge.
 438
 439 **/
 440 #define IS_PCI_P2P(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
 441 /**
 442   Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
 443
 444   @param  _p      Specified device.
 445
 446   @retval TRUE    Device is a Subtractive Decode PCI-to-PCI bridge.
 447   @retval FALSE   Device is not a Subtractive Decode PCI-to-PCI bridge.
 448
 449 **/
 450 #define IS_PCI_P2P_SUB(_p)            IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
 451 /**
 452   Macro that checks whether device is a 16550-compatible serial controller.
 453
 454   @param  _p      Specified device.
 455
 456   @retval TRUE    Device is a 16550-compatible serial controller.
 457   @retval FALSE   Device is not a 16550-compatible serial controller.
 458
 459 **/
 460 #define IS_PCI_16550_SERIAL(_p)       IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
 461 /**
 462   Macro that checks whether device is a Universal Serial Bus controller.
 463
 464   @param  _p      Specified device.
 465
 466   @retval TRUE    Device is a Universal Serial Bus controller.
 467   @retval FALSE   Device is not a Universal Serial Bus controller.
 468
 469 **/
 470 #define IS_PCI_USB(_p)                IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
 471
 472 //
 473 // the definition of Header Type
 474 //
 475 #define HEADER_TYPE_DEVICE            0x00
 476 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
 477 #define HEADER_TYPE_CARDBUS_BRIDGE    0x02
 478 #define HEADER_TYPE_MULTI_FUNCTION    0x80
 479 //
 480 // Mask of Header type
 481 //
 482 #define HEADER_LAYOUT_CODE            0x7f
 483 /**
 484   Macro that checks whether device is a PCI-PCI bridge.
 485
 486   @param  _p      Specified device.
 487
 488   @retval TRUE    Device is a PCI-PCI bridge.
 489   @retval FALSE   Device is not a PCI-PCI bridge.
 490
 491 **/
 492 #define IS_PCI_BRIDGE(_p)             (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
 493 /**
 494   Macro that checks whether device is a CardBus bridge.
 495
 496   @param  _p      Specified device.
 497
 498   @retval TRUE    Device is a CardBus bridge.
 499   @retval FALSE   Device is not a CardBus bridge.
 500
 501 **/
 502 #define IS_CARDBUS_BRIDGE(_p)         (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
 503 /**
 504   Macro that checks whether device is a multiple functions device.
 505
 506   @param  _p      Specified device.
 507
 508   @retval TRUE    Device is a multiple functions device.
 509   @retval FALSE   Device is not a multiple functions device.
 510
 511 **/
 512 #define IS_PCI_MULTI_FUNC(_p)         ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
 513
 514 ///
 515 /// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,
 516 ///
 517 #define PCI_BRIDGE_ROMBAR             0x38
 518
 519 #define PCI_MAX_BAR                   0x0006
 520 #define PCI_MAX_CONFIG_OFFSET         0x0100
 521
 522 #define PCI_VENDOR_ID_OFFSET                        0x00
 523 #define PCI_DEVICE_ID_OFFSET                        0x02
 524 #define PCI_COMMAND_OFFSET                          0x04
 525 #define PCI_PRIMARY_STATUS_OFFSET                   0x06
 526 #define PCI_REVISION_ID_OFFSET                      0x08
 527 #define PCI_CLASSCODE_OFFSET                        0x09
 528 #define PCI_CACHELINE_SIZE_OFFSET                   0x0C
 529 #define PCI_LATENCY_TIMER_OFFSET                    0x0D
 530 #define PCI_HEADER_TYPE_OFFSET                      0x0E
 531 #define PCI_BIST_OFFSET                             0x0F
 532 #define PCI_BASE_ADDRESSREG_OFFSET                  0x10
 533 #define PCI_CARDBUS_CIS_OFFSET                      0x28
 534 #define PCI_SVID_OFFSET                             0x2C ///< SubSystem Vendor id
 535 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET              0x2C
 536 #define PCI_SID_OFFSET                              0x2E ///< SubSystem ID
 537 #define PCI_SUBSYSTEM_ID_OFFSET                     0x2E
 538 #define PCI_EXPANSION_ROM_BASE                      0x30
 539 #define PCI_CAPBILITY_POINTER_OFFSET                0x34
 540 #define PCI_INT_LINE_OFFSET                         0x3C ///< Interrupt Line Register
 541 #define PCI_INT_PIN_OFFSET                          0x3D ///< Interrupt Pin Register
 542 #define PCI_MAXGNT_OFFSET                           0x3E ///< Max Grant Register
 543 #define PCI_MAXLAT_OFFSET                           0x3F ///< Max Latency Register
 544
 545 //
 546 // defined in PCI-to-PCI Bridge Architecture Specification
 547 //
 548 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18
 549 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19
 550 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a
 551 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E
 552 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E
 553
 554 ///
 555 /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
 556 ///
 557 #define PCI_INT_LINE_UNKNOWN                        0xFF
 558
 559 ///
 560 /// PCI Access Data Format
 561 ///
 562 typedef union {
 563   struct {
 564     UINT32  Reg : 8;
 565     UINT32  Func : 3;
 566     UINT32  Dev : 5;
 567     UINT32  Bus : 8;
 568     UINT32  Reserved : 7;
 569     UINT32  Enable : 1;
 570   } Bits;
 571   UINT32  Uint32;
 572 } PCI_CONFIG_ACCESS_CF8;
 573
 574 #pragma pack()
 575
 576 #define EFI_PCI_COMMAND_IO_SPACE                        BIT0   ///< 0x0001
 577 #define EFI_PCI_COMMAND_MEMORY_SPACE                    BIT1   ///< 0x0002
 578 #define EFI_PCI_COMMAND_BUS_MASTER                      BIT2   ///< 0x0004
 579 #define EFI_PCI_COMMAND_SPECIAL_CYCLE                   BIT3   ///< 0x0008
 580 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE     BIT4   ///< 0x0010
 581 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP               BIT5   ///< 0x0020
 582 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND            BIT6   ///< 0x0040
 583 #define EFI_PCI_COMMAND_STEPPING_CONTROL                BIT7   ///< 0x0080
 584 #define EFI_PCI_COMMAND_SERR                            BIT8   ///< 0x0100
 585 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK               BIT9   ///< 0x0200
 586
 587 //
 588 // defined in PCI-to-PCI Bridge Architecture Specification
 589 //
 590 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE    BIT0   ///< 0x0001
 591 #define EFI_PCI_BRIDGE_CONTROL_SERR                     BIT1   ///< 0x0002
 592 #define EFI_PCI_BRIDGE_CONTROL_ISA                      BIT2   ///< 0x0004
 593 #define EFI_PCI_BRIDGE_CONTROL_VGA                      BIT3   ///< 0x0008
 594 #define EFI_PCI_BRIDGE_CONTROL_VGA_16                   BIT4   ///< 0x0010
 595 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT             BIT5   ///< 0x0020
 596 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS      BIT6   ///< 0x0040
 597 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK        BIT7   ///< 0x0080
 598 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER    BIT8   ///< 0x0100
 599 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER  BIT9   ///< 0x0200
 600 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS             BIT10  ///< 0x0400
 601 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR       BIT11  ///< 0x0800
 602
 603 //
 604 // Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
 605 //
 606 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE           BIT7   ///< 0x0080
 607 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE       BIT8   ///< 0x0100
 608 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE       BIT9   ///< 0x0200
 609 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE     BIT10  ///< 0x0400
 610
 611 //
 612 // Following are the PCI status control bit
 613 //
 614 #define EFI_PCI_STATUS_CAPABILITY                       BIT4   ///< 0x0010
 615 #define EFI_PCI_STATUS_66MZ_CAPABLE                     BIT5   ///< 0x0020
 616 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE               BIT7   ///< 0x0080
 617 #define EFI_PCI_MASTER_DATA_PARITY_ERROR                BIT8   ///< 0x0100
 618
 619 ///
 620 /// defined in PC Card Standard
 621 ///
 622 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
 623
 624 #pragma pack(1)
 625 //
 626 // PCI Capability List IDs and records
 627 //
 628 #define EFI_PCI_CAPABILITY_ID_PMI     0x01
 629 #define EFI_PCI_CAPABILITY_ID_AGP     0x02
 630 #define EFI_PCI_CAPABILITY_ID_VPD     0x03
 631 #define EFI_PCI_CAPABILITY_ID_SLOTID  0x04
 632 #define EFI_PCI_CAPABILITY_ID_MSI     0x05
 633 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
 634
 635 ///
 636 /// Capabilities List Header
 637 /// Section 6.7, PCI Local Bus Specification, 2.2
 638 ///
 639 typedef struct {
 640   UINT8 CapabilityID;
 641   UINT8 NextItemPtr;
 642 } EFI_PCI_CAPABILITY_HDR;
 643
 644 ///
 645 /// Power Management Register Block Definition
 646 /// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2
 647 ///
 648 typedef struct {
 649   EFI_PCI_CAPABILITY_HDR  Hdr;
 650   UINT16                  PMC;
 651   UINT16                  PMCSR;
 652   UINT8                   BridgeExtention;
 653   UINT8                   Data;
 654 } EFI_PCI_CAPABILITY_PMI;
 655
 656 ///
 657 /// A.G.P Capability
 658 /// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0
 659 ///
 660 typedef struct {
 661   EFI_PCI_CAPABILITY_HDR  Hdr;
 662   UINT8                   Rev;
 663   UINT8                   Reserved;
 664   UINT32                  Status;
 665   UINT32                  Command;
 666 } EFI_PCI_CAPABILITY_AGP;
 667
 668 ///
 669 /// VPD Capability Structure
 670 /// Appendix I, PCI Local Bus Specification, 2.2
 671 ///
 672 typedef struct {
 673   EFI_PCI_CAPABILITY_HDR  Hdr;
 674   UINT16                  AddrReg;
 675   UINT32                  DataReg;
 676 } EFI_PCI_CAPABILITY_VPD;
 677
 678 ///
 679 /// Slot Numbering Capabilities Register
 680 /// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2
 681 ///
 682 typedef struct {
 683   EFI_PCI_CAPABILITY_HDR  Hdr;
 684   UINT8                   ExpnsSlotReg;
 685   UINT8                   ChassisNo;
 686 } EFI_PCI_CAPABILITY_SLOTID;
 687
 688 ///
 689 /// Message Capability Structure for 32-bit Message Address
 690 /// Section 6.8.1, PCI Local Bus Specification, 2.2
 691 ///
 692 typedef struct {
 693   EFI_PCI_CAPABILITY_HDR  Hdr;
 694   UINT16                  MsgCtrlReg;
 695   UINT32                  MsgAddrReg;
 696   UINT16                  MsgDataReg;
 697 } EFI_PCI_CAPABILITY_MSI32;
 698
 699 ///
 700 /// Message Capability Structure for 64-bit Message Address
 701 /// Section 6.8.1, PCI Local Bus Specification, 2.2
 702 ///
 703 typedef struct {
 704   EFI_PCI_CAPABILITY_HDR  Hdr;
 705   UINT16                  MsgCtrlReg;
 706   UINT32                  MsgAddrRegLsdw;
 707   UINT32                  MsgAddrRegMsdw;
 708   UINT16                  MsgDataReg;
 709 } EFI_PCI_CAPABILITY_MSI64;
 710
 711 ///
 712 /// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,
 713 /// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
 714 ///
 715 typedef struct {
 716   EFI_PCI_CAPABILITY_HDR  Hdr;
 717   ///
 718   /// not finished - fields need to go here
 719   ///
 720 } EFI_PCI_CAPABILITY_HOTPLUG;
 721
 722 #define DEVICE_ID_NOCARE    0xFFFF
 723
 724 #define PCI_ACPI_UNUSED     0
 725 #define PCI_BAR_NOCHANGE    0
 726 #define PCI_BAR_OLD_ALIGN   0xFFFFFFFFFFFFFFFFULL
 727 #define PCI_BAR_EVEN_ALIGN  0xFFFFFFFFFFFFFFFEULL
 728 #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
 729 #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
 730
 731 #define PCI_BAR_IDX0        0x00
 732 #define PCI_BAR_IDX1        0x01
 733 #define PCI_BAR_IDX2        0x02
 734 #define PCI_BAR_IDX3        0x03
 735 #define PCI_BAR_IDX4        0x04
 736 #define PCI_BAR_IDX5        0x05
 737 #define PCI_BAR_ALL         0xFF
 738
 739 ///
 740 /// EFI PCI Option ROM definitions
 741 ///
 742 #define EFI_ROOT_BRIDGE_LIST                            'eprb'
 743 #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE       0x0EF1  ///< defined in UEFI Spec.
 744
 745 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE              0xaa55
 746 #define PCI_DATA_STRUCTURE_SIGNATURE                    SIGNATURE_32 ('P', 'C', 'I', 'R')
 747 #define PCI_CODE_TYPE_PCAT_IMAGE                        0x00
 748 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED         0x0001  ///< defined in UEFI spec.
 749
 750 ///
 751 /// Standard PCI Expansion ROM Header
 752 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
 753 ///
 754 typedef struct {
 755   UINT16  Signature;    ///< 0xaa55
 756   UINT8   Reserved[0x16];
 757   UINT16  PcirOffset;
 758 } PCI_EXPANSION_ROM_HEADER;
 759
 760 ///
 761 /// Legacy ROM Header Extensions
 762 /// Section 6.3.3.1, PCI Local Bus Specification, 2.2
 763 ///
 764 typedef struct {
 765   UINT16  Signature;    ///< 0xaa55
 766   UINT8   Size512;
 767   UINT8   InitEntryPoint[3];
 768   UINT8   Reserved[0x12];
 769   UINT16  PcirOffset;
 770 } EFI_LEGACY_EXPANSION_ROM_HEADER;
 771
 772 ///
 773 /// PCI Data Structure Format
 774 /// Section 6.3.1.2, PCI Local Bus Specification, 2.2
 775 ///
 776 typedef struct {
 777   UINT32  Signature;    ///< "PCIR"
 778   UINT16  VendorId;
 779   UINT16  DeviceId;
 780   UINT16  Reserved0;
 781   UINT16  Length;
 782   UINT8   Revision;
 783   UINT8   ClassCode[3];
 784   UINT16  ImageLength;
 785   UINT16  CodeRevision;
 786   UINT8   CodeType;
 787   UINT8   Indicator;
 788   UINT16  Reserved1;
 789 } PCI_DATA_STRUCTURE;
 790
 791 ///
 792 /// EFI PCI Expansion ROM Header
 793 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
 794 ///
 795 typedef struct {
 796   UINT16  Signature;    ///< 0xaa55
 797   UINT16  InitializationSize;
 798   UINT32  EfiSignature; ///< 0x0EF1
 799   UINT16  EfiSubsystem;
 800   UINT16  EfiMachineType;
 801   UINT16  CompressionType;
 802   UINT8   Reserved[8];
 803   UINT16  EfiImageHeaderOffset;
 804   UINT16  PcirOffset;
 805 } EFI_PCI_EXPANSION_ROM_HEADER;
 806
 807 typedef union {
 808   UINT8                           *Raw;
 809   PCI_EXPANSION_ROM_HEADER        *Generic;
 810   EFI_PCI_EXPANSION_ROM_HEADER    *Efi;
 811   EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;
 812 } EFI_PCI_ROM_HEADER;
 813
 814 #pragma pack()
 815
 816 #endif