MdePkg/Include/IndustryStandard/Pci22.h

   1 /** @file
   2   Support for PCI 2.2 standard.
   3
   4   This file includes the definitions in the following specifications,
   5     PCI Local Bus Specification, 2.2
   6     PCI-to-PCI Bridge Architecture Specification, Revision 1.2
   7     PC Card Standard, 8.0
   8
   9   Copyright (c) 2006 - 2008, Intel Corporation
  10   All rights reserved. This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18 **/
  19
  20 #ifndef _PCI22_H_
  21 #define _PCI22_H_
  22
  23 #define PCI_MAX_SEGMENT 0
  24 #define PCI_MAX_BUS     255
  25 #define PCI_MAX_DEVICE  31
  26 #define PCI_MAX_FUNC    7
  27
  28 #pragma pack(1)
  29
  30 ///
  31 /// Common header region in PCI Configuration Space
  32 /// Section 6.1, PCI Local Bus Specification, 2.2
  33 ///
  34 typedef struct {
  35   UINT16  VendorId;
  36   UINT16  DeviceId;
  37   UINT16  Command;
  38   UINT16  Status;
  39   UINT8   RevisionID;
  40   UINT8   ClassCode[3];
  41   UINT8   CacheLineSize;
  42   UINT8   LatencyTimer;
  43   UINT8   HeaderType;
  44   UINT8   BIST;
  45 } PCI_DEVICE_INDEPENDENT_REGION;
  46
  47 ///
  48 /// PCI Device header region in PCI Configuration Space
  49 /// Section 6.1, PCI Local Bus Specification, 2.2
  50 ///
  51 typedef struct {
  52   UINT32  Bar[6];
  53   UINT32  CISPtr;
  54   UINT16  SubsystemVendorID;
  55   UINT16  SubsystemID;
  56   UINT32  ExpansionRomBar;
  57   UINT8   CapabilityPtr;
  58   UINT8   Reserved1[3];
  59   UINT32  Reserved2;
  60   UINT8   InterruptLine;
  61   UINT8   InterruptPin;
  62   UINT8   MinGnt;
  63   UINT8   MaxLat;
  64 } PCI_DEVICE_HEADER_TYPE_REGION;
  65
  66 ///
  67 /// PCI Device Configuration Space
  68 /// Section 6.1, PCI Local Bus Specification, 2.2
  69 ///
  70 typedef struct {
  71   PCI_DEVICE_INDEPENDENT_REGION Hdr;
  72   PCI_DEVICE_HEADER_TYPE_REGION Device;
  73 } PCI_TYPE00;
  74
  75 ///
  76 /// PCI-PCI Bridge header region in PCI Configuration Space
  77 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
  78 ///
  79 typedef struct {
  80   UINT32  Bar[2];
  81   UINT8   PrimaryBus;
  82   UINT8   SecondaryBus;
  83   UINT8   SubordinateBus;
  84   UINT8   SecondaryLatencyTimer;
  85   UINT8   IoBase;
  86   UINT8   IoLimit;
  87   UINT16  SecondaryStatus;
  88   UINT16  MemoryBase;
  89   UINT16  MemoryLimit;
  90   UINT16  PrefetchableMemoryBase;
  91   UINT16  PrefetchableMemoryLimit;
  92   UINT32  PrefetchableBaseUpper32;
  93   UINT32  PrefetchableLimitUpper32;
  94   UINT16  IoBaseUpper16;
  95   UINT16  IoLimitUpper16;
  96   UINT8   CapabilityPtr;
  97   UINT8   Reserved[3];
  98   UINT32  ExpansionRomBAR;
  99   UINT8   InterruptLine;
 100   UINT8   InterruptPin;
 101   UINT16  BridgeControl;
 102 } PCI_BRIDGE_CONTROL_REGISTER;
 103
 104 ///
 105 /// PCI-to-PCI Bridge Configuration Space
 106 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
 107 ///
 108 typedef struct {
 109   PCI_DEVICE_INDEPENDENT_REGION Hdr;
 110   PCI_BRIDGE_CONTROL_REGISTER   Bridge;
 111 } PCI_TYPE01;
 112
 113 typedef union {
 114   PCI_TYPE00  Device;
 115   PCI_TYPE01  Bridge;
 116 } PCI_TYPE_GENERIC;
 117
 118 ///
 119 /// CardBus Conroller Configuration Space,
 120 /// Section 4.5.1, PC Card Standard. 8.0
 121 ///
 122 typedef struct {
 123   UINT32  CardBusSocketReg;     ///< Cardus Socket/ExCA Base
 124   UINT8   Cap_Ptr;
 125   UINT8   Reserved;
 126   UINT16  SecondaryStatus;      ///< Secondary Status
 127   UINT8   PciBusNumber;         ///< PCI Bus Number
 128   UINT8   CardBusBusNumber;     ///< CardBus Bus Number
 129   UINT8   SubordinateBusNumber; ///< Subordinate Bus Number
 130   UINT8   CardBusLatencyTimer;  ///< CardBus Latency Timer
 131   UINT32  MemoryBase0;          ///< Memory Base Register 0
 132   UINT32  MemoryLimit0;         ///< Memory Limit Register 0
 133   UINT32  MemoryBase1;
 134   UINT32  MemoryLimit1;
 135   UINT32  IoBase0;
 136   UINT32  IoLimit0;             ///< I/O Base Register 0
 137   UINT32  IoBase1;              ///< I/O Limit Register 0
 138   UINT32  IoLimit1;
 139   UINT8   InterruptLine;        ///< Interrupt Line
 140   UINT8   InterruptPin;         ///< Interrupt Pin
 141   UINT16  BridgeControl;        ///< Bridge Control
 142 } PCI_CARDBUS_CONTROL_REGISTER;
 143
 144 //
 145 // Definitions of PCI class bytes and manipulation macros.
 146 //
 147 #define PCI_CLASS_OLD                 0x00
 148 #define   PCI_CLASS_OLD_OTHER           0x00
 149 #define   PCI_CLASS_OLD_VGA             0x01
 150
 151 #define PCI_CLASS_MASS_STORAGE        0x01
 152 #define   PCI_CLASS_MASS_STORAGE_SCSI   0x00
 153 #define   PCI_CLASS_MASS_STORAGE_IDE    0x01
 154 #define   PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
 155 #define   PCI_CLASS_MASS_STORAGE_IPI    0x03
 156 #define   PCI_CLASS_MASS_STORAGE_RAID   0x04
 157 #define   PCI_CLASS_MASS_STORAGE_OTHER  0x80
 158
 159 #define PCI_CLASS_NETWORK             0x02
 160 #define   PCI_CLASS_NETWORK_ETHERNET    0x00
 161 #define   PCI_CLASS_NETWORK_TOKENRING   0x01
 162 #define   PCI_CLASS_NETWORK_FDDI        0x02
 163 #define   PCI_CLASS_NETWORK_ATM         0x03
 164 #define   PCI_CLASS_NETWORK_ISDN        0x04
 165 #define   PCI_CLASS_NETWORK_OTHER       0x80
 166
 167 #define PCI_CLASS_DISPLAY             0x03
 168 #define   PCI_CLASS_DISPLAY_VGA         0x00
 169 #define     PCI_IF_VGA_VGA                0x00
 170 #define     PCI_IF_VGA_8514               0x01
 171 #define   PCI_CLASS_DISPLAY_XGA         0x01
 172 #define   PCI_CLASS_DISPLAY_3D          0x02
 173 #define   PCI_CLASS_DISPLAY_OTHER       0x80
 174 #define   PCI_CLASS_DISPLAY_GFX         0x80
 175
 176 #define PCI_CLASS_MEDIA               0x04
 177 #define   PCI_CLASS_MEDIA_VIDEO         0x00
 178 #define   PCI_CLASS_MEDIA_AUDIO         0x01
 179 #define   PCI_CLASS_MEDIA_TELEPHONE     0x02
 180 #define   PCI_CLASS_MEDIA_OTHER         0x80
 181
 182 #define PCI_CLASS_MEMORY_CONTROLLER   0x05
 183 #define   PCI_CLASS_MEMORY_RAM          0x00
 184 #define   PCI_CLASS_MEMORY_FLASH        0x01
 185 #define   PCI_CLASS_MEMORY_OTHER        0x80
 186
 187 #define PCI_CLASS_BRIDGE              0x06
 188 #define   PCI_CLASS_BRIDGE_HOST         0x00
 189 #define   PCI_CLASS_BRIDGE_ISA          0x01
 190 #define   PCI_CLASS_BRIDGE_EISA         0x02
 191 #define   PCI_CLASS_BRIDGE_MCA          0x03
 192 #define   PCI_CLASS_BRIDGE_P2P          0x04
 193 #define     PCI_IF_BRIDGE_P2P             0x00
 194 #define     PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
 195 #define   PCI_CLASS_BRIDGE_PCMCIA       0x05
 196 #define   PCI_CLASS_BRIDGE_NUBUS        0x06
 197 #define   PCI_CLASS_BRIDGE_CARDBUS      0x07
 198 #define   PCI_CLASS_BRIDGE_RACEWAY      0x08
 199 #define   PCI_CLASS_BRIDGE_OTHER        0x80
 200 #define   PCI_CLASS_BRIDGE_ISA_PDECODE  0x80
 201
 202 #define PCI_CLASS_SCC                 0x07  ///< Simple communications controllers
 203 #define   PCI_SUBCLASS_SERIAL           0x00
 204 #define     PCI_IF_GENERIC_XT             0x00
 205 #define     PCI_IF_16450                  0x01
 206 #define     PCI_IF_16550                  0x02
 207 #define     PCI_IF_16650                  0x03
 208 #define     PCI_IF_16750                  0x04
 209 #define     PCI_IF_16850                  0x05
 210 #define     PCI_IF_16950                  0x06
 211 #define   PCI_SUBCLASS_PARALLEL         0x01
 212 #define     PCI_IF_PARALLEL_PORT          0x00
 213 #define     PCI_IF_BI_DIR_PARALLEL_PORT   0x01
 214 #define     PCI_IF_ECP_PARALLEL_PORT      0x02
 215 #define     PCI_IF_1284_CONTROLLER        0x03
 216 #define     PCI_IF_1284_DEVICE            0xFE
 217 #define   PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
 218 #define   PCI_SUBCLASS_MODEM            0x03
 219 #define     PCI_IF_GENERIC_MODEM          0x00
 220 #define     PCI_IF_16450_MODEM            0x01
 221 #define     PCI_IF_16550_MODEM            0x02
 222 #define     PCI_IF_16650_MODEM            0x03
 223 #define     PCI_IF_16750_MODEM            0x04
 224 #define   PCI_SUBCLASS_SCC_OTHER          0x80
 225
 226 #define PCI_CLASS_SYSTEM_PERIPHERAL   0x08
 227 #define   PCI_SUBCLASS_PIC              0x00
 228 #define     PCI_IF_8259_PIC               0x00
 229 #define     PCI_IF_ISA_PIC                0x01
 230 #define     PCI_IF_EISA_PIC               0x02
 231 #define     PCI_IF_APIC_CONTROLLER        0x10  ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.
 232 #define     PCI_IF_APIC_CONTROLLER2       0x20
 233 #define   PCI_SUBCLASS_DMA              0x01
 234 #define     PCI_IF_8237_DMA               0x00
 235 #define     PCI_IF_ISA_DMA                0x01
 236 #define     PCI_IF_EISA_DMA               0x02
 237 #define   PCI_SUBCLASS_TIMER            0x02
 238 #define     PCI_IF_8254_TIMER             0x00
 239 #define     PCI_IF_ISA_TIMER              0x01
 240 #define     PCI_IF_EISA_TIMER             0x02
 241 #define   PCI_SUBCLASS_RTC              0x03
 242 #define     PCI_IF_GENERIC_RTC            0x00
 243 #define     PCI_IF_ISA_RTC                0x00
 244 #define   PCI_SUBCLASS_PNP_CONTROLLER   0x04    ///< HotPlug Controller
 245 #define   PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
 246
 247 #define PCI_CLASS_INPUT_DEVICE        0x09
 248 #define   PCI_SUBCLASS_KEYBOARD         0x00
 249 #define   PCI_SUBCLASS_PEN              0x01
 250 #define   PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
 251 #define   PCI_SUBCLASS_SCAN_CONTROLLER  0x03
 252 #define   PCI_SUBCLASS_GAMEPORT         0x04
 253 #define     PCI_IF_GAMEPORT               0x00
 254 #define     PCI_IF_GAMEPORT1              0x01
 255 #define   PCI_SUBCLASS_INPUT_OTHER      0x80
 256
 257 #define PCI_CLASS_DOCKING_STATION     0x0A
 258
 259 #define PCI_CLASS_PROCESSOR           0x0B
 260 #define   PCI_SUBCLASS_PROC_386         0x00
 261 #define   PCI_SUBCLASS_PROC_486         0x01
 262 #define   PCI_SUBCLASS_PROC_PENTIUM     0x02
 263 #define   PCI_SUBCLASS_PROC_ALPHA       0x10
 264 #define   PCI_SUBCLASS_PROC_POWERPC     0x20
 265 #define   PCI_SUBCLASS_PROC_MIPS        0x30
 266 #define   PCI_SUBCLASS_PROC_CO_PORC     0x40 ///< Co-Processor
 267
 268 #define PCI_CLASS_SERIAL              0x0C
 269 #define   PCI_CLASS_SERIAL_FIREWIRE     0x00
 270 #define     PCI_IF_1394                   0x00
 271 #define     PCI_IF_1394_OPEN_HCI          0x10
 272 #define   PCI_CLASS_SERIAL_ACCESS_BUS   0x01
 273 #define   PCI_CLASS_SERIAL_SSA          0x02
 274 #define   PCI_CLASS_SERIAL_USB          0x03
 275 #define     PCI_IF_UHCI                   0x00
 276 #define     PCI_IF_OHCI                   0x10
 277 #define     PCI_IF_USB_OTHER              0x80
 278 #define     PCI_IF_USB_DEVICE             0xFE
 279 #define   PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
 280 #define   PCI_CLASS_SERIAL_SMB          0x05
 281
 282 #define PCI_CLASS_WIRELESS            0x0D
 283 #define   PCI_SUBCLASS_IRDA             0x00
 284 #define   PCI_SUBCLASS_IR               0x01
 285 #define   PCI_SUBCLASS_RF               0x02
 286 #define   PCI_SUBCLASS_WIRELESS_OTHER   0x80
 287
 288 #define PCI_CLASS_INTELLIGENT_IO      0x0E
 289
 290 #define PCI_CLASS_SATELLITE           0x0F
 291 #define   PCI_SUBCLASS_TV               0x01
 292 #define   PCI_SUBCLASS_AUDIO            0x02
 293 #define   PCI_SUBCLASS_VOICE            0x03
 294 #define   PCI_SUBCLASS_DATA             0x04
 295
 296 #define PCI_SECURITY_CONTROLLER       0x10   ///< Encryption and decryption controller
 297 #define   PCI_SUBCLASS_NET_COMPUT       0x00
 298 #define   PCI_SUBCLASS_ENTERTAINMENT    0x10
 299 #define   PCI_SUBCLASS_SECURITY_OTHER   0x80
 300
 301 #define PCI_CLASS_DPIO                0x11
 302 #define   PCI_SUBCLASS_DPIO             0x00
 303 #define   PCI_SUBCLASS_DPIO_OTHER       0x80
 304
 305 #define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))
 306 #define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
 307 #define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
 308
 309 #define IS_PCI_DISPLAY(_p)            IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
 310 #define IS_PCI_VGA(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
 311 #define IS_PCI_8514(_p)               IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
 312 #define IS_PCI_GFX(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
 313 #define IS_PCI_OLD(_p)                IS_CLASS1 (_p, PCI_CLASS_OLD)
 314 #define IS_PCI_OLD_VGA(_p)            IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
 315 #define IS_PCI_IDE(_p)                IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
 316 #define IS_PCI_SCSI(_p)               IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
 317 #define IS_PCI_RAID(_p)               IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
 318 #define IS_PCI_LPC(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
 319 #define IS_PCI_P2P(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
 320 #define IS_PCI_P2P_SUB(_p)            IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
 321 #define IS_PCI_16550_SERIAL(_p)       IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
 322 #define IS_PCI_USB(_p)                IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
 323
 324 //
 325 // the definition of Header Type
 326 //
 327 #define HEADER_TYPE_DEVICE            0x00
 328 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
 329 #define HEADER_TYPE_CARDBUS_BRIDGE    0x02
 330 #define HEADER_TYPE_MULTI_FUNCTION    0x80
 331 //
 332 // Mask of Header type
 333 //
 334 #define HEADER_LAYOUT_CODE            0x7f
 335
 336 #define IS_PCI_BRIDGE(_p)             (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
 337 #define IS_CARDBUS_BRIDGE(_p)         (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
 338 #define IS_PCI_MULTI_FUNC(_p)         ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
 339
 340 ///
 341 /// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,
 342 ///
 343 #define PCI_BRIDGE_ROMBAR             0x38
 344
 345 #define PCI_MAX_BAR                   0x0006
 346 #define PCI_MAX_CONFIG_OFFSET         0x0100
 347
 348 #define PCI_VENDOR_ID_OFFSET                        0x00
 349 #define PCI_DEVICE_ID_OFFSET                        0x02
 350 #define PCI_COMMAND_OFFSET                          0x04
 351 #define PCI_PRIMARY_STATUS_OFFSET                   0x06
 352 #define PCI_REVISION_ID_OFFSET                      0x08
 353 #define PCI_CLASSCODE_OFFSET                        0x09
 354 #define PCI_CACHELINE_SIZE_OFFSET                   0x0C
 355 #define PCI_LATENCY_TIMER_OFFSET                    0x0D
 356 #define PCI_HEADER_TYPE_OFFSET                      0x0E
 357 #define PCI_BIST_OFFSET                             0x0F
 358 #define PCI_BASE_ADDRESSREG_OFFSET                  0x10
 359 #define PCI_CARDBUS_CIS_OFFSET                      0x28
 360 #define PCI_SVID_OFFSET                             0x2C ///< SubSystem Vendor id
 361 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET              0x2C
 362 #define PCI_SID_OFFSET                              0x2E ///< SubSystem ID
 363 #define PCI_SUBSYSTEM_ID_OFFSET                     0x2E
 364 #define PCI_EXPANSION_ROM_BASE                      0x30
 365 #define PCI_CAPBILITY_POINTER_OFFSET                0x34
 366 #define PCI_INT_LINE_OFFSET                         0x3C ///< Interrupt Line Register
 367 #define PCI_INT_PIN_OFFSET                          0x3D ///< Interrupt Pin Register
 368 #define PCI_MAXGNT_OFFSET                           0x3E ///< Max Grant Register
 369 #define PCI_MAXLAT_OFFSET                           0x3F ///< Max Latency Register
 370
 371 //
 372 // defined in PCI-to-PCI Bridge Architecture Specification
 373 //
 374 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18
 375 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19
 376 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a
 377 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E
 378 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E
 379
 380 ///
 381 /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
 382 ///
 383 #define PCI_INT_LINE_UNKNOWN                        0xFF
 384
 385 typedef union {
 386   struct {
 387     UINT32  Reg : 8;
 388     UINT32  Func : 3;
 389     UINT32  Dev : 5;
 390     UINT32  Bus : 8;
 391     UINT32  Reserved : 7;
 392     UINT32  Enable : 1;
 393   } Bits;
 394   UINT32  Uint32;
 395 } PCI_CONFIG_ACCESS_CF8;
 396
 397 #pragma pack()
 398
 399 #define EFI_PCI_COMMAND_IO_SPACE                        BIT0   ///< 0x0001
 400 #define EFI_PCI_COMMAND_MEMORY_SPACE                    BIT1   ///< 0x0002
 401 #define EFI_PCI_COMMAND_BUS_MASTER                      BIT2   ///< 0x0004
 402 #define EFI_PCI_COMMAND_SPECIAL_CYCLE                   BIT3   ///< 0x0008
 403 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE     BIT4   ///< 0x0010
 404 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP               BIT5   ///< 0x0020
 405 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND            BIT6   ///< 0x0040
 406 #define EFI_PCI_COMMAND_STEPPING_CONTROL                BIT7   ///< 0x0080
 407 #define EFI_PCI_COMMAND_SERR                            BIT8   ///< 0x0100
 408 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK               BIT9   ///< 0x0200
 409
 410 //
 411 // defined in PCI-to-PCI Bridge Architecture Specification
 412 //
 413 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE    BIT0   ///< 0x0001
 414 #define EFI_PCI_BRIDGE_CONTROL_SERR                     BIT1   ///< 0x0002
 415 #define EFI_PCI_BRIDGE_CONTROL_ISA                      BIT2   ///< 0x0004
 416 #define EFI_PCI_BRIDGE_CONTROL_VGA                      BIT3   ///< 0x0008
 417 #define EFI_PCI_BRIDGE_CONTROL_VGA_16                   BIT4   ///< 0x0010
 418 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT             BIT5   ///< 0x0020
 419 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS      BIT6   ///< 0x0040
 420 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK        BIT7   ///< 0x0080
 421 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER    BIT8   ///< 0x0100
 422 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER  BIT9   ///< 0x0200
 423 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS             BIT10  ///< 0x0400
 424 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR       BIT11  ///< 0x0800
 425
 426 //
 427 // Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
 428 //
 429 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE           BIT7   ///< 0x0080
 430 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE       BIT8   ///< 0x0100
 431 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE       BIT9   ///< 0x0200
 432 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE     BIT10  ///< 0x0400
 433
 434 //
 435 // Following are the PCI status control bit
 436 //
 437 #define EFI_PCI_STATUS_CAPABILITY                       BIT4   ///< 0x0010
 438 #define EFI_PCI_STATUS_66MZ_CAPABLE                     BIT5   ///< 0x0020
 439 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE               BIT7   ///< 0x0080
 440 #define EFI_PCI_MASTER_DATA_PARITY_ERROR                BIT8   ///< 0x0100
 441
 442 ///
 443 /// defined in PC Card Standard
 444 ///
 445 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
 446
 447 #pragma pack(1)
 448 //
 449 // PCI Capability List IDs and records
 450 //
 451 #define EFI_PCI_CAPABILITY_ID_PMI     0x01
 452 #define EFI_PCI_CAPABILITY_ID_AGP     0x02
 453 #define EFI_PCI_CAPABILITY_ID_VPD     0x03
 454 #define EFI_PCI_CAPABILITY_ID_SLOTID  0x04
 455 #define EFI_PCI_CAPABILITY_ID_MSI     0x05
 456 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
 457
 458 ///
 459 /// Capabilities List Header
 460 /// Section 6.7, PCI Local Bus Specification, 2.2
 461 ///
 462 typedef struct {
 463   UINT8 CapabilityID;
 464   UINT8 NextItemPtr;
 465 } EFI_PCI_CAPABILITY_HDR;
 466
 467 ///
 468 /// Power Management Register Block Definition
 469 /// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2
 470 ///
 471 typedef struct {
 472   EFI_PCI_CAPABILITY_HDR  Hdr;
 473   UINT16                  PMC;
 474   UINT16                  PMCSR;
 475   UINT8                   BridgeExtention;
 476   UINT8                   Data;
 477 } EFI_PCI_CAPABILITY_PMI;
 478
 479 ///
 480 /// A.G.P Capability
 481 /// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0
 482 ///
 483 typedef struct {
 484   EFI_PCI_CAPABILITY_HDR  Hdr;
 485   UINT8                   Rev;
 486   UINT8                   Reserved;
 487   UINT32                  Status;
 488   UINT32                  Command;
 489 } EFI_PCI_CAPABILITY_AGP;
 490
 491 ///
 492 /// VPD Capability Structure
 493 /// Appendix I, PCI Local Bus Specification, 2.2
 494 ///
 495 typedef struct {
 496   EFI_PCI_CAPABILITY_HDR  Hdr;
 497   UINT16                  AddrReg;
 498   UINT32                  DataReg;
 499 } EFI_PCI_CAPABILITY_VPD;
 500
 501 ///
 502 /// Slot Numbering Capabilities Register
 503 /// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2
 504 ///
 505 typedef struct {
 506   EFI_PCI_CAPABILITY_HDR  Hdr;
 507   UINT8                   ExpnsSlotReg;
 508   UINT8                   ChassisNo;
 509 } EFI_PCI_CAPABILITY_SLOTID;
 510
 511 ///
 512 /// Message Capability Structure for 32-bit Message Address
 513 /// Section 6.8.1, PCI Local Bus Specification, 2.2
 514 ///
 515 typedef struct {
 516   EFI_PCI_CAPABILITY_HDR  Hdr;
 517   UINT16                  MsgCtrlReg;
 518   UINT32                  MsgAddrReg;
 519   UINT16                  MsgDataReg;
 520 } EFI_PCI_CAPABILITY_MSI32;
 521
 522 ///
 523 /// Message Capability Structure for 64-bit Message Address
 524 /// Section 6.8.1, PCI Local Bus Specification, 2.2
 525 ///
 526 typedef struct {
 527   EFI_PCI_CAPABILITY_HDR  Hdr;
 528   UINT16                  MsgCtrlReg;
 529   UINT32                  MsgAddrRegLsdw;
 530   UINT32                  MsgAddrRegMsdw;
 531   UINT16                  MsgDataReg;
 532 } EFI_PCI_CAPABILITY_MSI64;
 533
 534 ///
 535 /// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,
 536 /// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
 537 ///
 538 typedef struct {
 539   EFI_PCI_CAPABILITY_HDR  Hdr;
 540   ///
 541   /// not finished - fields need to go here
 542   ///
 543 } EFI_PCI_CAPABILITY_HOTPLUG;
 544
 545 #define DEVICE_ID_NOCARE    0xFFFF
 546
 547 #define PCI_ACPI_UNUSED     0
 548 #define PCI_BAR_NOCHANGE    0
 549 #define PCI_BAR_OLD_ALIGN   0xFFFFFFFFFFFFFFFFULL
 550 #define PCI_BAR_EVEN_ALIGN  0xFFFFFFFFFFFFFFFEULL
 551 #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
 552 #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
 553
 554 #define PCI_BAR_IDX0        0x00
 555 #define PCI_BAR_IDX1        0x01
 556 #define PCI_BAR_IDX2        0x02
 557 #define PCI_BAR_IDX3        0x03
 558 #define PCI_BAR_IDX4        0x04
 559 #define PCI_BAR_IDX5        0x05
 560 #define PCI_BAR_ALL         0xFF
 561
 562 ///
 563 /// EFI PCI Option ROM definitions
 564 ///
 565 #define EFI_ROOT_BRIDGE_LIST                            'eprb'
 566 #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE       0x0EF1  ///< defined in UEFI Spec.
 567
 568 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE              0xaa55
 569 #define PCI_DATA_STRUCTURE_SIGNATURE                    SIGNATURE_32 ('P', 'C', 'I', 'R')
 570 #define PCI_CODE_TYPE_PCAT_IMAGE                        0x00
 571 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED         0x0001  ///< defined in UEFI spec.
 572
 573 ///
 574 /// Standard PCI Expansion ROM Header
 575 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
 576 ///
 577 typedef struct {
 578   UINT16  Signature;    ///< 0xaa55
 579   UINT8   Reserved[0x16];
 580   UINT16  PcirOffset;
 581 } PCI_EXPANSION_ROM_HEADER;
 582
 583 ///
 584 /// Legacy ROM Header Extensions
 585 /// Section 6.3.3.1, PCI Local Bus Specification, 2.2
 586 ///
 587 typedef struct {
 588   UINT16  Signature;    ///< 0xaa55
 589   UINT8   Size512;
 590   UINT8   InitEntryPoint[3];
 591   UINT8   Reserved[0x12];
 592   UINT16  PcirOffset;
 593 } EFI_LEGACY_EXPANSION_ROM_HEADER;
 594
 595 ///
 596 /// PCI Data Structure Format
 597 /// Section 6.3.1.2, PCI Local Bus Specification, 2.2
 598 ///
 599 typedef struct {
 600   UINT32  Signature;    ///< "PCIR"
 601   UINT16  VendorId;
 602   UINT16  DeviceId;
 603   UINT16  Reserved0;
 604   UINT16  Length;
 605   UINT8   Revision;
 606   UINT8   ClassCode[3];
 607   UINT16  ImageLength;
 608   UINT16  CodeRevision;
 609   UINT8   CodeType;
 610   UINT8   Indicator;
 611   UINT16  Reserved1;
 612 } PCI_DATA_STRUCTURE;
 613
 614 ///
 615 /// EFI PCI Expansion ROM Header
 616 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
 617 ///
 618 typedef struct {
 619   UINT16  Signature;    ///< 0xaa55
 620   UINT16  InitializationSize;
 621   UINT32  EfiSignature; ///< 0x0EF1
 622   UINT16  EfiSubsystem;
 623   UINT16  EfiMachineType;
 624   UINT16  CompressionType;
 625   UINT8   Reserved[8];
 626   UINT16  EfiImageHeaderOffset;
 627   UINT16  PcirOffset;
 628 } EFI_PCI_EXPANSION_ROM_HEADER;
 629
 630 typedef union {
 631   UINT8                           *Raw;
 632   PCI_EXPANSION_ROM_HEADER        *Generic;
 633   EFI_PCI_EXPANSION_ROM_HEADER    *Efi;
 634   EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;
 635 } EFI_PCI_ROM_HEADER;
 636
 637 #pragma pack()
 638
 639 #endif