MdePkg/Include/IndustryStandard/Pci22.h

   1 /** @file
   2   Support for PCI 2.2 standard.
   3
   4   This file includes the definitions in the following specifications,
   5     PCI Local Bus Specification, 2.2
   6     PCI-to-PCI Bridge Architecture Specification, Revision 1.2
   7     PC Card Standard, 8.0
   8
   9   Copyright (c) 2006 - 2009, Intel Corporation
  10   All rights reserved. This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18 **/
  19
  20 #ifndef _PCI22_H_
  21 #define _PCI22_H_
  22
  23 #define PCI_MAX_BUS     255
  24 #define PCI_MAX_DEVICE  31
  25 #define PCI_MAX_FUNC    7
  26
  27 #pragma pack(1)
  28
  29 ///
  30 /// Common header region in PCI Configuration Space
  31 /// Section 6.1, PCI Local Bus Specification, 2.2
  32 ///
  33 typedef struct {
  34   UINT16  VendorId;
  35   UINT16  DeviceId;
  36   UINT16  Command;
  37   UINT16  Status;
  38   UINT8   RevisionID;
  39   UINT8   ClassCode[3];
  40   UINT8   CacheLineSize;
  41   UINT8   LatencyTimer;
  42   UINT8   HeaderType;
  43   UINT8   BIST;
  44 } PCI_DEVICE_INDEPENDENT_REGION;
  45
  46 ///
  47 /// PCI Device header region in PCI Configuration Space
  48 /// Section 6.1, PCI Local Bus Specification, 2.2
  49 ///
  50 typedef struct {
  51   UINT32  Bar[6];
  52   UINT32  CISPtr;
  53   UINT16  SubsystemVendorID;
  54   UINT16  SubsystemID;
  55   UINT32  ExpansionRomBar;
  56   UINT8   CapabilityPtr;
  57   UINT8   Reserved1[3];
  58   UINT32  Reserved2;
  59   UINT8   InterruptLine;
  60   UINT8   InterruptPin;
  61   UINT8   MinGnt;
  62   UINT8   MaxLat;
  63 } PCI_DEVICE_HEADER_TYPE_REGION;
  64
  65 ///
  66 /// PCI Device Configuration Space
  67 /// Section 6.1, PCI Local Bus Specification, 2.2
  68 ///
  69 typedef struct {
  70   PCI_DEVICE_INDEPENDENT_REGION Hdr;
  71   PCI_DEVICE_HEADER_TYPE_REGION Device;
  72 } PCI_TYPE00;
  73
  74 ///
  75 /// PCI-PCI Bridge header region in PCI Configuration Space
  76 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
  77 ///
  78 typedef struct {
  79   UINT32  Bar[2];
  80   UINT8   PrimaryBus;
  81   UINT8   SecondaryBus;
  82   UINT8   SubordinateBus;
  83   UINT8   SecondaryLatencyTimer;
  84   UINT8   IoBase;
  85   UINT8   IoLimit;
  86   UINT16  SecondaryStatus;
  87   UINT16  MemoryBase;
  88   UINT16  MemoryLimit;
  89   UINT16  PrefetchableMemoryBase;
  90   UINT16  PrefetchableMemoryLimit;
  91   UINT32  PrefetchableBaseUpper32;
  92   UINT32  PrefetchableLimitUpper32;
  93   UINT16  IoBaseUpper16;
  94   UINT16  IoLimitUpper16;
  95   UINT8   CapabilityPtr;
  96   UINT8   Reserved[3];
  97   UINT32  ExpansionRomBAR;
  98   UINT8   InterruptLine;
  99   UINT8   InterruptPin;
 100   UINT16  BridgeControl;
 101 } PCI_BRIDGE_CONTROL_REGISTER;
 102
 103 ///
 104 /// PCI-to-PCI Bridge Configuration Space
 105 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
 106 ///
 107 typedef struct {
 108   PCI_DEVICE_INDEPENDENT_REGION Hdr;
 109   PCI_BRIDGE_CONTROL_REGISTER   Bridge;
 110 } PCI_TYPE01;
 111
 112 typedef union {
 113   PCI_TYPE00  Device;
 114   PCI_TYPE01  Bridge;
 115 } PCI_TYPE_GENERIC;
 116
 117 ///
 118 /// CardBus Conroller Configuration Space,
 119 /// Section 4.5.1, PC Card Standard. 8.0
 120 ///
 121 typedef struct {
 122   UINT32  CardBusSocketReg;     ///< Cardus Socket/ExCA Base
 123   UINT8   Cap_Ptr;
 124   UINT8   Reserved;
 125   UINT16  SecondaryStatus;      ///< Secondary Status
 126   UINT8   PciBusNumber;         ///< PCI Bus Number
 127   UINT8   CardBusBusNumber;     ///< CardBus Bus Number
 128   UINT8   SubordinateBusNumber; ///< Subordinate Bus Number
 129   UINT8   CardBusLatencyTimer;  ///< CardBus Latency Timer
 130   UINT32  MemoryBase0;          ///< Memory Base Register 0
 131   UINT32  MemoryLimit0;         ///< Memory Limit Register 0
 132   UINT32  MemoryBase1;
 133   UINT32  MemoryLimit1;
 134   UINT32  IoBase0;
 135   UINT32  IoLimit0;             ///< I/O Base Register 0
 136   UINT32  IoBase1;              ///< I/O Limit Register 0
 137   UINT32  IoLimit1;
 138   UINT8   InterruptLine;        ///< Interrupt Line
 139   UINT8   InterruptPin;         ///< Interrupt Pin
 140   UINT16  BridgeControl;        ///< Bridge Control
 141 } PCI_CARDBUS_CONTROL_REGISTER;
 142
 143 //
 144 // Definitions of PCI class bytes and manipulation macros.
 145 //
 146 #define PCI_CLASS_OLD                 0x00
 147 #define   PCI_CLASS_OLD_OTHER           0x00
 148 #define   PCI_CLASS_OLD_VGA             0x01
 149
 150 #define PCI_CLASS_MASS_STORAGE        0x01
 151 #define   PCI_CLASS_MASS_STORAGE_SCSI   0x00
 152 #define   PCI_CLASS_MASS_STORAGE_IDE    0x01
 153 #define   PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
 154 #define   PCI_CLASS_MASS_STORAGE_IPI    0x03
 155 #define   PCI_CLASS_MASS_STORAGE_RAID   0x04
 156 #define   PCI_CLASS_MASS_STORAGE_OTHER  0x80
 157
 158 #define PCI_CLASS_NETWORK             0x02
 159 #define   PCI_CLASS_NETWORK_ETHERNET    0x00
 160 #define   PCI_CLASS_NETWORK_TOKENRING   0x01
 161 #define   PCI_CLASS_NETWORK_FDDI        0x02
 162 #define   PCI_CLASS_NETWORK_ATM         0x03
 163 #define   PCI_CLASS_NETWORK_ISDN        0x04
 164 #define   PCI_CLASS_NETWORK_OTHER       0x80
 165
 166 #define PCI_CLASS_DISPLAY             0x03
 167 #define   PCI_CLASS_DISPLAY_VGA         0x00
 168 #define     PCI_IF_VGA_VGA                0x00
 169 #define     PCI_IF_VGA_8514               0x01
 170 #define   PCI_CLASS_DISPLAY_XGA         0x01
 171 #define   PCI_CLASS_DISPLAY_3D          0x02
 172 #define   PCI_CLASS_DISPLAY_OTHER       0x80
 173
 174 #define PCI_CLASS_MEDIA               0x04
 175 #define   PCI_CLASS_MEDIA_VIDEO         0x00
 176 #define   PCI_CLASS_MEDIA_AUDIO         0x01
 177 #define   PCI_CLASS_MEDIA_TELEPHONE     0x02
 178 #define   PCI_CLASS_MEDIA_OTHER         0x80
 179
 180 #define PCI_CLASS_MEMORY_CONTROLLER   0x05
 181 #define   PCI_CLASS_MEMORY_RAM          0x00
 182 #define   PCI_CLASS_MEMORY_FLASH        0x01
 183 #define   PCI_CLASS_MEMORY_OTHER        0x80
 184
 185 #define PCI_CLASS_BRIDGE              0x06
 186 #define   PCI_CLASS_BRIDGE_HOST         0x00
 187 #define   PCI_CLASS_BRIDGE_ISA          0x01
 188 #define   PCI_CLASS_BRIDGE_EISA         0x02
 189 #define   PCI_CLASS_BRIDGE_MCA          0x03
 190 #define   PCI_CLASS_BRIDGE_P2P          0x04
 191 #define     PCI_IF_BRIDGE_P2P             0x00
 192 #define     PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
 193 #define   PCI_CLASS_BRIDGE_PCMCIA       0x05
 194 #define   PCI_CLASS_BRIDGE_NUBUS        0x06
 195 #define   PCI_CLASS_BRIDGE_CARDBUS      0x07
 196 #define   PCI_CLASS_BRIDGE_RACEWAY      0x08
 197 #define   PCI_CLASS_BRIDGE_OTHER        0x80
 198 #define   PCI_CLASS_BRIDGE_ISA_PDECODE  0x80
 199
 200 #define PCI_CLASS_SCC                 0x07  ///< Simple communications controllers
 201 #define   PCI_SUBCLASS_SERIAL           0x00
 202 #define     PCI_IF_GENERIC_XT             0x00
 203 #define     PCI_IF_16450                  0x01
 204 #define     PCI_IF_16550                  0x02
 205 #define     PCI_IF_16650                  0x03
 206 #define     PCI_IF_16750                  0x04
 207 #define     PCI_IF_16850                  0x05
 208 #define     PCI_IF_16950                  0x06
 209 #define   PCI_SUBCLASS_PARALLEL         0x01
 210 #define     PCI_IF_PARALLEL_PORT          0x00
 211 #define     PCI_IF_BI_DIR_PARALLEL_PORT   0x01
 212 #define     PCI_IF_ECP_PARALLEL_PORT      0x02
 213 #define     PCI_IF_1284_CONTROLLER        0x03
 214 #define     PCI_IF_1284_DEVICE            0xFE
 215 #define   PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
 216 #define   PCI_SUBCLASS_MODEM            0x03
 217 #define     PCI_IF_GENERIC_MODEM          0x00
 218 #define     PCI_IF_16450_MODEM            0x01
 219 #define     PCI_IF_16550_MODEM            0x02
 220 #define     PCI_IF_16650_MODEM            0x03
 221 #define     PCI_IF_16750_MODEM            0x04
 222 #define   PCI_SUBCLASS_SCC_OTHER          0x80
 223
 224 #define PCI_CLASS_SYSTEM_PERIPHERAL   0x08
 225 #define   PCI_SUBCLASS_PIC              0x00
 226 #define     PCI_IF_8259_PIC               0x00
 227 #define     PCI_IF_ISA_PIC                0x01
 228 #define     PCI_IF_EISA_PIC               0x02
 229 #define     PCI_IF_APIC_CONTROLLER        0x10  ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.
 230 #define     PCI_IF_APIC_CONTROLLER2       0x20
 231 #define   PCI_SUBCLASS_DMA              0x01
 232 #define     PCI_IF_8237_DMA               0x00
 233 #define     PCI_IF_ISA_DMA                0x01
 234 #define     PCI_IF_EISA_DMA               0x02
 235 #define   PCI_SUBCLASS_TIMER            0x02
 236 #define     PCI_IF_8254_TIMER             0x00
 237 #define     PCI_IF_ISA_TIMER              0x01
 238 #define     PCI_IF_EISA_TIMER             0x02
 239 #define   PCI_SUBCLASS_RTC              0x03
 240 #define     PCI_IF_GENERIC_RTC            0x00
 241 #define     PCI_IF_ISA_RTC                0x00
 242 #define   PCI_SUBCLASS_PNP_CONTROLLER   0x04    ///< HotPlug Controller
 243 #define   PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
 244
 245 #define PCI_CLASS_INPUT_DEVICE        0x09
 246 #define   PCI_SUBCLASS_KEYBOARD         0x00
 247 #define   PCI_SUBCLASS_PEN              0x01
 248 #define   PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
 249 #define   PCI_SUBCLASS_SCAN_CONTROLLER  0x03
 250 #define   PCI_SUBCLASS_GAMEPORT         0x04
 251 #define     PCI_IF_GAMEPORT               0x00
 252 #define     PCI_IF_GAMEPORT1              0x01
 253 #define   PCI_SUBCLASS_INPUT_OTHER      0x80
 254
 255 #define PCI_CLASS_DOCKING_STATION     0x0A
 256
 257 #define PCI_CLASS_PROCESSOR           0x0B
 258 #define   PCI_SUBCLASS_PROC_386         0x00
 259 #define   PCI_SUBCLASS_PROC_486         0x01
 260 #define   PCI_SUBCLASS_PROC_PENTIUM     0x02
 261 #define   PCI_SUBCLASS_PROC_ALPHA       0x10
 262 #define   PCI_SUBCLASS_PROC_POWERPC     0x20
 263 #define   PCI_SUBCLASS_PROC_MIPS        0x30
 264 #define   PCI_SUBCLASS_PROC_CO_PORC     0x40 ///< Co-Processor
 265
 266 #define PCI_CLASS_SERIAL              0x0C
 267 #define   PCI_CLASS_SERIAL_FIREWIRE     0x00
 268 #define     PCI_IF_1394                   0x00
 269 #define     PCI_IF_1394_OPEN_HCI          0x10
 270 #define   PCI_CLASS_SERIAL_ACCESS_BUS   0x01
 271 #define   PCI_CLASS_SERIAL_SSA          0x02
 272 #define   PCI_CLASS_SERIAL_USB          0x03
 273 #define     PCI_IF_UHCI                   0x00
 274 #define     PCI_IF_OHCI                   0x10
 275 #define     PCI_IF_USB_OTHER              0x80
 276 #define     PCI_IF_USB_DEVICE             0xFE
 277 #define   PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
 278 #define   PCI_CLASS_SERIAL_SMB          0x05
 279
 280 #define PCI_CLASS_WIRELESS            0x0D
 281 #define   PCI_SUBCLASS_IRDA             0x00
 282 #define   PCI_SUBCLASS_IR               0x01
 283 #define   PCI_SUBCLASS_RF               0x02
 284 #define   PCI_SUBCLASS_WIRELESS_OTHER   0x80
 285
 286 #define PCI_CLASS_INTELLIGENT_IO      0x0E
 287
 288 #define PCI_CLASS_SATELLITE           0x0F
 289 #define   PCI_SUBCLASS_TV               0x01
 290 #define   PCI_SUBCLASS_AUDIO            0x02
 291 #define   PCI_SUBCLASS_VOICE            0x03
 292 #define   PCI_SUBCLASS_DATA             0x04
 293
 294 #define PCI_SECURITY_CONTROLLER       0x10   ///< Encryption and decryption controller
 295 #define   PCI_SUBCLASS_NET_COMPUT       0x00
 296 #define   PCI_SUBCLASS_ENTERTAINMENT    0x10
 297 #define   PCI_SUBCLASS_SECURITY_OTHER   0x80
 298
 299 #define PCI_CLASS_DPIO                0x11
 300 #define   PCI_SUBCLASS_DPIO             0x00
 301 #define   PCI_SUBCLASS_DPIO_OTHER       0x80
 302
 303 /**
 304   Macro that checks whether the Base Class code of device matched.
 305
 306   @param  _p      Specified device.
 307   @param  c       Base Class code needs matching.
 308
 309   @retval TRUE    Base Class code matches the specified device.
 310   @retval FALSE   Base Class code doesn't match the specified device.
 311
 312 **/
 313 #define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))
 314 /**
 315   Macro that checks whether the Base Class code and Sub-Class code of device matched.
 316
 317   @param  _p      Specified device.
 318   @param  c       Base Class code needs matching.
 319   @param  s       Sub-Class code needs matching.
 320
 321   @retval TRUE    Base Class code and Sub-Class code match the specified device.
 322   @retval FALSE   Base Class code and Sub-Class code don't match the specified device.
 323
 324 **/
 325 #define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
 326 /**
 327   Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
 328
 329   @param  _p      Specified device.
 330   @param  c       Base Class code needs matching.
 331   @param  s       Sub-Class code needs matching.
 332   @param  p       Interface code needs matching.
 333
 334   @retval TRUE    Base Class code, Sub-Class code and Interface code match the specified device.
 335   @retval FALSE   Base Class code, Sub-Class code and Interface code don't match the specified device.
 336
 337 **/
 338 #define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
 339
 340 /**
 341   Macro that checks whether device is a display controller.
 342
 343   @param  _p      Specified device.
 344
 345   @retval TRUE    Device is a display controller.
 346   @retval FALSE   Device is not a display controller.
 347
 348 **/
 349 #define IS_PCI_DISPLAY(_p)            IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
 350 /**
 351   Macro that checks whether device is a VGA-compatible controller.
 352
 353   @param  _p      Specified device.
 354
 355   @retval TRUE    Device is a VGA-compatible controller.
 356   @retval FALSE   Device is not a VGA-compatible controller.
 357
 358 **/
 359 #define IS_PCI_VGA(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
 360 /**
 361   Macro that checks whether device is an 8514-compatible controller.
 362
 363   @param  _p      Specified device.
 364
 365   @retval TRUE    Device is an 8514-compatible controller.
 366   @retval FALSE   Device is not an 8514-compatible controller.
 367
 368 **/
 369 #define IS_PCI_8514(_p)               IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
 370 /**
 371   Macro that checks whether device is built before the Class Code field was defined.
 372
 373   @param  _p      Specified device.
 374
 375   @retval TRUE    Device is an old device.
 376   @retval FALSE   Device is not an old device.
 377
 378 **/
 379 #define IS_PCI_OLD(_p)                IS_CLASS1 (_p, PCI_CLASS_OLD)
 380 /**
 381   Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
 382
 383   @param  _p      Specified device.
 384
 385   @retval TRUE    Device is an old VGA-compatible device.
 386   @retval FALSE   Device is not an old VGA-compatible device.
 387
 388 **/
 389 #define IS_PCI_OLD_VGA(_p)            IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
 390 /**
 391   Macro that checks whether device is an IDE controller.
 392
 393   @param  _p      Specified device.
 394
 395   @retval TRUE    Device is an IDE controller.
 396   @retval FALSE   Device is not an IDE controller.
 397
 398 **/
 399 #define IS_PCI_IDE(_p)                IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
 400 /**
 401   Macro that checks whether device is a SCSI bus controller.
 402
 403   @param  _p      Specified device.
 404
 405   @retval TRUE    Device is a SCSI bus controller.
 406   @retval FALSE   Device is not a SCSI bus controller.
 407
 408 **/
 409 #define IS_PCI_SCSI(_p)               IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
 410 /**
 411   Macro that checks whether device is a RAID controller.
 412
 413   @param  _p      Specified device.
 414
 415   @retval TRUE    Device is a RAID controller.
 416   @retval FALSE   Device is not a RAID controller.
 417
 418 **/
 419 #define IS_PCI_RAID(_p)               IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
 420 /**
 421   Macro that checks whether device is an ISA bridge.
 422
 423   @param  _p      Specified device.
 424
 425   @retval TRUE    Device is an ISA bridge.
 426   @retval FALSE   Device is not an ISA bridge.
 427
 428 **/
 429 #define IS_PCI_LPC(_p)                IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
 430 /**
 431   Macro that checks whether device is a PCI-to-PCI bridge.
 432
 433   @param  _p      Specified device.
 434
 435   @retval TRUE    Device is a PCI-to-PCI bridge.
 436   @retval FALSE   Device is not a PCI-to-PCI bridge.
 437
 438 **/
 439 #define IS_PCI_P2P(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
 440 /**
 441   Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
 442
 443   @param  _p      Specified device.
 444
 445   @retval TRUE    Device is a Subtractive Decode PCI-to-PCI bridge.
 446   @retval FALSE   Device is not a Subtractive Decode PCI-to-PCI bridge.
 447
 448 **/
 449 #define IS_PCI_P2P_SUB(_p)            IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
 450 /**
 451   Macro that checks whether device is a 16550-compatible serial controller.
 452
 453   @param  _p      Specified device.
 454
 455   @retval TRUE    Device is a 16550-compatible serial controller.
 456   @retval FALSE   Device is not a 16550-compatible serial controller.
 457
 458 **/
 459 #define IS_PCI_16550_SERIAL(_p)       IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
 460 /**
 461   Macro that checks whether device is a Universal Serial Bus controller.
 462
 463   @param  _p      Specified device.
 464
 465   @retval TRUE    Device is a Universal Serial Bus controller.
 466   @retval FALSE   Device is not a Universal Serial Bus controller.
 467
 468 **/
 469 #define IS_PCI_USB(_p)                IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
 470
 471 //
 472 // the definition of Header Type
 473 //
 474 #define HEADER_TYPE_DEVICE            0x00
 475 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
 476 #define HEADER_TYPE_CARDBUS_BRIDGE    0x02
 477 #define HEADER_TYPE_MULTI_FUNCTION    0x80
 478 //
 479 // Mask of Header type
 480 //
 481 #define HEADER_LAYOUT_CODE            0x7f
 482 /**
 483   Macro that checks whether device is a PCI-PCI bridge.
 484
 485   @param  _p      Specified device.
 486
 487   @retval TRUE    Device is a PCI-PCI bridge.
 488   @retval FALSE   Device is not a PCI-PCI bridge.
 489
 490 **/
 491 #define IS_PCI_BRIDGE(_p)             (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
 492 /**
 493   Macro that checks whether device is a CardBus bridge.
 494
 495   @param  _p      Specified device.
 496
 497   @retval TRUE    Device is a CardBus bridge.
 498   @retval FALSE   Device is not a CardBus bridge.
 499
 500 **/
 501 #define IS_CARDBUS_BRIDGE(_p)         (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
 502 /**
 503   Macro that checks whether device is a multiple functions device.
 504
 505   @param  _p      Specified device.
 506
 507   @retval TRUE    Device is a multiple functions device.
 508   @retval FALSE   Device is not a multiple functions device.
 509
 510 **/
 511 #define IS_PCI_MULTI_FUNC(_p)         ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
 512
 513 ///
 514 /// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,
 515 ///
 516 #define PCI_BRIDGE_ROMBAR             0x38
 517
 518 #define PCI_MAX_BAR                   0x0006
 519 #define PCI_MAX_CONFIG_OFFSET         0x0100
 520
 521 #define PCI_VENDOR_ID_OFFSET                        0x00
 522 #define PCI_DEVICE_ID_OFFSET                        0x02
 523 #define PCI_COMMAND_OFFSET                          0x04
 524 #define PCI_PRIMARY_STATUS_OFFSET                   0x06
 525 #define PCI_REVISION_ID_OFFSET                      0x08
 526 #define PCI_CLASSCODE_OFFSET                        0x09
 527 #define PCI_CACHELINE_SIZE_OFFSET                   0x0C
 528 #define PCI_LATENCY_TIMER_OFFSET                    0x0D
 529 #define PCI_HEADER_TYPE_OFFSET                      0x0E
 530 #define PCI_BIST_OFFSET                             0x0F
 531 #define PCI_BASE_ADDRESSREG_OFFSET                  0x10
 532 #define PCI_CARDBUS_CIS_OFFSET                      0x28
 533 #define PCI_SVID_OFFSET                             0x2C ///< SubSystem Vendor id
 534 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET              0x2C
 535 #define PCI_SID_OFFSET                              0x2E ///< SubSystem ID
 536 #define PCI_SUBSYSTEM_ID_OFFSET                     0x2E
 537 #define PCI_EXPANSION_ROM_BASE                      0x30
 538 #define PCI_CAPBILITY_POINTER_OFFSET                0x34
 539 #define PCI_INT_LINE_OFFSET                         0x3C ///< Interrupt Line Register
 540 #define PCI_INT_PIN_OFFSET                          0x3D ///< Interrupt Pin Register
 541 #define PCI_MAXGNT_OFFSET                           0x3E ///< Max Grant Register
 542 #define PCI_MAXLAT_OFFSET                           0x3F ///< Max Latency Register
 543
 544 //
 545 // defined in PCI-to-PCI Bridge Architecture Specification
 546 //
 547 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18
 548 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19
 549 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a
 550 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E
 551 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E
 552
 553 ///
 554 /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
 555 ///
 556 #define PCI_INT_LINE_UNKNOWN                        0xFF
 557
 558 ///
 559 /// PCI Access Data Format
 560 ///
 561 typedef union {
 562   struct {
 563     UINT32  Reg : 8;
 564     UINT32  Func : 3;
 565     UINT32  Dev : 5;
 566     UINT32  Bus : 8;
 567     UINT32  Reserved : 7;
 568     UINT32  Enable : 1;
 569   } Bits;
 570   UINT32  Uint32;
 571 } PCI_CONFIG_ACCESS_CF8;
 572
 573 #pragma pack()
 574
 575 #define EFI_PCI_COMMAND_IO_SPACE                        BIT0   ///< 0x0001
 576 #define EFI_PCI_COMMAND_MEMORY_SPACE                    BIT1   ///< 0x0002
 577 #define EFI_PCI_COMMAND_BUS_MASTER                      BIT2   ///< 0x0004
 578 #define EFI_PCI_COMMAND_SPECIAL_CYCLE                   BIT3   ///< 0x0008
 579 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE     BIT4   ///< 0x0010
 580 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP               BIT5   ///< 0x0020
 581 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND            BIT6   ///< 0x0040
 582 #define EFI_PCI_COMMAND_STEPPING_CONTROL                BIT7   ///< 0x0080
 583 #define EFI_PCI_COMMAND_SERR                            BIT8   ///< 0x0100
 584 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK               BIT9   ///< 0x0200
 585
 586 //
 587 // defined in PCI-to-PCI Bridge Architecture Specification
 588 //
 589 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE    BIT0   ///< 0x0001
 590 #define EFI_PCI_BRIDGE_CONTROL_SERR                     BIT1   ///< 0x0002
 591 #define EFI_PCI_BRIDGE_CONTROL_ISA                      BIT2   ///< 0x0004
 592 #define EFI_PCI_BRIDGE_CONTROL_VGA                      BIT3   ///< 0x0008
 593 #define EFI_PCI_BRIDGE_CONTROL_VGA_16                   BIT4   ///< 0x0010
 594 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT             BIT5   ///< 0x0020
 595 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS      BIT6   ///< 0x0040
 596 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK        BIT7   ///< 0x0080
 597 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER    BIT8   ///< 0x0100
 598 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER  BIT9   ///< 0x0200
 599 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS             BIT10  ///< 0x0400
 600 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR       BIT11  ///< 0x0800
 601
 602 //
 603 // Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
 604 //
 605 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE           BIT7   ///< 0x0080
 606 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE       BIT8   ///< 0x0100
 607 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE       BIT9   ///< 0x0200
 608 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE     BIT10  ///< 0x0400
 609
 610 //
 611 // Following are the PCI status control bit
 612 //
 613 #define EFI_PCI_STATUS_CAPABILITY                       BIT4   ///< 0x0010
 614 #define EFI_PCI_STATUS_66MZ_CAPABLE                     BIT5   ///< 0x0020
 615 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE               BIT7   ///< 0x0080
 616 #define EFI_PCI_MASTER_DATA_PARITY_ERROR                BIT8   ///< 0x0100
 617
 618 ///
 619 /// defined in PC Card Standard
 620 ///
 621 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
 622
 623 #pragma pack(1)
 624 //
 625 // PCI Capability List IDs and records
 626 //
 627 #define EFI_PCI_CAPABILITY_ID_PMI     0x01
 628 #define EFI_PCI_CAPABILITY_ID_AGP     0x02
 629 #define EFI_PCI_CAPABILITY_ID_VPD     0x03
 630 #define EFI_PCI_CAPABILITY_ID_SLOTID  0x04
 631 #define EFI_PCI_CAPABILITY_ID_MSI     0x05
 632 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
 633
 634 ///
 635 /// Capabilities List Header
 636 /// Section 6.7, PCI Local Bus Specification, 2.2
 637 ///
 638 typedef struct {
 639   UINT8 CapabilityID;
 640   UINT8 NextItemPtr;
 641 } EFI_PCI_CAPABILITY_HDR;
 642
 643 ///
 644 /// Power Management Register Block Definition
 645 /// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2
 646 ///
 647 typedef struct {
 648   EFI_PCI_CAPABILITY_HDR  Hdr;
 649   UINT16                  PMC;
 650   UINT16                  PMCSR;
 651   UINT8                   BridgeExtention;
 652   UINT8                   Data;
 653 } EFI_PCI_CAPABILITY_PMI;
 654
 655 ///
 656 /// A.G.P Capability
 657 /// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0
 658 ///
 659 typedef struct {
 660   EFI_PCI_CAPABILITY_HDR  Hdr;
 661   UINT8                   Rev;
 662   UINT8                   Reserved;
 663   UINT32                  Status;
 664   UINT32                  Command;
 665 } EFI_PCI_CAPABILITY_AGP;
 666
 667 ///
 668 /// VPD Capability Structure
 669 /// Appendix I, PCI Local Bus Specification, 2.2
 670 ///
 671 typedef struct {
 672   EFI_PCI_CAPABILITY_HDR  Hdr;
 673   UINT16                  AddrReg;
 674   UINT32                  DataReg;
 675 } EFI_PCI_CAPABILITY_VPD;
 676
 677 ///
 678 /// Slot Numbering Capabilities Register
 679 /// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2
 680 ///
 681 typedef struct {
 682   EFI_PCI_CAPABILITY_HDR  Hdr;
 683   UINT8                   ExpnsSlotReg;
 684   UINT8                   ChassisNo;
 685 } EFI_PCI_CAPABILITY_SLOTID;
 686
 687 ///
 688 /// Message Capability Structure for 32-bit Message Address
 689 /// Section 6.8.1, PCI Local Bus Specification, 2.2
 690 ///
 691 typedef struct {
 692   EFI_PCI_CAPABILITY_HDR  Hdr;
 693   UINT16                  MsgCtrlReg;
 694   UINT32                  MsgAddrReg;
 695   UINT16                  MsgDataReg;
 696 } EFI_PCI_CAPABILITY_MSI32;
 697
 698 ///
 699 /// Message Capability Structure for 64-bit Message Address
 700 /// Section 6.8.1, PCI Local Bus Specification, 2.2
 701 ///
 702 typedef struct {
 703   EFI_PCI_CAPABILITY_HDR  Hdr;
 704   UINT16                  MsgCtrlReg;
 705   UINT32                  MsgAddrRegLsdw;
 706   UINT32                  MsgAddrRegMsdw;
 707   UINT16                  MsgDataReg;
 708 } EFI_PCI_CAPABILITY_MSI64;
 709
 710 ///
 711 /// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,
 712 /// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
 713 ///
 714 typedef struct {
 715   EFI_PCI_CAPABILITY_HDR  Hdr;
 716   ///
 717   /// not finished - fields need to go here
 718   ///
 719 } EFI_PCI_CAPABILITY_HOTPLUG;
 720
 721 #define DEVICE_ID_NOCARE    0xFFFF
 722
 723 #define PCI_ACPI_UNUSED     0
 724 #define PCI_BAR_NOCHANGE    0
 725 #define PCI_BAR_OLD_ALIGN   0xFFFFFFFFFFFFFFFFULL
 726 #define PCI_BAR_EVEN_ALIGN  0xFFFFFFFFFFFFFFFEULL
 727 #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
 728 #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
 729
 730 #define PCI_BAR_IDX0        0x00
 731 #define PCI_BAR_IDX1        0x01
 732 #define PCI_BAR_IDX2        0x02
 733 #define PCI_BAR_IDX3        0x03
 734 #define PCI_BAR_IDX4        0x04
 735 #define PCI_BAR_IDX5        0x05
 736 #define PCI_BAR_ALL         0xFF
 737
 738 ///
 739 /// EFI PCI Option ROM definitions
 740 ///
 741 #define EFI_ROOT_BRIDGE_LIST                            'eprb'
 742 #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE       0x0EF1  ///< defined in UEFI Spec.
 743
 744 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE              0xaa55
 745 #define PCI_DATA_STRUCTURE_SIGNATURE                    SIGNATURE_32 ('P', 'C', 'I', 'R')
 746 #define PCI_CODE_TYPE_PCAT_IMAGE                        0x00
 747 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED         0x0001  ///< defined in UEFI spec.
 748
 749 ///
 750 /// Standard PCI Expansion ROM Header
 751 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
 752 ///
 753 typedef struct {
 754   UINT16  Signature;    ///< 0xaa55
 755   UINT8   Reserved[0x16];
 756   UINT16  PcirOffset;
 757 } PCI_EXPANSION_ROM_HEADER;
 758
 759 ///
 760 /// Legacy ROM Header Extensions
 761 /// Section 6.3.3.1, PCI Local Bus Specification, 2.2
 762 ///
 763 typedef struct {
 764   UINT16  Signature;    ///< 0xaa55
 765   UINT8   Size512;
 766   UINT8   InitEntryPoint[3];
 767   UINT8   Reserved[0x12];
 768   UINT16  PcirOffset;
 769 } EFI_LEGACY_EXPANSION_ROM_HEADER;
 770
 771 ///
 772 /// PCI Data Structure Format
 773 /// Section 6.3.1.2, PCI Local Bus Specification, 2.2
 774 ///
 775 typedef struct {
 776   UINT32  Signature;    ///< "PCIR"
 777   UINT16  VendorId;
 778   UINT16  DeviceId;
 779   UINT16  Reserved0;
 780   UINT16  Length;
 781   UINT8   Revision;
 782   UINT8   ClassCode[3];
 783   UINT16  ImageLength;
 784   UINT16  CodeRevision;
 785   UINT8   CodeType;
 786   UINT8   Indicator;
 787   UINT16  Reserved1;
 788 } PCI_DATA_STRUCTURE;
 789
 790 ///
 791 /// EFI PCI Expansion ROM Header
 792 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
 793 ///
 794 typedef struct {
 795   UINT16  Signature;    ///< 0xaa55
 796   UINT16  InitializationSize;
 797   UINT32  EfiSignature; ///< 0x0EF1
 798   UINT16  EfiSubsystem;
 799   UINT16  EfiMachineType;
 800   UINT16  CompressionType;
 801   UINT8   Reserved[8];
 802   UINT16  EfiImageHeaderOffset;
 803   UINT16  PcirOffset;
 804 } EFI_PCI_EXPANSION_ROM_HEADER;
 805
 806 typedef union {
 807   UINT8                           *Raw;
 808   PCI_EXPANSION_ROM_HEADER        *Generic;
 809   EFI_PCI_EXPANSION_ROM_HEADER    *Efi;
 810   EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;
 811 } EFI_PCI_ROM_HEADER;
 812
 813 #pragma pack()
 814
 815 #endif