MdePkg/Include/IndustryStandard/Pci23.h

   1 /** @file
   2   Support for PCI 2.3 standard.
   3
   4   Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php.
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _PCI23_H_
  16 #define _PCI23_H_
  17
  18 #include <IndustryStandard/Pci22.h>
  19
  20 ///
  21 /// PCI_CLASS_MASS_STORAGE, Base Class 01h.
  22 ///
  23 ///@{
  24 #define PCI_CLASS_MASS_STORAGE_ATA       0x05
  25 #define   PCI_IF_MASS_STORAGE_SINGLE_DMA   0x20
  26 #define   PCI_IF_MASS_STORAGE_CHAINED_DMA  0x30
  27 ///@}
  28
  29 ///
  30 /// PCI_CLASS_NETWORK, Base Class 02h.
  31 ///
  32 ///@{
  33 #define PCI_CLASS_NETWORK_WORLDFIP              0x05
  34 #define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06
  35 ///@}
  36
  37 ///
  38 /// PCI_CLASS_BRIDGE, Base Class 06h.
  39 ///
  40 ///@{
  41 #define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P        0x09
  42 #define   PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY   0x40
  43 #define   PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80
  44 #define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI           0x0A
  45 ///@}
  46
  47 ///
  48 /// PCI_CLASS_SCC, Base Class 07h.
  49 ///
  50 ///@{
  51 #define PCI_SUBCLASS_GPIB          0x04
  52 #define PCI_SUBCLASS_SMART_CARD    0x05
  53 ///@}
  54
  55 ///
  56 /// PCI_CLASS_SERIAL, Base Class 0Ch.
  57 ///
  58 ///@{
  59 #define   PCI_IF_EHCI                      0x20
  60 #define PCI_CLASS_SERIAL_IB              0x06
  61 #define PCI_CLASS_SERIAL_IPMI            0x07
  62 #define   PCI_IF_IPMI_SMIC                 0x00
  63 #define   PCI_IF_IPMI_KCS                  0x01 ///< Keyboard Controller Style
  64 #define   PCI_IF_IPMI_BT                   0x02 ///< Block Transfer
  65 #define PCI_CLASS_SERIAL_SERCOS          0x08
  66 #define PCI_CLASS_SERIAL_CANBUS          0x09
  67 ///@}
  68
  69 ///
  70 /// PCI_CLASS_WIRELESS, Base Class 0Dh.
  71 ///
  72 ///@{
  73 #define PCI_SUBCLASS_BLUETOOTH    0x11
  74 #define PCI_SUBCLASS_BROADBAND    0x12
  75 ///@}
  76
  77 ///
  78 /// PCI_CLASS_DPIO, Base Class 11h.
  79 ///
  80 ///@{
  81 #define PCI_SUBCLASS_PERFORMANCE_COUNTERS          0x01
  82 #define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION 0x10
  83 #define PCI_SUBCLASS_MANAGEMENT_CARD               0x20
  84 ///@}
  85
  86 ///
  87 /// defined in PCI Express Spec.
  88 ///
  89 #define PCI_EXP_MAX_CONFIG_OFFSET     0x1000
  90
  91 ///
  92 /// PCI Capability List IDs and records.
  93 ///
  94 #define EFI_PCI_CAPABILITY_ID_PCIX    0x07
  95
  96 #pragma pack(1)
  97 ///
  98 /// PCI-X Capabilities List,
  99 /// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.
 100 ///
 101 typedef struct {
 102   EFI_PCI_CAPABILITY_HDR  Hdr;
 103   UINT16                  CommandReg;
 104   UINT32                  StatusReg;
 105 } EFI_PCI_CAPABILITY_PCIX;
 106
 107 ///
 108 /// PCI-X Bridge Capabilities List,
 109 /// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.
 110 ///
 111 typedef struct {
 112   EFI_PCI_CAPABILITY_HDR  Hdr;
 113   UINT16                  SecStatusReg;
 114   UINT32                  StatusReg;
 115   UINT32                  SplitTransCtrlRegUp;
 116   UINT32                  SplitTransCtrlRegDn;
 117 } EFI_PCI_CAPABILITY_PCIX_BRDG;
 118
 119 #pragma pack()
 120
 121 #define PCI_CODE_TYPE_EFI_IMAGE       0x03
 122
 123 #endif