MdePkg/Include/IndustryStandard/Pci30.h

   1 /** @file
   2   Support for PCI 3.0 standard.
   3
   4   Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #ifndef __PCI30_H__
  10 #define __PCI30_H__
  11
  12 #include <IndustryStandard/Pci23.h>
  13
  14 ///
  15 /// PCI_CLASS_MASS_STORAGE, Base Class 01h.
  16 ///
  17 ///@{
  18 #define PCI_CLASS_MASS_STORAGE_SATADPA  0x06
  19 #define   PCI_IF_MASS_STORAGE_SATA      0x00
  20 #define   PCI_IF_MASS_STORAGE_AHCI      0x01
  21 ///@}
  22
  23 ///
  24 /// PCI_CLASS_WIRELESS, Base Class 0Dh.
  25 ///
  26 ///@{
  27 #define PCI_SUBCLASS_ETHERNET_80211A  0x20
  28 #define PCI_SUBCLASS_ETHERNET_80211B  0x21
  29 ///@}
  30
  31 /**
  32   Macro that checks whether device is a SATA controller.
  33
  34   @param  _p      Specified device.
  35
  36   @retval TRUE    Device is a SATA controller.
  37   @retval FALSE   Device is not a SATA controller.
  38
  39 **/
  40 #define IS_PCI_SATADPA(_p)  IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)
  41
  42 ///
  43 /// PCI Capability List IDs and records
  44 ///
  45 #define EFI_PCI_CAPABILITY_ID_PCIEXP  0x10
  46
  47 #pragma pack(1)
  48
  49 ///
  50 /// PCI Data Structure Format
  51 /// Section 5.1.2, PCI Firmware Specification, Revision 3.0
  52 ///
  53 typedef struct {
  54   UINT32    Signature;  ///< "PCIR"
  55   UINT16    VendorId;
  56   UINT16    DeviceId;
  57   UINT16    DeviceListOffset;
  58   UINT16    Length;
  59   UINT8     Revision;
  60   UINT8     ClassCode[3];
  61   UINT16    ImageLength;
  62   UINT16    CodeRevision;
  63   UINT8     CodeType;
  64   UINT8     Indicator;
  65   UINT16    MaxRuntimeImageLength;
  66   UINT16    ConfigUtilityCodeHeaderOffset;
  67   UINT16    DMTFCLPEntryPointOffset;
  68 } PCI_3_0_DATA_STRUCTURE;
  69
  70 #pragma pack()
  71
  72 #endif