MdePkg/Include/IndustryStandard/PciExpress21.h

   1 /** @file
   2   Support for the latest PCI standard.
   3
   4   Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
   5   (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef _PCIEXPRESS21_H_
  17 #define _PCIEXPRESS21_H_
  18
  19 #include <IndustryStandard/Pci30.h>
  20
  21 /**
  22   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  23   ECAM (Enhanced Configuration Access Mechanism) address. The unused upper bits
  24   of Bus, Device, Function and Register are stripped prior to the generation of
  25   the address.
  26
  27   @param  Bus       PCI Bus number. Range 0..255.
  28   @param  Device    PCI Device number. Range 0..31.
  29   @param  Function  PCI Function number. Range 0..7.
  30   @param  Register  PCI Register number. Range 0..4095.
  31
  32   @return The encode ECAM address.
  33
  34 **/
  35 #define PCI_ECAM_ADDRESS(Bus,Device,Function,Offset) \
  36   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  37
  38 #pragma pack(1)
  39 ///
  40 /// PCI Express Capability Structure
  41 ///
  42 typedef union {
  43   struct {
  44     UINT16 Version : 4;
  45     UINT16 DevicePortType : 4;
  46     UINT16 SlotImplemented : 1;
  47     UINT16 InterruptMessageNumber : 5;
  48     UINT16 Undefined : 1;
  49     UINT16 Reserved : 1;
  50   } Bits;
  51   UINT16   Uint16;
  52 } PCI_REG_PCIE_CAPABILITY;
  53
  54 #define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT                    0
  55 #define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT             1
  56 #define PCIE_DEVICE_PORT_TYPE_ROOT_PORT                        4
  57 #define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT                    5
  58 #define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT                  6
  59 #define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE               7
  60 #define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE               8
  61 #define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9
  62 #define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR     10
  63
  64 typedef union {
  65   struct {
  66     UINT32 MaxPayloadSize : 3;
  67     UINT32 PhantomFunctions : 2;
  68     UINT32 ExtendedTagField : 1;
  69     UINT32 EndpointL0sAcceptableLatency : 3;
  70     UINT32 EndpointL1AcceptableLatency : 3;
  71     UINT32 Undefined : 3;
  72     UINT32 RoleBasedErrorReporting : 1;
  73     UINT32 Reserved : 2;
  74     UINT32 CapturedSlotPowerLimitValue : 8;
  75     UINT32 CapturedSlotPowerLimitScale : 2;
  76     UINT32 FunctionLevelReset : 1;
  77     UINT32 Reserved2 : 3;
  78   } Bits;
  79   UINT32   Uint32;
  80 } PCI_REG_PCIE_DEVICE_CAPABILITY;
  81
  82 typedef union {
  83   struct {
  84     UINT16 CorrectableError : 1;
  85     UINT16 NonFatalError : 1;
  86     UINT16 FatalError : 1;
  87     UINT16 UnsupportedRequest : 1;
  88     UINT16 RelaxedOrdering : 1;
  89     UINT16 MaxPayloadSize : 3;
  90     UINT16 ExtendedTagField : 1;
  91     UINT16 PhantomFunctions : 1;
  92     UINT16 AuxPower : 1;
  93     UINT16 NoSnoop : 1;
  94     UINT16 MaxReadRequestSize : 3;
  95     UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;
  96   } Bits;
  97   UINT16   Uint16;
  98 } PCI_REG_PCIE_DEVICE_CONTROL;
  99
 100 typedef union {
 101   struct {
 102     UINT16 CorrectableError : 1;
 103     UINT16 NonFatalError : 1;
 104     UINT16 FatalError : 1;
 105     UINT16 UnsupportedRequest : 1;
 106     UINT16 AuxPower : 1;
 107     UINT16 TransactionsPending : 1;
 108     UINT16 Reserved : 10;
 109   } Bits;
 110   UINT16   Uint16;
 111 } PCI_REG_PCIE_DEVICE_STATUS;
 112
 113 typedef union {
 114   struct {
 115     UINT32 MaxLinkSpeed : 4;
 116     UINT32 MaxLinkWidth : 6;
 117     UINT32 Aspm : 2;
 118     UINT32 L0sExitLatency : 3;
 119     UINT32 L1ExitLatency : 3;
 120     UINT32 ClockPowerManagement : 1;
 121     UINT32 SurpriseDownError : 1;
 122     UINT32 DataLinkLayerLinkActive : 1;
 123     UINT32 LinkBandwidthNotification : 1;
 124     UINT32 AspmOptionalityCompliance : 1;
 125     UINT32 Reserved : 1;
 126     UINT32 PortNumber : 8;
 127   } Bits;
 128   UINT32   Uint32;
 129 } PCI_REG_PCIE_LINK_CAPABILITY;
 130
 131 #define PCIE_LINK_ASPM_L0S BIT0
 132 #define PCIE_LINK_ASPM_L1  BIT1
 133
 134 typedef union {
 135   struct {
 136     UINT16 AspmControl : 2;
 137     UINT16 Reserved : 1;
 138     UINT16 ReadCompletionBoundary : 1;
 139     UINT16 LinkDisable : 1;
 140     UINT16 RetrainLink : 1;
 141     UINT16 CommonClockConfiguration : 1;
 142     UINT16 ExtendedSynch : 1;
 143     UINT16 ClockPowerManagement : 1;
 144     UINT16 HardwareAutonomousWidthDisable : 1;
 145     UINT16 LinkBandwidthManagementInterrupt : 1;
 146     UINT16 LinkAutonomousBandwidthInterrupt : 1;
 147   } Bits;
 148   UINT16   Uint16;
 149 } PCI_REG_PCIE_LINK_CONTROL;
 150
 151 typedef union {
 152   struct {
 153     UINT16 CurrentLinkSpeed : 4;
 154     UINT16 NegotiatedLinkWidth : 6;
 155     UINT16 Undefined : 1;
 156     UINT16 LinkTraining : 1;
 157     UINT16 SlotClockConfiguration : 1;
 158     UINT16 DataLinkLayerLinkActive : 1;
 159     UINT16 LinkBandwidthManagement : 1;
 160     UINT16 LinkAutonomousBandwidth : 1;
 161   } Bits;
 162   UINT16   Uint16;
 163 } PCI_REG_PCIE_LINK_STATUS;
 164
 165 typedef union {
 166   struct {
 167     UINT32 AttentionButton : 1;
 168     UINT32 PowerController : 1;
 169     UINT32 MrlSensor : 1;
 170     UINT32 AttentionIndicator : 1;
 171     UINT32 PowerIndicator : 1;
 172     UINT32 HotPlugSurprise : 1;
 173     UINT32 HotPlugCapable : 1;
 174     UINT32 SlotPowerLimitValue : 8;
 175     UINT32 SlotPowerLimitScale : 2;
 176     UINT32 ElectromechanicalInterlock : 1;
 177     UINT32 NoCommandCompleted : 1;
 178     UINT32 PhysicalSlotNumber : 13;
 179   } Bits;
 180   UINT32   Uint32;
 181 } PCI_REG_PCIE_SLOT_CAPABILITY;
 182
 183 typedef union {
 184   struct {
 185     UINT16 AttentionButtonPressed : 1;
 186     UINT16 PowerFaultDetected : 1;
 187     UINT16 MrlSensorChanged : 1;
 188     UINT16 PresenceDetectChanged : 1;
 189     UINT16 CommandCompletedInterrupt : 1;
 190     UINT16 HotPlugInterrupt : 1;
 191     UINT16 AttentionIndicator : 2;
 192     UINT16 PowerIndicator : 2;
 193     UINT16 PowerController : 1;
 194     UINT16 ElectromechanicalInterlock : 1;
 195     UINT16 DataLinkLayerStateChanged : 1;
 196     UINT16 Reserved : 3;
 197   } Bits;
 198   UINT16   Uint16;
 199 } PCI_REG_PCIE_SLOT_CONTROL;
 200
 201 typedef union {
 202   struct {
 203     UINT16 AttentionButtonPressed : 1;
 204     UINT16 PowerFaultDetected : 1;
 205     UINT16 MrlSensorChanged : 1;
 206     UINT16 PresenceDetectChanged : 1;
 207     UINT16 CommandCompleted : 1;
 208     UINT16 MrlSensor : 1;
 209     UINT16 PresenceDetect : 1;
 210     UINT16 ElectromechanicalInterlock : 1;
 211     UINT16 DataLinkLayerStateChanged : 1;
 212     UINT16 Reserved : 7;
 213   } Bits;
 214   UINT16   Uint16;
 215 } PCI_REG_PCIE_SLOT_STATUS;
 216
 217 typedef union {
 218   struct {
 219     UINT16 SystemErrorOnCorrectableError : 1;
 220     UINT16 SystemErrorOnNonFatalError : 1;
 221     UINT16 SystemErrorOnFatalError : 1;
 222     UINT16 PmeInterrupt : 1;
 223     UINT16 CrsSoftwareVisibility : 1;
 224     UINT16 Reserved : 11;
 225   } Bits;
 226   UINT16   Uint16;
 227 } PCI_REG_PCIE_ROOT_CONTROL;
 228
 229 typedef union {
 230   struct {
 231     UINT16 CrsSoftwareVisibility : 1;
 232     UINT16 Reserved : 15;
 233   } Bits;
 234   UINT16   Uint16;
 235 } PCI_REG_PCIE_ROOT_CAPABILITY;
 236
 237 typedef union {
 238   struct {
 239     UINT32 PmeRequesterId : 16;
 240     UINT32 PmeStatus : 1;
 241     UINT32 PmePending : 1;
 242     UINT32 Reserved : 14;
 243   } Bits;
 244   UINT32   Uint32;
 245 } PCI_REG_PCIE_ROOT_STATUS;
 246
 247 typedef union {
 248   struct {
 249     UINT32 CompletionTimeoutRanges : 4;
 250     UINT32 CompletionTimeoutDisable : 1;
 251     UINT32 AriForwarding : 1;
 252     UINT32 AtomicOpRouting : 1;
 253     UINT32 AtomicOp32Completer : 1;
 254     UINT32 AtomicOp64Completer : 1;
 255     UINT32 Cas128Completer : 1;
 256     UINT32 NoRoEnabledPrPrPassing : 1;
 257     UINT32 LtrMechanism : 1;
 258     UINT32 TphCompleter : 2;
 259     UINT32 Reserved : 4;
 260     UINT32 Obff : 2;
 261     UINT32 ExtendedFmtField : 1;
 262     UINT32 EndEndTlpPrefix : 1;
 263     UINT32 MaxEndEndTlpPrefixes : 2;
 264     UINT32 Reserved2 : 8;
 265   } Bits;
 266   UINT32   Uint32;
 267 } PCI_REG_PCIE_DEVICE_CAPABILITY2;
 268
 269 #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
 270 #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE    BIT1
 271
 272 typedef union {
 273   struct {
 274     UINT16 CompletionTimeoutValue : 4;
 275     UINT16 CompletionTimeoutDisable : 1;
 276     UINT16 AriForwarding : 1;
 277     UINT16 AtomicOpRequester : 1;
 278     UINT16 AtomicOpEgressBlocking : 1;
 279     UINT16 IdoRequest : 1;
 280     UINT16 IdoCompletion : 1;
 281     UINT16 LtrMechanism : 2;
 282     UINT16 Reserved : 2;
 283     UINT16 Obff : 2;
 284     UINT16 EndEndTlpPrefixBlocking : 1;
 285   } Bits;
 286   UINT16   Uint16;
 287 } PCI_REG_PCIE_DEVICE_CONTROL2;
 288
 289 #define PCIE_COMPLETION_TIMEOUT_50US_50MS   0
 290 #define PCIE_COMPLETION_TIMEOUT_50US_100US  1
 291 #define PCIE_COMPLETION_TIMEOUT_1MS_10MS    2
 292 #define PCIE_COMPLETION_TIMEOUT_16MS_55MS   5
 293 #define PCIE_COMPLETION_TIMEOUT_65MS_210MS  6
 294 #define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9
 295 #define PCIE_COMPLETION_TIMEOUT_1S_3_5S     10
 296 #define PCIE_COMPLETION_TIMEOUT_4S_13S      13
 297 #define PCIE_COMPLETION_TIMEOUT_17S_64S     14
 298
 299 #define PCIE_DEVICE_CONTROL_OBFF_DISABLED  0
 300 #define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1
 301 #define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2
 302 #define PCIE_DEVICE_CONTROL_OBFF_WAKE      3
 303
 304 typedef union {
 305   struct {
 306     UINT32 Reserved : 1;
 307     UINT32 LinkSpeedsVector : 7;
 308     UINT32 Crosslink : 1;
 309     UINT32 Reserved2 : 23;
 310   } Bits;
 311   UINT32   Uint32;
 312 } PCI_REG_PCIE_LINK_CAPABILITY2;
 313
 314 typedef union {
 315   struct {
 316     UINT16 TargetLinkSpeed : 4;
 317     UINT16 EnterCompliance : 1;
 318     UINT16 HardwareAutonomousSpeedDisable : 1;
 319     UINT16 SelectableDeemphasis : 1;
 320     UINT16 TransmitMargin : 3;
 321     UINT16 EnterModifiedCompliance : 1;
 322     UINT16 ComplianceSos : 1;
 323     UINT16 CompliancePresetDeemphasis : 4;
 324   } Bits;
 325   UINT16   Uint16;
 326 } PCI_REG_PCIE_LINK_CONTROL2;
 327
 328 typedef union {
 329   struct {
 330     UINT16 CurrentDeemphasisLevel : 1;
 331     UINT16 EqualizationComplete : 1;
 332     UINT16 EqualizationPhase1Successful : 1;
 333     UINT16 EqualizationPhase2Successful : 1;
 334     UINT16 EqualizationPhase3Successful : 1;
 335     UINT16 LinkEqualizationRequest : 1;
 336     UINT16 Reserved : 10;
 337   } Bits;
 338   UINT16   Uint16;
 339 } PCI_REG_PCIE_LINK_STATUS2;
 340
 341 typedef struct {
 342   EFI_PCI_CAPABILITY_HDR          Hdr;
 343   PCI_REG_PCIE_CAPABILITY         Capability;
 344   PCI_REG_PCIE_DEVICE_CAPABILITY  DeviceCapability;
 345   PCI_REG_PCIE_DEVICE_CONTROL     DeviceControl;
 346   PCI_REG_PCIE_DEVICE_STATUS      DeviceStatus;
 347   PCI_REG_PCIE_LINK_CAPABILITY    LinkCapability;
 348   PCI_REG_PCIE_LINK_CONTROL       LinkControl;
 349   PCI_REG_PCIE_LINK_STATUS        LinkStatus;
 350   PCI_REG_PCIE_SLOT_CAPABILITY    SlotCapability;
 351   PCI_REG_PCIE_SLOT_CONTROL       SlotControl;
 352   PCI_REG_PCIE_SLOT_STATUS        SlotStatus;
 353   PCI_REG_PCIE_ROOT_CONTROL       RootControl;
 354   PCI_REG_PCIE_ROOT_CAPABILITY    RootCapability;
 355   PCI_REG_PCIE_ROOT_STATUS        RootStatus;
 356   PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;
 357   PCI_REG_PCIE_DEVICE_CONTROL2    DeviceControl2;
 358   UINT16                          DeviceStatus2;
 359   PCI_REG_PCIE_LINK_CAPABILITY2   LinkCapability2;
 360   PCI_REG_PCIE_LINK_CONTROL2      LinkControl2;
 361   PCI_REG_PCIE_LINK_STATUS2       LinkStatus2;
 362   UINT32                          SlotCapability2;
 363   UINT16                          SlotControl2;
 364   UINT16                          SlotStatus2;
 365 } PCI_CAPABILITY_PCIEXP;
 366
 367 #define EFI_PCIE_CAPABILITY_BASE_OFFSET                             0x100
 368 #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY          0x10
 369 #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET            0x24
 370 #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING    0x20
 371 #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET                 0x28
 372 #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING         0x20
 373
 374 //
 375 // for SR-IOV
 376 //
 377 #define EFI_PCIE_CAPABILITY_ID_ARI        0x0E
 378 #define EFI_PCIE_CAPABILITY_ID_ATS        0x0F
 379 #define EFI_PCIE_CAPABILITY_ID_SRIOV      0x10
 380 #define EFI_PCIE_CAPABILITY_ID_MRIOV      0x11
 381
 382 typedef struct {
 383   UINT32  CapabilityHeader;
 384   UINT32  Capability;
 385   UINT16  Control;
 386   UINT16  Status;
 387   UINT16  InitialVFs;
 388   UINT16  TotalVFs;
 389   UINT16  NumVFs;
 390   UINT8   FunctionDependencyLink;
 391   UINT8   Reserved0;
 392   UINT16  FirstVFOffset;
 393   UINT16  VFStride;
 394   UINT16  Reserved1;
 395   UINT16  VFDeviceID;
 396   UINT32  SupportedPageSize;
 397   UINT32  SystemPageSize;
 398   UINT32  VFBar[6];
 399   UINT32  VFMigrationStateArrayOffset;
 400 } SR_IOV_CAPABILITY_REGISTER;
 401
 402 #define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES               0x04
 403 #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL                    0x08
 404 #define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS                     0x0A
 405 #define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS                 0x0C
 406 #define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS                   0x0E
 407 #define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS                     0x10
 408 #define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK   0x12
 409 #define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF                    0x14
 410 #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE                   0x16
 411 #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID                 0x1A
 412 #define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE        0x1C
 413 #define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE           0x20
 414 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0                       0x24
 415 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1                       0x28
 416 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2                       0x2C
 417 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3                       0x30
 418 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4                       0x34
 419 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5                       0x38
 420 #define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE         0x3C
 421
 422 typedef struct {
 423   UINT32 CapabilityId:16;
 424   UINT32 CapabilityVersion:4;
 425   UINT32 NextCapabilityOffset:12;
 426 } PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER;
 427
 428 #define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
 429
 430 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID   0x0001
 431 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1
 432 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2
 433
 434 typedef union {
 435   struct {
 436     UINT32 Undefined : 1;
 437     UINT32 Reserved : 3;
 438     UINT32 DataLinkProtocolError : 1;
 439     UINT32 SurpriseDownError : 1;
 440     UINT32 Reserved2 : 6;
 441     UINT32 PoisonedTlp : 1;
 442     UINT32 FlowControlProtocolError : 1;
 443     UINT32 CompletionTimeout : 1;
 444     UINT32 CompleterAbort : 1;
 445     UINT32 UnexpectedCompletion : 1;
 446     UINT32 ReceiverOverflow : 1;
 447     UINT32 MalformedTlp : 1;
 448     UINT32 EcrcError : 1;
 449     UINT32 UnsupportedRequestError : 1;
 450     UINT32 AcsVoilation : 1;
 451     UINT32 UncorrectableInternalError : 1;
 452     UINT32 McBlockedTlp : 1;
 453     UINT32 AtomicOpEgressBlocked : 1;
 454     UINT32 TlpPrefixBlockedError : 1;
 455     UINT32 Reserved3 : 6;
 456   } Bits;
 457   UINT32   Uint32;
 458 } PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;
 459
 460 typedef struct {
 461   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
 462   PCI_EXPRESS_REG_UNCORRECTABLE_ERROR       UncorrectableErrorStatus;
 463   PCI_EXPRESS_REG_UNCORRECTABLE_ERROR       UncorrectableErrorMask;
 464   PCI_EXPRESS_REG_UNCORRECTABLE_ERROR       UncorrectableErrorSeverity;
 465   UINT32                                    CorrectableErrorStatus;
 466   UINT32                                    CorrectableErrorMask;
 467   UINT32                                    AdvancedErrorCapabilitiesAndControl;
 468   UINT32                                    HeaderLog[4];
 469   UINT32                                    RootErrorCommand;
 470   UINT32                                    RootErrorStatus;
 471   UINT16                                    ErrorSourceIdentification;
 472   UINT16                                    CorrectableErrorSourceIdentification;
 473   UINT32                                    TlpPrefixLog[4];
 474 } PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING;
 475
 476 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID    0x0002
 477 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC  0x0009
 478 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1  0x1
 479
 480 typedef struct {
 481   UINT32                                    VcResourceCapability:24;
 482   UINT32                                    PortArbTableOffset:8;
 483   UINT32                                    VcResourceControl;
 484   UINT16                                    Reserved1;
 485   UINT16                                    VcResourceStatus;
 486 } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC;
 487
 488 typedef struct {
 489   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER              Header;
 490   UINT32                                                ExtendedVcCount:3;
 491   UINT32                                                PortVcCapability1:29;
 492   UINT32                                                PortVcCapability2:24;
 493   UINT32                                                VcArbTableOffset:8;
 494   UINT16                                                PortVcControl;
 495   UINT16                                                PortVcStatus;
 496   PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC  Capability[1];
 497 } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY;
 498
 499 #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID    0x0003
 500 #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1  0x1
 501
 502 typedef struct {
 503   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
 504   UINT64                                    SerialNumber;
 505 } PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER;
 506
 507 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID   0x0005
 508 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1
 509
 510 typedef struct {
 511   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
 512   UINT32                                    ElementSelfDescription;
 513   UINT32                                    Reserved;
 514   UINT32                                    LinkEntry[1];
 515 } PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION;
 516
 517 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)
 518
 519 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID   0x0006
 520 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1
 521
 522 typedef struct {
 523   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
 524   UINT32                                    RootComplexLinkCapabilities;
 525   UINT16                                    RootComplexLinkControl;
 526   UINT16                                    RootComplexLinkStatus;
 527 } PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL;
 528
 529 #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID   0x0004
 530 #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1
 531
 532 typedef struct {
 533   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
 534   UINT32                                    DataSelect:8;
 535   UINT32                                    Reserved:24;
 536   UINT32                                    Data;
 537   UINT32                                    PowerBudgetCapability:1;
 538   UINT32                                    Reserved2:7;
 539   UINT32                                    Reserved3:24;
 540 } PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING;
 541
 542 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID   0x000D
 543 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1
 544
 545 typedef struct {
 546   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
 547   UINT16                                    AcsCapability;
 548   UINT16                                    AcsControl;
 549   UINT8                                     EgressControlVectorArray[1];
 550 } PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED;
 551
 552 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))
 553 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))
 554
 555 #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID   0x0007
 556 #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1
 557
 558 typedef struct {
 559   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
 560   UINT32                                    AssociationBitmap;
 561 } PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION;
 562
 563 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID    0x0008
 564 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1  0x1
 565
 566 typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY;
 567
 568 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID   0x000B
 569 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1
 570
 571 typedef struct {
 572   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
 573   UINT32                                    VendorSpecificHeader;
 574   UINT8                                     VendorSpecific[1];
 575 } PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC;
 576
 577 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)
 578
 579 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID   0x000A
 580 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1
 581
 582 typedef struct {
 583   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
 584   UINT16                                    VendorId;
 585   UINT16                                    DeviceId;
 586   UINT32                                    RcrbCapabilities;
 587   UINT32                                    RcrbControl;
 588   UINT32                                    Reserved;
 589 } PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER;
 590
 591 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID   0x0012
 592 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1
 593
 594 typedef struct {
 595   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER  Header;
 596   UINT16                                    MultiCastCapability;
 597   UINT16                                    MulticastControl;
 598   UINT64                                    McBaseAddress;
 599   UINT64                                    McReceiveAddress;
 600   UINT64                                    McBlockAll;
 601   UINT64                                    McBlockUntranslated;
 602   UINT64                                    McOverlayBar;
 603 } PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST;
 604
 605 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID    0x0015
 606 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1  0x1
 607
 608 typedef struct {
 609   UINT32                                                 ResizableBarCapability;
 610   UINT16                                                 ResizableBarControl;
 611   UINT16                                                 Reserved;
 612 } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY;
 613
 614 typedef struct {
 615   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER               Header;
 616   PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY  Capability[1];
 617 } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR;
 618
 619 #define GET_NUMBER_RESIZABLE_BARS(x) (((x->Capability[0].ResizableBarControl) & 0xE0) >> 5)
 620
 621 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID    0x000E
 622 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1  0x1
 623
 624 typedef struct {
 625   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                Header;
 626   UINT16                                                  AriCapability;
 627   UINT16                                                  AriControl;
 628 } PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY;
 629
 630 #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID    0x0016
 631 #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1  0x1
 632
 633 typedef struct {
 634   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                Header;
 635   UINT32                                                  DpaCapability;
 636   UINT32                                                  DpaLatencyIndicator;
 637   UINT16                                                  DpaStatus;
 638   UINT16                                                  DpaControl;
 639   UINT8                                                   DpaPowerAllocationArray[1];
 640 } PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION;
 641
 642 #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))
 643
 644
 645 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID    0x0018
 646 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1  0x1
 647
 648 typedef struct {
 649   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                Header;
 650   UINT16                                                  MaxSnoopLatency;
 651   UINT16                                                  MaxNoSnoopLatency;
 652 } PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING;
 653
 654 #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID    0x0017
 655 #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1  0x1
 656
 657 typedef struct {
 658   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                Header;
 659   UINT32                                                  TphRequesterCapability;
 660   UINT32                                                  TphRequesterControl;
 661   UINT16                                                  TphStTable[1];
 662 } PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH;
 663
 664 #define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)
 665
 666 #pragma pack()
 667
 668 #endif