MdePkg/Include/IndustryStandard/PciExpress21.h

   1 /** @file
   2   Support for the latest PCI standard.
   3
   4   Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
   5   (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #ifndef _PCIEXPRESS21_H_
  11 #define _PCIEXPRESS21_H_
  12
  13 #include <IndustryStandard/Pci30.h>
  14
  15 /**
  16   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  17   ECAM (Enhanced Configuration Access Mechanism) address. The unused upper bits
  18   of Bus, Device, Function and Register are stripped prior to the generation of
  19   the address.
  20
  21   @param  Bus       PCI Bus number. Range 0..255.
  22   @param  Device    PCI Device number. Range 0..31.
  23   @param  Function  PCI Function number. Range 0..7.
  24   @param  Register  PCI Register number. Range 0..4095.
  25
  26   @return The encode ECAM address.
  27
  28 **/
  29 #define PCI_ECAM_ADDRESS(Bus, Device, Function, Offset) \
  30   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  31
  32 #pragma pack(1)
  33 ///
  34 /// PCI Express Capability Structure
  35 ///
  36 typedef union {
  37   struct {
  38     UINT16    Version                : 4;
  39     UINT16    DevicePortType         : 4;
  40     UINT16    SlotImplemented        : 1;
  41     UINT16    InterruptMessageNumber : 5;
  42     UINT16    Undefined              : 1;
  43     UINT16    Reserved               : 1;
  44   } Bits;
  45   UINT16    Uint16;
  46 } PCI_REG_PCIE_CAPABILITY;
  47
  48 #define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT                     0
  49 #define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT              1
  50 #define PCIE_DEVICE_PORT_TYPE_ROOT_PORT                         4
  51 #define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT                     5
  52 #define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT                   6
  53 #define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE                7
  54 #define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE                8
  55 #define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT  9
  56 #define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR      10
  57
  58 typedef union {
  59   struct {
  60     UINT32    MaxPayloadSize               : 3;
  61     UINT32    PhantomFunctions             : 2;
  62     UINT32    ExtendedTagField             : 1;
  63     UINT32    EndpointL0sAcceptableLatency : 3;
  64     UINT32    EndpointL1AcceptableLatency  : 3;
  65     UINT32    Undefined                    : 3;
  66     UINT32    RoleBasedErrorReporting      : 1;
  67     UINT32    Reserved                     : 2;
  68     UINT32    CapturedSlotPowerLimitValue  : 8;
  69     UINT32    CapturedSlotPowerLimitScale  : 2;
  70     UINT32    FunctionLevelReset           : 1;
  71     UINT32    Reserved2                    : 3;
  72   } Bits;
  73   UINT32    Uint32;
  74 } PCI_REG_PCIE_DEVICE_CAPABILITY;
  75
  76 typedef union {
  77   struct {
  78     UINT16    CorrectableError                             : 1;
  79     UINT16    NonFatalError                                : 1;
  80     UINT16    FatalError                                   : 1;
  81     UINT16    UnsupportedRequest                           : 1;
  82     UINT16    RelaxedOrdering                              : 1;
  83     UINT16    MaxPayloadSize                               : 3;
  84     UINT16    ExtendedTagField                             : 1;
  85     UINT16    PhantomFunctions                             : 1;
  86     UINT16    AuxPower                                     : 1;
  87     UINT16    NoSnoop                                      : 1;
  88     UINT16    MaxReadRequestSize                           : 3;
  89     UINT16    BridgeConfigurationRetryOrFunctionLevelReset : 1;
  90   } Bits;
  91   UINT16    Uint16;
  92 } PCI_REG_PCIE_DEVICE_CONTROL;
  93
  94 #define PCIE_MAX_PAYLOAD_SIZE_128B   0
  95 #define PCIE_MAX_PAYLOAD_SIZE_256B   1
  96 #define PCIE_MAX_PAYLOAD_SIZE_512B   2
  97 #define PCIE_MAX_PAYLOAD_SIZE_1024B  3
  98 #define PCIE_MAX_PAYLOAD_SIZE_2048B  4
  99 #define PCIE_MAX_PAYLOAD_SIZE_4096B  5
 100 #define PCIE_MAX_PAYLOAD_SIZE_RVSD1  6
 101 #define PCIE_MAX_PAYLOAD_SIZE_RVSD2  7
 102
 103 #define PCIE_MAX_READ_REQ_SIZE_128B   0
 104 #define PCIE_MAX_READ_REQ_SIZE_256B   1
 105 #define PCIE_MAX_READ_REQ_SIZE_512B   2
 106 #define PCIE_MAX_READ_REQ_SIZE_1024B  3
 107 #define PCIE_MAX_READ_REQ_SIZE_2048B  4
 108 #define PCIE_MAX_READ_REQ_SIZE_4096B  5
 109 #define PCIE_MAX_READ_REQ_SIZE_RVSD1  6
 110 #define PCIE_MAX_READ_REQ_SIZE_RVSD2  7
 111
 112 typedef union {
 113   struct {
 114     UINT16    CorrectableError    : 1;
 115     UINT16    NonFatalError       : 1;
 116     UINT16    FatalError          : 1;
 117     UINT16    UnsupportedRequest  : 1;
 118     UINT16    AuxPower            : 1;
 119     UINT16    TransactionsPending : 1;
 120     UINT16    Reserved            : 10;
 121   } Bits;
 122   UINT16    Uint16;
 123 } PCI_REG_PCIE_DEVICE_STATUS;
 124
 125 typedef union {
 126   struct {
 127     UINT32    MaxLinkSpeed              : 4;
 128     UINT32    MaxLinkWidth              : 6;
 129     UINT32    Aspm                      : 2;
 130     UINT32    L0sExitLatency            : 3;
 131     UINT32    L1ExitLatency             : 3;
 132     UINT32    ClockPowerManagement      : 1;
 133     UINT32    SurpriseDownError         : 1;
 134     UINT32    DataLinkLayerLinkActive   : 1;
 135     UINT32    LinkBandwidthNotification : 1;
 136     UINT32    AspmOptionalityCompliance : 1;
 137     UINT32    Reserved                  : 1;
 138     UINT32    PortNumber                : 8;
 139   } Bits;
 140   UINT32    Uint32;
 141 } PCI_REG_PCIE_LINK_CAPABILITY;
 142
 143 #define PCIE_LINK_ASPM_L0S  BIT0
 144 #define PCIE_LINK_ASPM_L1   BIT1
 145
 146 typedef union {
 147   struct {
 148     UINT16    AspmControl                      : 2;
 149     UINT16    Reserved                         : 1;
 150     UINT16    ReadCompletionBoundary           : 1;
 151     UINT16    LinkDisable                      : 1;
 152     UINT16    RetrainLink                      : 1;
 153     UINT16    CommonClockConfiguration         : 1;
 154     UINT16    ExtendedSynch                    : 1;
 155     UINT16    ClockPowerManagement             : 1;
 156     UINT16    HardwareAutonomousWidthDisable   : 1;
 157     UINT16    LinkBandwidthManagementInterrupt : 1;
 158     UINT16    LinkAutonomousBandwidthInterrupt : 1;
 159   } Bits;
 160   UINT16    Uint16;
 161 } PCI_REG_PCIE_LINK_CONTROL;
 162
 163 typedef union {
 164   struct {
 165     UINT16    CurrentLinkSpeed        : 4;
 166     UINT16    NegotiatedLinkWidth     : 6;
 167     UINT16    Undefined               : 1;
 168     UINT16    LinkTraining            : 1;
 169     UINT16    SlotClockConfiguration  : 1;
 170     UINT16    DataLinkLayerLinkActive : 1;
 171     UINT16    LinkBandwidthManagement : 1;
 172     UINT16    LinkAutonomousBandwidth : 1;
 173   } Bits;
 174   UINT16    Uint16;
 175 } PCI_REG_PCIE_LINK_STATUS;
 176
 177 typedef union {
 178   struct {
 179     UINT32    AttentionButton            : 1;
 180     UINT32    PowerController            : 1;
 181     UINT32    MrlSensor                  : 1;
 182     UINT32    AttentionIndicator         : 1;
 183     UINT32    PowerIndicator             : 1;
 184     UINT32    HotPlugSurprise            : 1;
 185     UINT32    HotPlugCapable             : 1;
 186     UINT32    SlotPowerLimitValue        : 8;
 187     UINT32    SlotPowerLimitScale        : 2;
 188     UINT32    ElectromechanicalInterlock : 1;
 189     UINT32    NoCommandCompleted         : 1;
 190     UINT32    PhysicalSlotNumber         : 13;
 191   } Bits;
 192   UINT32    Uint32;
 193 } PCI_REG_PCIE_SLOT_CAPABILITY;
 194
 195 typedef union {
 196   struct {
 197     UINT16    AttentionButtonPressed     : 1;
 198     UINT16    PowerFaultDetected         : 1;
 199     UINT16    MrlSensorChanged           : 1;
 200     UINT16    PresenceDetectChanged      : 1;
 201     UINT16    CommandCompletedInterrupt  : 1;
 202     UINT16    HotPlugInterrupt           : 1;
 203     UINT16    AttentionIndicator         : 2;
 204     UINT16    PowerIndicator             : 2;
 205     UINT16    PowerController            : 1;
 206     UINT16    ElectromechanicalInterlock : 1;
 207     UINT16    DataLinkLayerStateChanged  : 1;
 208     UINT16    Reserved                   : 3;
 209   } Bits;
 210   UINT16    Uint16;
 211 } PCI_REG_PCIE_SLOT_CONTROL;
 212
 213 typedef union {
 214   struct {
 215     UINT16    AttentionButtonPressed     : 1;
 216     UINT16    PowerFaultDetected         : 1;
 217     UINT16    MrlSensorChanged           : 1;
 218     UINT16    PresenceDetectChanged      : 1;
 219     UINT16    CommandCompleted           : 1;
 220     UINT16    MrlSensor                  : 1;
 221     UINT16    PresenceDetect             : 1;
 222     UINT16    ElectromechanicalInterlock : 1;
 223     UINT16    DataLinkLayerStateChanged  : 1;
 224     UINT16    Reserved                   : 7;
 225   } Bits;
 226   UINT16    Uint16;
 227 } PCI_REG_PCIE_SLOT_STATUS;
 228
 229 typedef union {
 230   struct {
 231     UINT16    SystemErrorOnCorrectableError : 1;
 232     UINT16    SystemErrorOnNonFatalError    : 1;
 233     UINT16    SystemErrorOnFatalError       : 1;
 234     UINT16    PmeInterrupt                  : 1;
 235     UINT16    CrsSoftwareVisibility         : 1;
 236     UINT16    Reserved                      : 11;
 237   } Bits;
 238   UINT16    Uint16;
 239 } PCI_REG_PCIE_ROOT_CONTROL;
 240
 241 typedef union {
 242   struct {
 243     UINT16    CrsSoftwareVisibility : 1;
 244     UINT16    Reserved              : 15;
 245   } Bits;
 246   UINT16    Uint16;
 247 } PCI_REG_PCIE_ROOT_CAPABILITY;
 248
 249 typedef union {
 250   struct {
 251     UINT32    PmeRequesterId : 16;
 252     UINT32    PmeStatus      : 1;
 253     UINT32    PmePending     : 1;
 254     UINT32    Reserved       : 14;
 255   } Bits;
 256   UINT32    Uint32;
 257 } PCI_REG_PCIE_ROOT_STATUS;
 258
 259 typedef union {
 260   struct {
 261     UINT32    CompletionTimeoutRanges                       : 4;
 262     UINT32    CompletionTimeoutDisable                      : 1;
 263     UINT32    AriForwarding                                 : 1;
 264     UINT32    AtomicOpRouting                               : 1;
 265     UINT32    AtomicOp32Completer                           : 1;
 266     UINT32    AtomicOp64Completer                           : 1;
 267     UINT32    Cas128Completer                               : 1;
 268     UINT32    NoRoEnabledPrPrPassing                        : 1;
 269     UINT32    LtrMechanism                                  : 1;
 270     UINT32    TphCompleter                                  : 2;
 271     UINT32    LnSystemCLS                                   : 2;
 272     UINT32    TenBitTagCompleterSupported                   : 1;
 273     UINT32    TenBitTagRequesterSupported                   : 1;
 274     UINT32    Obff                                          : 2;
 275     UINT32    ExtendedFmtField                              : 1;
 276     UINT32    EndEndTlpPrefix                               : 1;
 277     UINT32    MaxEndEndTlpPrefixes                          : 2;
 278     UINT32    EmergencyPowerReductionSupported              : 2;
 279     UINT32    EmergencyPowerReductionInitializationRequired : 1;
 280     UINT32    Reserved3                                     : 4;
 281     UINT32    FrsSupported                                  : 1;
 282   } Bits;
 283   UINT32    Uint32;
 284 } PCI_REG_PCIE_DEVICE_CAPABILITY2;
 285
 286 #define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED            0
 287 #define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED        1
 288 #define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED        2
 289 #define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED      3
 290 #define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED      6
 291 #define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED    7
 292 #define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED    14
 293 #define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED  15
 294
 295 #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE  BIT0
 296 #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE     BIT1
 297
 298 typedef union {
 299   struct {
 300     UINT16    CompletionTimeoutValue         : 4;
 301     UINT16    CompletionTimeoutDisable       : 1;
 302     UINT16    AriForwarding                  : 1;
 303     UINT16    AtomicOpRequester              : 1;
 304     UINT16    AtomicOpEgressBlocking         : 1;
 305     UINT16    IdoRequest                     : 1;
 306     UINT16    IdoCompletion                  : 1;
 307     UINT16    LtrMechanism                   : 1;
 308     UINT16    EmergencyPowerReductionRequest : 1;
 309     UINT16    TenBitTagRequesterEnable       : 1;
 310     UINT16    Obff                           : 2;
 311     UINT16    EndEndTlpPrefixBlocking        : 1;
 312   } Bits;
 313   UINT16    Uint16;
 314 } PCI_REG_PCIE_DEVICE_CONTROL2;
 315
 316 #define PCIE_COMPLETION_TIMEOUT_50US_50MS    0
 317 #define PCIE_COMPLETION_TIMEOUT_50US_100US   1
 318 #define PCIE_COMPLETION_TIMEOUT_1MS_10MS     2
 319 #define PCIE_COMPLETION_TIMEOUT_16MS_55MS    5
 320 #define PCIE_COMPLETION_TIMEOUT_65MS_210MS   6
 321 #define PCIE_COMPLETION_TIMEOUT_260MS_900MS  9
 322 #define PCIE_COMPLETION_TIMEOUT_1S_3_5S      10
 323 #define PCIE_COMPLETION_TIMEOUT_4S_13S       13
 324 #define PCIE_COMPLETION_TIMEOUT_17S_64S      14
 325
 326 #define PCIE_DEVICE_CONTROL_OBFF_DISABLED   0
 327 #define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A  1
 328 #define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B  2
 329 #define PCIE_DEVICE_CONTROL_OBFF_WAKE       3
 330
 331 typedef union {
 332   struct {
 333     UINT32    Reserved         : 1;
 334     UINT32    LinkSpeedsVector : 7;
 335     UINT32    Crosslink        : 1;
 336     UINT32    Reserved2        : 23;
 337   } Bits;
 338   UINT32    Uint32;
 339 } PCI_REG_PCIE_LINK_CAPABILITY2;
 340
 341 typedef union {
 342   struct {
 343     UINT16    TargetLinkSpeed                : 4;
 344     UINT16    EnterCompliance                : 1;
 345     UINT16    HardwareAutonomousSpeedDisable : 1;
 346     UINT16    SelectableDeemphasis           : 1;
 347     UINT16    TransmitMargin                 : 3;
 348     UINT16    EnterModifiedCompliance        : 1;
 349     UINT16    ComplianceSos                  : 1;
 350     UINT16    CompliancePresetDeemphasis     : 4;
 351   } Bits;
 352   UINT16    Uint16;
 353 } PCI_REG_PCIE_LINK_CONTROL2;
 354
 355 typedef union {
 356   struct {
 357     UINT16    CurrentDeemphasisLevel       : 1;
 358     UINT16    EqualizationComplete         : 1;
 359     UINT16    EqualizationPhase1Successful : 1;
 360     UINT16    EqualizationPhase2Successful : 1;
 361     UINT16    EqualizationPhase3Successful : 1;
 362     UINT16    LinkEqualizationRequest      : 1;
 363     UINT16    Reserved                     : 10;
 364   } Bits;
 365   UINT16    Uint16;
 366 } PCI_REG_PCIE_LINK_STATUS2;
 367
 368 typedef struct {
 369   EFI_PCI_CAPABILITY_HDR             Hdr;
 370   PCI_REG_PCIE_CAPABILITY            Capability;
 371   PCI_REG_PCIE_DEVICE_CAPABILITY     DeviceCapability;
 372   PCI_REG_PCIE_DEVICE_CONTROL        DeviceControl;
 373   PCI_REG_PCIE_DEVICE_STATUS         DeviceStatus;
 374   PCI_REG_PCIE_LINK_CAPABILITY       LinkCapability;
 375   PCI_REG_PCIE_LINK_CONTROL          LinkControl;
 376   PCI_REG_PCIE_LINK_STATUS           LinkStatus;
 377   PCI_REG_PCIE_SLOT_CAPABILITY       SlotCapability;
 378   PCI_REG_PCIE_SLOT_CONTROL          SlotControl;
 379   PCI_REG_PCIE_SLOT_STATUS           SlotStatus;
 380   PCI_REG_PCIE_ROOT_CONTROL          RootControl;
 381   PCI_REG_PCIE_ROOT_CAPABILITY       RootCapability;
 382   PCI_REG_PCIE_ROOT_STATUS           RootStatus;
 383   PCI_REG_PCIE_DEVICE_CAPABILITY2    DeviceCapability2;
 384   PCI_REG_PCIE_DEVICE_CONTROL2       DeviceControl2;
 385   UINT16                             DeviceStatus2;
 386   PCI_REG_PCIE_LINK_CAPABILITY2      LinkCapability2;
 387   PCI_REG_PCIE_LINK_CONTROL2         LinkControl2;
 388   PCI_REG_PCIE_LINK_STATUS2          LinkStatus2;
 389   UINT32                             SlotCapability2;
 390   UINT16                             SlotControl2;
 391   UINT16                             SlotStatus2;
 392 } PCI_CAPABILITY_PCIEXP;
 393
 394 #define EFI_PCIE_CAPABILITY_BASE_OFFSET                           0x100
 395 #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY        0x10
 396 #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET          0x24
 397 #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING  0x20
 398 #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET               0x28
 399 #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING       0x20
 400
 401 //
 402 // for SR-IOV
 403 //
 404 #define EFI_PCIE_CAPABILITY_ID_ARI    0x0E
 405 #define EFI_PCIE_CAPABILITY_ID_ATS    0x0F
 406 #define EFI_PCIE_CAPABILITY_ID_SRIOV  0x10
 407 #define EFI_PCIE_CAPABILITY_ID_MRIOV  0x11
 408
 409 typedef struct {
 410   UINT32    CapabilityHeader;
 411   UINT32    Capability;
 412   UINT16    Control;
 413   UINT16    Status;
 414   UINT16    InitialVFs;
 415   UINT16    TotalVFs;
 416   UINT16    NumVFs;
 417   UINT8     FunctionDependencyLink;
 418   UINT8     Reserved0;
 419   UINT16    FirstVFOffset;
 420   UINT16    VFStride;
 421   UINT16    Reserved1;
 422   UINT16    VFDeviceID;
 423   UINT32    SupportedPageSize;
 424   UINT32    SystemPageSize;
 425   UINT32    VFBar[6];
 426   UINT32    VFMigrationStateArrayOffset;
 427 } SR_IOV_CAPABILITY_REGISTER;
 428
 429 #define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES              0x04
 430 #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL                   0x08
 431 #define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS                    0x0A
 432 #define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS                0x0C
 433 #define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS                  0x0E
 434 #define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS                    0x10
 435 #define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK  0x12
 436 #define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF                   0x14
 437 #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE                  0x16
 438 #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID                0x1A
 439 #define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE       0x1C
 440 #define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE          0x20
 441 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0                      0x24
 442 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1                      0x28
 443 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2                      0x2C
 444 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3                      0x30
 445 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4                      0x34
 446 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5                      0x38
 447 #define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE        0x3C
 448
 449 typedef struct {
 450   UINT32    CapabilityId         : 16;
 451   UINT32    CapabilityVersion    : 4;
 452   UINT32    NextCapabilityOffset : 12;
 453 } PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER;
 454
 455 #define PCI_EXP_EXT_HDR  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
 456
 457 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID    0x0001
 458 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1  0x1
 459 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2  0x2
 460
 461 typedef union {
 462   struct {
 463     UINT32    Undefined                  : 1;
 464     UINT32    Reserved                   : 3;
 465     UINT32    DataLinkProtocolError      : 1;
 466     UINT32    SurpriseDownError          : 1;
 467     UINT32    Reserved2                  : 6;
 468     UINT32    PoisonedTlp                : 1;
 469     UINT32    FlowControlProtocolError   : 1;
 470     UINT32    CompletionTimeout          : 1;
 471     UINT32    CompleterAbort             : 1;
 472     UINT32    UnexpectedCompletion       : 1;
 473     UINT32    ReceiverOverflow           : 1;
 474     UINT32    MalformedTlp               : 1;
 475     UINT32    EcrcError                  : 1;
 476     UINT32    UnsupportedRequestError    : 1;
 477     UINT32    AcsVoilation               : 1;
 478     UINT32    UncorrectableInternalError : 1;
 479     UINT32    McBlockedTlp               : 1;
 480     UINT32    AtomicOpEgressBlocked      : 1;
 481     UINT32    TlpPrefixBlockedError      : 1;
 482     UINT32    Reserved3                  : 6;
 483   } Bits;
 484   UINT32    Uint32;
 485 } PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;
 486
 487 typedef struct {
 488   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER    Header;
 489   PCI_EXPRESS_REG_UNCORRECTABLE_ERROR         UncorrectableErrorStatus;
 490   PCI_EXPRESS_REG_UNCORRECTABLE_ERROR         UncorrectableErrorMask;
 491   PCI_EXPRESS_REG_UNCORRECTABLE_ERROR         UncorrectableErrorSeverity;
 492   UINT32                                      CorrectableErrorStatus;
 493   UINT32                                      CorrectableErrorMask;
 494   UINT32                                      AdvancedErrorCapabilitiesAndControl;
 495   UINT32                                      HeaderLog[4];
 496   UINT32                                      RootErrorCommand;
 497   UINT32                                      RootErrorStatus;
 498   UINT16                                      ErrorSourceIdentification;
 499   UINT16                                      CorrectableErrorSourceIdentification;
 500   UINT32                                      TlpPrefixLog[4];
 501 } PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING;
 502
 503 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID    0x0002
 504 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC  0x0009
 505 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1  0x1
 506
 507 typedef struct {
 508   UINT32    VcResourceCapability : 24;
 509   UINT32    PortArbTableOffset   : 8;
 510   UINT32    VcResourceControl;
 511   UINT16    Reserved1;
 512   UINT16    VcResourceStatus;
 513 } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC;
 514
 515 typedef struct {
 516   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                Header;
 517   UINT32                                                  ExtendedVcCount   : 3;
 518   UINT32                                                  PortVcCapability1 : 29;
 519   UINT32                                                  PortVcCapability2 : 24;
 520   UINT32                                                  VcArbTableOffset  : 8;
 521   UINT16                                                  PortVcControl;
 522   UINT16                                                  PortVcStatus;
 523   PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC    Capability[1];
 524 } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY;
 525
 526 #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID    0x0003
 527 #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1  0x1
 528
 529 typedef struct {
 530   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER    Header;
 531   UINT64                                      SerialNumber;
 532 } PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER;
 533
 534 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID    0x0005
 535 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1  0x1
 536
 537 typedef struct {
 538   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER    Header;
 539   UINT32                                      ElementSelfDescription;
 540   UINT32                                      Reserved;
 541   UINT32                                      LinkEntry[1];
 542 } PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION;
 543
 544 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION)  (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)
 545
 546 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID    0x0006
 547 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1  0x1
 548
 549 typedef struct {
 550   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER    Header;
 551   UINT32                                      RootComplexLinkCapabilities;
 552   UINT16                                      RootComplexLinkControl;
 553   UINT16                                      RootComplexLinkStatus;
 554 } PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL;
 555
 556 #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID    0x0004
 557 #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1  0x1
 558
 559 typedef struct {
 560   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER    Header;
 561   UINT32                                      DataSelect            : 8;
 562   UINT32                                      Reserved              : 24;
 563   UINT32                                      Data;
 564   UINT32                                      PowerBudgetCapability : 1;
 565   UINT32                                      Reserved2             : 7;
 566   UINT32                                      Reserved3             : 24;
 567 } PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING;
 568
 569 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID    0x000D
 570 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1  0x1
 571
 572 typedef struct {
 573   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER    Header;
 574   UINT16                                      AcsCapability;
 575   UINT16                                      AcsControl;
 576   UINT8                                       EgressControlVectorArray[1];
 577 } PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED;
 578
 579 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED)      (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))
 580 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED)  (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))
 581
 582 #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID    0x0007
 583 #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1  0x1
 584
 585 typedef struct {
 586   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER    Header;
 587   UINT32                                      AssociationBitmap;
 588 } PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION;
 589
 590 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID    0x0008
 591 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1  0x1
 592
 593 typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY;
 594
 595 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID    0x000B
 596 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1  0x1
 597
 598 typedef struct {
 599   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER    Header;
 600   UINT32                                      VendorSpecificHeader;
 601   UINT8                                       VendorSpecific[1];
 602 } PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC;
 603
 604 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR)  (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)
 605
 606 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID    0x000A
 607 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1  0x1
 608
 609 typedef struct {
 610   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER    Header;
 611   UINT16                                      VendorId;
 612   UINT16                                      DeviceId;
 613   UINT32                                      RcrbCapabilities;
 614   UINT32                                      RcrbControl;
 615   UINT32                                      Reserved;
 616 } PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER;
 617
 618 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID    0x0012
 619 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1  0x1
 620
 621 typedef struct {
 622   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER    Header;
 623   UINT16                                      MultiCastCapability;
 624   UINT16                                      MulticastControl;
 625   UINT64                                      McBaseAddress;
 626   UINT64                                      McReceiveAddress;
 627   UINT64                                      McBlockAll;
 628   UINT64                                      McBlockUntranslated;
 629   UINT64                                      McOverlayBar;
 630 } PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST;
 631
 632 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID    0x0015
 633 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1  0x1
 634
 635 typedef union {
 636   struct {
 637     UINT32    Reserved          : 4;
 638     UINT32    BarSizeCapability : 28;
 639   } Bits;
 640   UINT32    Uint32;
 641 } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY;
 642
 643 typedef union {
 644   struct {
 645     UINT32    BarIndex           : 3;
 646     UINT32    Reserved           : 2;
 647     UINT32    ResizableBarNumber : 3;
 648     UINT32    BarSize            : 6;
 649     UINT32    Reserved2          : 2;
 650     UINT32    BarSizeCapability  : 16;
 651   } Bits;
 652   UINT32    Uint32;
 653 } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL;
 654
 655 typedef struct {
 656   PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY    ResizableBarCapability;
 657   PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL       ResizableBarControl;
 658 } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY;
 659
 660 typedef struct {
 661   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                 Header;
 662   PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY    Capability[1];
 663 } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR;
 664
 665 #define GET_NUMBER_RESIZABLE_BARS(x)  (x->Capability[0].ResizableBarControl.Bits.ResizableBarNumber)
 666
 667 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID    0x000E
 668 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1  0x1
 669
 670 typedef struct {
 671   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER    Header;
 672   UINT16                                      AriCapability;
 673   UINT16                                      AriControl;
 674 } PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY;
 675
 676 #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID    0x0016
 677 #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1  0x1
 678
 679 typedef struct {
 680   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER    Header;
 681   UINT32                                      DpaCapability;
 682   UINT32                                      DpaLatencyIndicator;
 683   UINT16                                      DpaStatus;
 684   UINT16                                      DpaControl;
 685   UINT8                                       DpaPowerAllocationArray[1];
 686 } PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION;
 687
 688 #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER)  (UINT16)(((POWER->DpaCapability)&0x0000000F))
 689
 690 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID    0x0018
 691 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1  0x1
 692
 693 typedef struct {
 694   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER    Header;
 695   UINT16                                      MaxSnoopLatency;
 696   UINT16                                      MaxNoSnoopLatency;
 697 } PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING;
 698
 699 #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID    0x0017
 700 #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1  0x1
 701
 702 typedef struct {
 703   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER    Header;
 704   UINT32                                      TphRequesterCapability;
 705   UINT32                                      TphRequesterControl;
 706   UINT16                                      TphStTable[1];
 707 } PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH;
 708
 709 #define GET_TPH_TABLE_SIZE(x)  ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)
 710
 711 #pragma pack()
 712
 713 #endif