MdePkg/Include/IndustryStandard/PciExpress40.h

   1 /** @file
   2 Support for the PCI Express 4.0 standard.
   3
   4 This header file may not define all structures.  Please extend as required.
   5
   6 Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>
   7 This program and the accompanying materials
   8 are licensed and made available under the terms and conditions of the BSD License
   9 which accompanies this distribution.  The full text of the license may be found at
  10 http://opensource.org/licenses/bsd-license.php
  11
  12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 #ifndef _PCIEXPRESS40_H_
  18 #define _PCIEXPRESS40_H_
  19
  20 #include <IndustryStandard/PciExpress31.h>
  21
  22 #pragma pack(1)
  23
  24 /// The Physical Layer PCI Express Extended Capability definitions.
  25 ///
  26 /// Based on section 7.7.5 of PCI Express Base Specification 4.0.
  27 ///@{
  28 #define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID    0x0026
  29 #define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1  0x1
  30
  31 // Register offsets from Physical Layer PCI-E Ext Cap Header
  32 #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET                         0x04
  33 #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET                              0x08
  34 #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET                               0x0C
  35 #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET             0x10
  36 #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET     0x14
  37 #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET    0x18
  38 #define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET            0x20
  39
  40 typedef union {
  41   struct {
  42     UINT32 Reserved                  : 32; // Reserved bit 0:31
  43   } Bits;
  44   UINT32   Uint32;
  45 } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES;
  46
  47 typedef union {
  48   struct {
  49     UINT32 Reserved                  : 32; // Reserved bit 0:31
  50   } Bits;
  51   UINT32   Uint32;
  52 } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL;
  53
  54 typedef union {
  55   struct {
  56     UINT32 EqualizationComplete      : 1; // bit 0
  57     UINT32 EqualizationPhase1Success : 1; // bit 1
  58     UINT32 EqualizationPhase2Success : 1; // bit 2
  59     UINT32 EqualizationPhase3Success : 1; // bit 3
  60     UINT32 LinkEqualizationRequest   : 1; // bit 4
  61     UINT32 Reserved                  : 27; // Reserved bit 5:31
  62   } Bits;
  63   UINT32   Uint32;
  64 } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS;
  65
  66 typedef union {
  67   struct {
  68     UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3
  69     UINT8 UpstreamPortTransmitterPreset   : 4; //bit 4..7
  70   } Bits;
  71   UINT8   Uint8;
  72 } PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL;
  73
  74 typedef struct {
  75   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                      Header;
  76   PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES              Capablities;
  77   PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL                   Control;
  78   PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS                    Status;
  79   UINT32                                                        LocalDataParityMismatchStatus;
  80   UINT32                                                        FirstRetimerDataParityMismatchStatus;
  81   UINT32                                                        SecondRetimerDataParityMismatchStatus;
  82   UINT32                                                        Reserved;
  83   PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
  84 } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
  85 ///@}
  86
  87 #pragma pack()
  88
  89 #endif