MdePkg/Include/IndustryStandard/Sal.h

   1 /** @file
   2   Main SAL API's defined in Intel Itanium Processor Family System Abstraction
   3   Layer Specification Revision 3.2 (December 2003)
   4
   5 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #ifndef __SAL_API_H__
  11 #define __SAL_API_H__
  12
  13 ///
  14 /// SAL return status type
  15 ///
  16 typedef INTN EFI_SAL_STATUS;
  17
  18 ///
  19 /// Call completed without error.
  20 ///
  21 #define EFI_SAL_SUCCESS               ((EFI_SAL_STATUS) 0)
  22 ///
  23 /// Call completed without error, but some information was lost due to overflow.
  24 ///
  25 #define EFI_SAL_OVERFLOW              ((EFI_SAL_STATUS) 1)
  26 ///
  27 /// Call completed without error; effect a warm boot of the system to complete the update.
  28 ///
  29 #define EFI_SAL_WARM_BOOT_NEEDED      ((EFI_SAL_STATUS) 2)
  30 ///
  31 /// More information is available for retrieval.
  32 ///
  33 #define EFI_SAL_MORE_RECORDS          ((EFI_SAL_STATUS) 3)
  34 ///
  35 /// Not implemented.
  36 ///
  37 #define EFI_SAL_NOT_IMPLEMENTED       ((EFI_SAL_STATUS) - 1)
  38 ///
  39 /// Invalid Argument.
  40 ///
  41 #define EFI_SAL_INVALID_ARGUMENT      ((EFI_SAL_STATUS) - 2)
  42 ///
  43 /// Call completed without error.
  44 ///
  45 #define EFI_SAL_ERROR                 ((EFI_SAL_STATUS) - 3)
  46 ///
  47 /// Virtual address not registered.
  48 ///
  49 #define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
  50 ///
  51 /// No information available.
  52 ///
  53 #define EFI_SAL_NO_INFORMATION        ((EFI_SAL_STATUS) - 5)
  54 ///
  55 /// Scratch buffer required.
  56 ///
  57 #define EFI_SAL_NOT_ENOUGH_SCRATCH    ((EFI_SAL_STATUS) - 9)
  58
  59 ///
  60 /// Return registers from SAL.
  61 ///
  62 typedef struct {
  63   ///
  64   /// SAL return status value in r8.
  65   ///
  66   EFI_SAL_STATUS  Status;
  67   ///
  68   /// SAL returned value in r9.
  69   ///
  70   UINTN           r9;
  71   ///
  72   /// SAL returned value in r10.
  73   ///
  74   UINTN           r10;
  75   ///
  76   /// SAL returned value in r11.
  77   ///
  78   UINTN           r11;
  79 } SAL_RETURN_REGS;
  80
  81 /**
  82   Prototype of SAL procedures.
  83
  84   @param  FunctionId         Functional identifier.
  85                              The upper 32 bits are ignored and only the lower 32 bits
  86                              are used. The following functional identifiers are defined:
  87                              0x01XXXXXX - Architected SAL functional group.
  88                              0x02XXXXXX to 0x03XXXXXX - OEM SAL functional group. Each OEM is
  89                              allowed to use the entire range in the 0x02XXXXXX to 0x03XXXXXX range.
  90                              0x04XXXXXX to 0xFFFFFFFF - Reserved.
  91   @param  Arg1               The first parameter of the architected/OEM specific SAL functions.
  92   @param  Arg2               The second parameter of the architected/OEM specific SAL functions.
  93   @param  Arg3               The third parameter passed to the ESAL function based.
  94   @param  Arg4               The fourth parameter passed to the ESAL function based.
  95   @param  Arg5               The fifth parameter passed to the ESAL function based.
  96   @param  Arg6               The sixth parameter passed to the ESAL function.
  97   @param  Arg7               The seventh parameter passed to the ESAL function based.
  98
  99   @return r8                 Return status: positive number indicates successful,
 100                              negative number indicates failure.
 101           r9                 Other return parameter in r9.
 102           r10                Other return parameter in r10.
 103           r11                Other return parameter in r11.
 104
 105 **/
 106 typedef
 107 SAL_RETURN_REGS
 108 (EFIAPI *SAL_PROC)(
 109   IN UINT64 FunctionId,
 110   IN UINT64 Arg1,
 111   IN UINT64 Arg2,
 112   IN UINT64 Arg3,
 113   IN UINT64 Arg4,
 114   IN UINT64 Arg5,
 115   IN UINT64 Arg6,
 116   IN UINT64 Arg7
 117   );
 118
 119 //
 120 // SAL Procedure FunctionId definition
 121 //
 122
 123 ///
 124 /// Register software code locations with SAL.
 125 ///
 126 #define EFI_SAL_SET_VECTORS             0x01000000
 127 ///
 128 /// Return Machine State information obtained by SAL.
 129 ///
 130 #define EFI_SAL_GET_STATE_INFO          0x01000001
 131 ///
 132 /// Obtain size of Machine State information.
 133 ///
 134 #define EFI_SAL_GET_STATE_INFO_SIZE     0x01000002
 135 ///
 136 /// Clear Machine State information.
 137 ///
 138 #define EFI_SAL_CLEAR_STATE_INFO        0x01000003
 139 ///
 140 /// Cause the processor to go into a spin loop within SAL.
 141 ///
 142 #define EFI_SAL_MC_RENDEZ               0x01000004
 143 ///
 144 /// Register the machine check interface layer with SAL.
 145 ///
 146 #define EFI_SAL_MC_SET_PARAMS           0x01000005
 147 ///
 148 /// Register the physical addresses of locations needed by SAL.
 149 ///
 150 #define EFI_SAL_REGISTER_PHYSICAL_ADDR  0x01000006
 151 ///
 152 /// Flush the instruction or data caches.
 153 ///
 154 #define EFI_SAL_CACHE_FLUSH             0x01000008
 155 ///
 156 /// Initialize the instruction and data caches.
 157 ///
 158 #define EFI_SAL_CACHE_INIT              0x01000009
 159 ///
 160 /// Read from the PCI configuration space.
 161 ///
 162 #define EFI_SAL_PCI_CONFIG_READ         0x01000010
 163 ///
 164 /// Write to the PCI configuration space.
 165 ///
 166 #define EFI_SAL_PCI_CONFIG_WRITE        0x01000011
 167 ///
 168 /// Return the base frequency of the platform.
 169 ///
 170 #define EFI_SAL_FREQ_BASE               0x01000012
 171 ///
 172 /// Returns information on the physical processor mapping within the platform.
 173 ///
 174 #define EFI_SAL_PHYSICAL_ID_INFO        0x01000013
 175 ///
 176 /// Update the contents of firmware blocks.
 177 ///
 178 #define EFI_SAL_UPDATE_PAL              0x01000020
 179
 180 #define EFI_SAL_FUNCTION_ID_MASK        0x0000ffff
 181 #define EFI_SAL_MAX_SAL_FUNCTION_ID     0x00000021
 182
 183 //
 184 // SAL Procedure parameter definitions
 185 // Not much point in using typedefs or enums because all params
 186 // are UINT64 and the entry point is common
 187 //
 188
 189 //
 190 // Parameter of EFI_SAL_SET_VECTORS
 191 //
 192 // Vector type
 193 //
 194 #define EFI_SAL_SET_MCA_VECTOR          0x0
 195 #define EFI_SAL_SET_INIT_VECTOR         0x1
 196 #define EFI_SAL_SET_BOOT_RENDEZ_VECTOR  0x2
 197 ///
 198 /// The format of a length_cs_n argument.
 199 ///
 200 typedef struct {
 201   UINT64  Length : 32;
 202   UINT64  ChecksumValid : 1;
 203   UINT64  Reserved1 : 7;
 204   UINT64  ByteChecksum : 8;
 205   UINT64  Reserved2 : 16;
 206 } SAL_SET_VECTORS_CS_N;
 207
 208 //
 209 // Parameter of EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE, and EFI_SAL_CLEAR_STATE_INFO
 210 //
 211 // Type of information
 212 //
 213 #define EFI_SAL_MCA_STATE_INFO  0x0
 214 #define EFI_SAL_INIT_STATE_INFO 0x1
 215 #define EFI_SAL_CMC_STATE_INFO  0x2
 216 #define EFI_SAL_CP_STATE_INFO   0x3
 217
 218 //
 219 // Parameter of EFI_SAL_MC_SET_PARAMS
 220 //
 221 // Unsigned 64-bit integer value for the parameter type of the machine check interface
 222 //
 223 #define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
 224 #define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
 225 #define EFI_SAL_MC_SET_CPE_PARAM    0x3
 226 //
 227 // Unsigned 64-bit integer value indicating whether interrupt vector or
 228 // memory address is specified
 229 //
 230 #define EFI_SAL_MC_SET_INTR_PARAM   0x1
 231 #define EFI_SAL_MC_SET_MEM_PARAM    0x2
 232
 233 //
 234 // Parameter of EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
 235 //
 236 // The encoded value of the entity whose physical address is registered
 237 //
 238 #define EFI_SAL_REGISTER_PAL_ADDR 0x0
 239
 240 //
 241 // Parameter of EFI_SAL_CACHE_FLUSH
 242 //
 243 // Unsigned 64-bit integer denoting type of cache flush operation
 244 //
 245 #define EFI_SAL_FLUSH_I_CACHE       0x01
 246 #define EFI_SAL_FLUSH_D_CACHE       0x02
 247 #define EFI_SAL_FLUSH_BOTH_CACHE    0x03
 248 #define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
 249
 250 //
 251 // Parameter of EFI_SAL_PCI_CONFIG_READ and EFI_SAL_PCI_CONFIG_WRITE
 252 //
 253 // PCI config size
 254 //
 255 #define EFI_SAL_PCI_CONFIG_ONE_BYTE   0x1
 256 #define EFI_SAL_PCI_CONFIG_TWO_BYTES  0x2
 257 #define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
 258 //
 259 // The type of PCI configuration address
 260 //
 261 #define EFI_SAL_PCI_COMPATIBLE_ADDRESS         0x0
 262 #define EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS  0x1
 263 ///
 264 /// The format of PCI Compatible Address.
 265 ///
 266 typedef struct {
 267   UINT64  Register : 8;
 268   UINT64  Function : 3;
 269   UINT64  Device : 5;
 270   UINT64  Bus : 8;
 271   UINT64  Segment : 8;
 272   UINT64  Reserved : 32;
 273 } SAL_PCI_ADDRESS;
 274 ///
 275 /// The format of Extended Register Address.
 276 ///
 277 typedef struct {
 278   UINT64  Register : 8;
 279   UINT64  ExtendedRegister : 4;
 280   UINT64  Function : 3;
 281   UINT64  Device : 5;
 282   UINT64  Bus : 8;
 283   UINT64  Segment : 16;
 284   UINT64  Reserved : 20;
 285 } SAL_PCI_EXTENDED_REGISTER_ADDRESS;
 286
 287 //
 288 // Parameter of EFI_SAL_FREQ_BASE
 289 //
 290 // Unsigned 64-bit integer specifying the type of clock source
 291 //
 292 #define EFI_SAL_CPU_INPUT_FREQ_BASE     0x0
 293 #define EFI_SAL_PLATFORM_IT_FREQ_BASE   0x1
 294 #define EFI_SAL_PLATFORM_RTC_FREQ_BASE  0x2
 295
 296 //
 297 // Parameter and return value of EFI_SAL_UPDATE_PAL
 298 //
 299 // Return parameter provides additional information on the
 300 // failure when the status field contains a value of -3,
 301 // returned in r9.
 302 //
 303 #define EFI_SAL_UPDATE_BAD_PAL_VERSION  ((UINT64) -1)
 304 #define EFI_SAL_UPDATE_PAL_AUTH_FAIL    ((UINT64) -2)
 305 #define EFI_SAL_UPDATE_PAL_BAD_TYPE     ((UINT64) -3)
 306 #define EFI_SAL_UPDATE_PAL_READONLY     ((UINT64) -4)
 307 #define EFI_SAL_UPDATE_PAL_WRITE_FAIL   ((UINT64) -10)
 308 #define EFI_SAL_UPDATE_PAL_ERASE_FAIL   ((UINT64) -11)
 309 #define EFI_SAL_UPDATE_PAL_READ_FAIL    ((UINT64) -12)
 310 #define EFI_SAL_UPDATE_PAL_CANT_FIT     ((UINT64) -13)
 311 ///
 312 /// 64-byte header of update data block.
 313 ///
 314 typedef struct {
 315   UINT32  Size;
 316   UINT32  MmddyyyyDate;
 317   UINT16  Version;
 318   UINT8   Type;
 319   UINT8   Reserved[5];
 320   UINT64  FwVendorId;
 321   UINT8   Reserved2[40];
 322 } SAL_UPDATE_PAL_DATA_BLOCK;
 323 ///
 324 /// Data structure pointed by the parameter param_buf.
 325 /// It is a 16-byte aligned data structure in memory with a length of 32 bytes
 326 /// that describes the new firmware. This information is organized in the form
 327 /// of a linked list with each element describing one firmware component.
 328 ///
 329 typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {
 330   struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;
 331   struct SAL_UPDATE_PAL_DATA_BLOCK  *DataBlock;
 332   UINT8                             StoreChecksum;
 333   UINT8                             Reserved[15];
 334 } SAL_UPDATE_PAL_INFO_BLOCK;
 335
 336 ///
 337 /// SAL System Table Definitions.
 338 ///
 339 #pragma pack(1)
 340 typedef struct {
 341   ///
 342   /// The ASCII string representation of "SST_" that confirms the presence of the table.
 343   ///
 344   UINT32  Signature;
 345   ///
 346   /// The length of the entire table in bytes, starting from offset zero and including the
 347   /// header and all entries indicated by the EntryCount field.
 348   ///
 349   UINT32  Length;
 350   ///
 351   /// The revision number of the Itanium Processor Family System Abstraction Layer
 352   /// Specification supported by the SAL implementation, in binary coded decimal (BCD) format.
 353   ///
 354   UINT16  SalRevision;
 355   ///
 356   /// The number of entries in the variable portion of the table.
 357   ///
 358   UINT16  EntryCount;
 359   ///
 360   /// A modulo checksum of the entire table and the entries following this table.
 361   ///
 362   UINT8   CheckSum;
 363   ///
 364   /// Unused, must be zero.
 365   ///
 366   UINT8   Reserved[7];
 367   ///
 368   /// Version Number of the SAL_A firmware implementation in BCD format.
 369   ///
 370   UINT16  SalAVersion;
 371   ///
 372   /// Version Number of the SAL_B firmware implementation in BCD format.
 373   ///
 374   UINT16  SalBVersion;
 375   ///
 376   /// An ASCII identification string which uniquely identifies the manufacturer
 377   /// of the system hardware.
 378   ///
 379   UINT8   OemId[32];
 380   ///
 381   /// An ASCII identification string which uniquely identifies a family of
 382   /// compatible products from the manufacturer.
 383   ///
 384   UINT8   ProductId[32];
 385   ///
 386   /// Unused, must be zero.
 387   ///
 388   UINT8   Reserved2[8];
 389 } SAL_SYSTEM_TABLE_HEADER;
 390
 391 #define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
 392 #define EFI_SAL_REVISION            0x0320
 393 //
 394 // SAL System Types
 395 //
 396 #define EFI_SAL_ST_ENTRY_POINT        0
 397 #define EFI_SAL_ST_MEMORY_DESCRIPTOR  1
 398 #define EFI_SAL_ST_PLATFORM_FEATURES  2
 399 #define EFI_SAL_ST_TR_USAGE           3
 400 #define EFI_SAL_ST_PTC                4
 401 #define EFI_SAL_ST_AP_WAKEUP          5
 402
 403 //
 404 // SAL System Type Sizes
 405 //
 406 #define EFI_SAL_ST_ENTRY_POINT_SIZE        48
 407 #define EFI_SAL_ST_MEMORY_DESCRIPTOR_SIZE  32
 408 #define EFI_SAL_ST_PLATFORM_FEATURES_SIZE  16
 409 #define EFI_SAL_ST_TR_USAGE_SIZE           32
 410 #define EFI_SAL_ST_PTC_SIZE                16
 411 #define EFI_SAL_ST_AP_WAKEUP_SIZE          16
 412
 413 ///
 414 /// Format of Entrypoint Descriptor Entry.
 415 ///
 416 typedef struct {
 417   UINT8   Type;         ///< Type here should be 0.
 418   UINT8   Reserved[7];
 419   UINT64  PalProcEntry;
 420   UINT64  SalProcEntry;
 421   UINT64  SalGlobalDataPointer;
 422   UINT64  Reserved2[2];
 423 } SAL_ST_ENTRY_POINT_DESCRIPTOR;
 424
 425 ///
 426 /// Format of Platform Features Descriptor Entry.
 427 ///
 428 typedef struct {
 429   UINT8 Type;           ///< Type here should be 2.
 430   UINT8 PlatformFeatures;
 431   UINT8 Reserved[14];
 432 } SAL_ST_PLATFORM_FEATURES;
 433
 434 //
 435 // Value of Platform Feature List
 436 //
 437 #define SAL_PLAT_FEAT_BUS_LOCK      0x01
 438 #define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
 439 #define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
 440
 441 ///
 442 /// Format of Translation Register Descriptor Entry.
 443 ///
 444 typedef struct {
 445   UINT8   Type;         ///< Type here should be 3.
 446   UINT8   TRType;
 447   UINT8   TRNumber;
 448   UINT8   Reserved[5];
 449   UINT64  VirtualAddress;
 450   UINT64  EncodedPageSize;
 451   UINT64  Reserved1;
 452 } SAL_ST_TR_DECRIPTOR;
 453
 454 //
 455 // Type of Translation Register
 456 //
 457 #define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
 458 #define EFI_SAL_ST_TR_USAGE_DATA        01
 459
 460 ///
 461 /// Definition of Coherence Domain Information.
 462 ///
 463 typedef struct {
 464   UINT64  NumberOfProcessors;
 465   UINT64  LocalIDRegister;
 466 } SAL_COHERENCE_DOMAIN_INFO;
 467
 468 ///
 469 /// Format of Purge Translation Cache Coherence Domain Entry.
 470 ///
 471 typedef struct {
 472   UINT8                     Type;       ///< Type here should be 4.
 473   UINT8                     Reserved[3];
 474   UINT32                    NumberOfDomains;
 475   SAL_COHERENCE_DOMAIN_INFO *DomainInformation;
 476 } SAL_ST_CACHE_COHERENCE_DECRIPTOR;
 477
 478 ///
 479 /// Format of Application Processor Wake-Up Descriptor Entry.
 480 ///
 481 typedef struct {
 482   UINT8   Type;                   ///< Type here should be 5.
 483   UINT8   WakeUpType;
 484   UINT8   Reserved[6];
 485   UINT64  ExternalInterruptVector;
 486 } SAL_ST_AP_WAKEUP_DECRIPTOR;
 487
 488 ///
 489 /// Format of Firmware Interface Table (FIT) Entry.
 490 ///
 491 typedef struct {
 492   UINT64  Address;
 493   UINT8   Size[3];
 494   UINT8   Reserved;
 495   UINT16  Revision;
 496   UINT8   Type : 7;
 497   UINT8   CheckSumValid : 1;
 498   UINT8   CheckSum;
 499 } EFI_SAL_FIT_ENTRY;
 500 //
 501 // FIT Types
 502 //
 503 #define EFI_SAL_FIT_FIT_HEADER_TYPE                0x00
 504 #define EFI_SAL_FIT_PAL_B_TYPE                     0x01
 505 //
 506 // Type from 0x02 to 0x0D is reserved.
 507 //
 508 #define EFI_SAL_FIT_PROCESSOR_SPECIFIC_PAL_A_TYPE  0x0E
 509 #define EFI_SAL_FIT_PAL_A_TYPE                     0x0F
 510 //
 511 // OEM-defined type range is from 0x10 to 0x7E.
 512 // Here we defined the PEI_CORE type as 0x10
 513 //
 514 #define EFI_SAL_FIT_PEI_CORE_TYPE                  0x10
 515 #define EFI_SAL_FIT_UNUSED_TYPE                    0x7F
 516
 517 //
 518 // FIT Entry
 519 //
 520 #define EFI_SAL_FIT_ENTRY_PTR   (0x100000000 - 32)  // 4GB - 24
 521 #define EFI_SAL_FIT_PALA_ENTRY  (0x100000000 - 48)  // 4GB - 32
 522 #define EFI_SAL_FIT_PALB_TYPE   01
 523
 524 //
 525 // Following definitions are for Error Record Structure
 526 //
 527
 528 ///
 529 /// Format of TimeStamp field in Record Header.
 530 ///
 531 typedef struct {
 532   UINT8 Seconds;
 533   UINT8 Minutes;
 534   UINT8 Hours;
 535   UINT8 Reserved;
 536   UINT8 Day;
 537   UINT8 Month;
 538   UINT8 Year;
 539   UINT8 Century;
 540 } SAL_TIME_STAMP;
 541 ///
 542 /// Definition of Record Header.
 543 ///
 544 typedef struct {
 545   UINT64          RecordId;
 546   UINT16          Revision;
 547   UINT8           ErrorSeverity;
 548   UINT8           ValidationBits;
 549   UINT32          RecordLength;
 550   SAL_TIME_STAMP  TimeStamp;
 551   UINT8           OemPlatformId[16];
 552 } SAL_RECORD_HEADER;
 553 ///
 554 /// Definition of Section Header.
 555 ///
 556 typedef struct {
 557   GUID      Guid;
 558   UINT16    Revision;
 559   UINT8     ErrorRecoveryInfo;
 560   UINT8     Reserved;
 561   UINT32    SectionLength;
 562 } SAL_SEC_HEADER;
 563
 564 ///
 565 /// GUID of Processor Machine Check Errors.
 566 ///
 567 #define SAL_PROCESSOR_ERROR_RECORD_INFO \
 568   { \
 569     0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 570   }
 571 //
 572 // Bit masks for valid bits of MOD_ERROR_INFO
 573 //
 574 #define CHECK_INFO_VALID_BIT_MASK   0x1
 575 #define REQUESTOR_ID_VALID_BIT_MASK 0x2
 576 #define RESPONDER_ID_VALID_BIT_MASK 0x4
 577 #define TARGER_ID_VALID_BIT_MASK    0x8
 578 #define PRECISE_IP_VALID_BIT_MASK   0x10
 579 ///
 580 /// Definition of MOD_ERROR_INFO_STRUCT.
 581 ///
 582 typedef struct {
 583   UINT64  InfoValid : 1;
 584   UINT64  ReqValid : 1;
 585   UINT64  RespValid : 1;
 586   UINT64  TargetValid : 1;
 587   UINT64  IpValid : 1;
 588   UINT64  Reserved : 59;
 589   UINT64  Info;
 590   UINT64  Req;
 591   UINT64  Resp;
 592   UINT64  Target;
 593   UINT64  Ip;
 594 } MOD_ERROR_INFO;
 595 ///
 596 /// Definition of CPUID_INFO_STRUCT.
 597 ///
 598 typedef struct {
 599   UINT8 CpuidInfo[40];
 600   UINT8 Reserved;
 601 } CPUID_INFO;
 602
 603 typedef struct {
 604   UINT64  FrLow;
 605   UINT64  FrHigh;
 606 } FR_STRUCT;
 607 //
 608 // Bit masks for PSI_STATIC_STRUCT.ValidFieldBits
 609 //
 610 #define MIN_STATE_VALID_BIT_MASK  0x1
 611 #define BR_VALID_BIT_MASK         0x2
 612 #define CR_VALID_BIT_MASK         0x4
 613 #define AR_VALID_BIT_MASK         0x8
 614 #define RR_VALID_BIT_MASK         0x10
 615 #define FR_VALID_BIT_MASK         0x20
 616 ///
 617 /// Definition of PSI_STATIC_STRUCT.
 618 ///
 619 typedef struct {
 620   UINT64    ValidFieldBits;
 621   UINT8     MinStateInfo[1024];
 622   UINT64    Br[8];
 623   UINT64    Cr[128];
 624   UINT64    Ar[128];
 625   UINT64    Rr[8];
 626   FR_STRUCT Fr[128];
 627 } PSI_STATIC_STRUCT;
 628 //
 629 // Bit masks for SAL_PROCESSOR_ERROR_RECORD.ValidationBits
 630 //
 631 #define PROC_ERROR_MAP_VALID_BIT_MASK       0x1
 632 #define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
 633 #define PROC_CR_LID_VALID_BIT_MASK          0x4
 634 #define PROC_STATIC_STRUCT_VALID_BIT_MASK   0x8
 635 #define CPU_INFO_VALID_BIT_MASK             0x1000000
 636 ///
 637 /// Definition of Processor Machine Check Error Record.
 638 ///
 639 typedef struct {
 640   SAL_SEC_HEADER    SectionHeader;
 641   UINT64            ValidationBits;
 642   UINT64            ProcErrorMap;
 643   UINT64            ProcStateParameter;
 644   UINT64            ProcCrLid;
 645   MOD_ERROR_INFO    CacheError[15];
 646   MOD_ERROR_INFO    TlbError[15];
 647   MOD_ERROR_INFO    BusError[15];
 648   MOD_ERROR_INFO    RegFileCheck[15];
 649   MOD_ERROR_INFO    MsCheck[15];
 650   CPUID_INFO        CpuInfo;
 651   PSI_STATIC_STRUCT PsiValidData;
 652 } SAL_PROCESSOR_ERROR_RECORD;
 653
 654 ///
 655 /// GUID of Platform Memory Device Error Info.
 656 ///
 657 #define SAL_MEMORY_ERROR_RECORD_INFO \
 658   { \
 659     0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 660   }
 661 //
 662 // Bit masks for SAL_MEMORY_ERROR_RECORD.ValidationBits
 663 //
 664 #define MEMORY_ERROR_STATUS_VALID_BIT_MASK                0x1
 665 #define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK            0x2
 666 #define MEMORY_ADDR_BIT_MASK                              0x4
 667 #define MEMORY_NODE_VALID_BIT_MASK                        0x8
 668 #define MEMORY_CARD_VALID_BIT_MASK                        0x10
 669 #define MEMORY_MODULE_VALID_BIT_MASK                      0x20
 670 #define MEMORY_BANK_VALID_BIT_MASK                        0x40
 671 #define MEMORY_DEVICE_VALID_BIT_MASK                      0x80
 672 #define MEMORY_ROW_VALID_BIT_MASK                         0x100
 673 #define MEMORY_COLUMN_VALID_BIT_MASK                      0x200
 674 #define MEMORY_BIT_POSITION_VALID_BIT_MASK                0x400
 675 #define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK       0x800
 676 #define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK       0x1000
 677 #define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK             0x2000
 678 #define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK  0x4000
 679 #define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK             0x8000
 680 #define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK    0x10000
 681 ///
 682 /// Definition of Platform Memory Device Error Info Record.
 683 ///
 684 typedef struct {
 685   SAL_SEC_HEADER  SectionHeader;
 686   UINT64          ValidationBits;
 687   UINT64          MemErrorStatus;
 688   UINT64          MemPhysicalAddress;
 689   UINT64          MemPhysicalAddressMask;
 690   UINT16          MemNode;
 691   UINT16          MemCard;
 692   UINT16          MemModule;
 693   UINT16          MemBank;
 694   UINT16          MemDevice;
 695   UINT16          MemRow;
 696   UINT16          MemColumn;
 697   UINT16          MemBitPosition;
 698   UINT64          ModRequestorId;
 699   UINT64          ModResponderId;
 700   UINT64          ModTargetId;
 701   UINT64          BusSpecificData;
 702   UINT8           MemPlatformOemId[16];
 703 } SAL_MEMORY_ERROR_RECORD;
 704
 705 ///
 706 /// GUID of Platform PCI Bus Error Info.
 707 ///
 708 #define SAL_PCI_BUS_ERROR_RECORD_INFO \
 709   { \
 710     0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 711   }
 712 //
 713 // Bit masks for SAL_PCI_BUS_ERROR_RECORD.ValidationBits
 714 //
 715 #define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK     0x1
 716 #define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK       0x2
 717 #define PCI_BUS_ID_VALID_BIT_MASK               0x4
 718 #define PCI_BUS_ADDRESS_VALID_BIT_MASK          0x8
 719 #define PCI_BUS_DATA_VALID_BIT_MASK             0x10
 720 #define PCI_BUS_CMD_VALID_BIT_MASK              0x20
 721 #define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK     0x40
 722 #define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK     0x80
 723 #define PCI_BUS_TARGET_VALID_BIT_MASK           0x100
 724 #define PCI_BUS_OEM_ID_VALID_BIT_MASK           0x200
 725 #define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK  0x400
 726
 727 ///
 728 /// Designated PCI Bus identifier.
 729 ///
 730 typedef struct {
 731   UINT8 BusNumber;
 732   UINT8 SegmentNumber;
 733 } PCI_BUS_ID;
 734
 735 ///
 736 /// Definition of Platform PCI Bus Error Info Record.
 737 ///
 738 typedef struct {
 739   SAL_SEC_HEADER  SectionHeader;
 740   UINT64          ValidationBits;
 741   UINT64          PciBusErrorStatus;
 742   UINT16          PciBusErrorType;
 743   PCI_BUS_ID      PciBusId;
 744   UINT32          Reserved;
 745   UINT64          PciBusAddress;
 746   UINT64          PciBusData;
 747   UINT64          PciBusCommand;
 748   UINT64          PciBusRequestorId;
 749   UINT64          PciBusResponderId;
 750   UINT64          PciBusTargetId;
 751   UINT8           PciBusOemId[16];
 752 } SAL_PCI_BUS_ERROR_RECORD;
 753
 754 ///
 755 /// GUID of Platform PCI Component Error Info.
 756 ///
 757 #define SAL_PCI_COMP_ERROR_RECORD_INFO \
 758   { \
 759     0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 760   }
 761 //
 762 // Bit masks for SAL_PCI_COMPONENT_ERROR_RECORD.ValidationBits
 763 //
 764 #define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK    0x1
 765 #define PCI_COMP_INFO_VALID_BIT_MASK            0x2
 766 #define PCI_COMP_MEM_NUM_VALID_BIT_MASK         0x4
 767 #define PCI_COMP_IO_NUM_VALID_BIT_MASK          0x8
 768 #define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK   0x10
 769 #define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
 770 ///
 771 /// Format of PCI Component Information to identify the device.
 772 ///
 773 typedef struct {
 774   UINT16  VendorId;
 775   UINT16  DeviceId;
 776   UINT8   ClassCode[3];
 777   UINT8   FunctionNumber;
 778   UINT8   DeviceNumber;
 779   UINT8   BusNumber;
 780   UINT8   SegmentNumber;
 781   UINT8   Reserved[5];
 782 } PCI_COMP_INFO;
 783 ///
 784 /// Definition of Platform PCI Component Error Info.
 785 ///
 786 typedef struct {
 787   SAL_SEC_HEADER  SectionHeader;
 788   UINT64          ValidationBits;
 789   UINT64          PciComponentErrorStatus;
 790   PCI_COMP_INFO   PciComponentInfo;
 791   UINT32          PciComponentMemNum;
 792   UINT32          PciComponentIoNum;
 793   UINT8           PciBusOemId[16];
 794 } SAL_PCI_COMPONENT_ERROR_RECORD;
 795
 796 ///
 797 /// Platform SEL Device Error Info.
 798 ///
 799 #define SAL_SEL_DEVICE_ERROR_RECORD_INFO \
 800   { \
 801     0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 802   }
 803 //
 804 // Bit masks for SAL_SEL_DEVICE_ERROR_RECORD.ValidationBits
 805 //
 806 #define SEL_RECORD_ID_VALID_BIT_MASK      0x1;
 807 #define SEL_RECORD_TYPE_VALID_BIT_MASK    0x2;
 808 #define SEL_GENERATOR_ID_VALID_BIT_MASK   0x4;
 809 #define SEL_EVM_REV_VALID_BIT_MASK        0x8;
 810 #define SEL_SENSOR_TYPE_VALID_BIT_MASK    0x10;
 811 #define SEL_SENSOR_NUM_VALID_BIT_MASK     0x20;
 812 #define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
 813 #define SEL_EVENT_DATA1_VALID_BIT_MASK    0x80;
 814 #define SEL_EVENT_DATA2_VALID_BIT_MASK    0x100;
 815 #define SEL_EVENT_DATA3_VALID_BIT_MASK    0x200;
 816 ///
 817 /// Definition of Platform SEL Device Error Info Record.
 818 ///
 819 typedef struct {
 820   SAL_SEC_HEADER  SectionHeader;
 821   UINT64          ValidationBits;
 822   UINT16          SelRecordId;
 823   UINT8           SelRecordType;
 824   UINT32          TimeStamp;
 825   UINT16          GeneratorId;
 826   UINT8           EvmRevision;
 827   UINT8           SensorType;
 828   UINT8           SensorNum;
 829   UINT8           EventDirType;
 830   UINT8           Data1;
 831   UINT8           Data2;
 832   UINT8           Data3;
 833 } SAL_SEL_DEVICE_ERROR_RECORD;
 834
 835 ///
 836 /// GUID of Platform SMBIOS Device Error Info.
 837 ///
 838 #define SAL_SMBIOS_ERROR_RECORD_INFO \
 839   { \
 840     0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 841   }
 842 //
 843 // Bit masks for SAL_SMBIOS_DEVICE_ERROR_RECORD.ValidationBits
 844 //
 845 #define SMBIOS_EVENT_TYPE_VALID_BIT_MASK  0x1
 846 #define SMBIOS_LENGTH_VALID_BIT_MASK      0x2
 847 #define SMBIOS_TIME_STAMP_VALID_BIT_MASK  0x4
 848 #define SMBIOS_DATA_VALID_BIT_MASK        0x8
 849 ///
 850 /// Definition of Platform SMBIOS Device Error Info Record.
 851 ///
 852 typedef struct {
 853   SAL_SEC_HEADER  SectionHeader;
 854   UINT64          ValidationBits;
 855   UINT8           SmbiosEventType;
 856   UINT8           SmbiosLength;
 857   UINT8           SmbiosBcdTimeStamp[6];
 858 } SAL_SMBIOS_DEVICE_ERROR_RECORD;
 859
 860 ///
 861 /// GUID of Platform Specific Error Info.
 862 ///
 863 #define SAL_PLATFORM_ERROR_RECORD_INFO \
 864   { \
 865     0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 866   }
 867 //
 868 // Bit masks for SAL_PLATFORM_SPECIFIC_ERROR_RECORD.ValidationBits
 869 //
 870 #define PLATFORM_ERROR_STATUS_VALID_BIT_MASK    0x1
 871 #define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK    0x2
 872 #define PLATFORM_RESPONDER_ID_VALID_BIT_MASK    0x4
 873 #define PLATFORM_TARGET_VALID_BIT_MASK          0x8
 874 #define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK   0x10
 875 #define PLATFORM_OEM_ID_VALID_BIT_MASK          0x20
 876 #define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
 877 #define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
 878 ///
 879 /// Definition of Platform Specific Error Info Record.
 880 ///
 881 typedef struct {
 882   SAL_SEC_HEADER  SectionHeader;
 883   UINT64          ValidationBits;
 884   UINT64          PlatformErrorStatus;
 885   UINT64          PlatformRequestorId;
 886   UINT64          PlatformResponderId;
 887   UINT64          PlatformTargetId;
 888   UINT64          PlatformBusSpecificData;
 889   UINT8           OemComponentId[16];
 890 } SAL_PLATFORM_SPECIFIC_ERROR_RECORD;
 891
 892 ///
 893 /// Union of all the possible SAL Error Record Types.
 894 ///
 895 typedef union {
 896   SAL_RECORD_HEADER                   *RecordHeader;
 897   SAL_PROCESSOR_ERROR_RECORD          *SalProcessorRecord;
 898   SAL_PCI_BUS_ERROR_RECORD            *SalPciBusRecord;
 899   SAL_PCI_COMPONENT_ERROR_RECORD      *SalPciComponentRecord;
 900   SAL_SEL_DEVICE_ERROR_RECORD         *ImpiRecord;
 901   SAL_SMBIOS_DEVICE_ERROR_RECORD      *SmbiosRecord;
 902   SAL_PLATFORM_SPECIFIC_ERROR_RECORD  *PlatformRecord;
 903   SAL_MEMORY_ERROR_RECORD             *MemoryRecord;
 904   UINT8                               *Raw;
 905 } SAL_ERROR_RECORDS_POINTERS;
 906
 907 #pragma pack()
 908
 909 #endif