MdePkg/Include/IndustryStandard/Sal.h

   1 /** @file
   2   Main SAL API's defined in Intel Itanium Processor Family System Abstraction
   3   Layer Specification Revision 3.2 (December 2003)
   4
   5   Copyright (c) 2006 - 2008, Intel Corporation
   6   All rights reserved. This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __SAL_API_H__
  17 #define __SAL_API_H__
  18
  19 ///
  20 /// SAL return status type
  21 ///
  22 typedef UINTN EFI_SAL_STATUS;
  23
  24 ///
  25 /// Call completed without error.
  26 ///
  27 #define EFI_SAL_SUCCESS               ((EFI_SAL_STATUS) 0)
  28 ///
  29 /// Call completed without error but some information was lost due to overflow.
  30 ///
  31 #define EFI_SAL_OVERFLOW              ((EFI_SAL_STATUS) 1)
  32 ///
  33 /// Call completed without error; effect a warm boot of the system to complete the update.
  34 ///
  35 #define EFI_SAL_WARM_BOOT_NEEDED      ((EFI_SAL_STATUS) 2)
  36 ///
  37 /// More information is available for retrieval.
  38 ///
  39 #define EFI_SAL_MORE_RECORDS          ((EFI_SAL_STATUS) 3)
  40 ///
  41 /// Not implemented.
  42 ///
  43 #define EFI_SAL_NOT_IMPLEMENTED       ((EFI_SAL_STATUS) - 1)
  44 ///
  45 /// Invalid Argument.
  46 ///
  47 #define EFI_SAL_INVALID_ARGUMENT      ((EFI_SAL_STATUS) - 2)
  48 ///
  49 /// Call completed without error.
  50 ///
  51 #define EFI_SAL_ERROR                 ((EFI_SAL_STATUS) - 3)
  52 ///
  53 /// Virtual address not registered.
  54 ///
  55 #define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
  56 ///
  57 /// No information available.
  58 ///
  59 #define EFI_SAL_NO_INFORMATION        ((EFI_SAL_STATUS) - 5)
  60 ///
  61 /// Scratch buffer required.
  62 ///
  63 #define EFI_SAL_NOT_ENOUGH_SCRATCH    ((EFI_SAL_STATUS) - 9)
  64
  65 ///
  66 /// Return registers from SAL
  67 ///
  68 typedef struct {
  69   ///
  70   /// SAL return status value in r8
  71   ///
  72   EFI_SAL_STATUS  Status;
  73   ///
  74   /// SAL returned value in r9
  75   ///
  76   UINTN           r9;
  77   ///
  78   /// SAL returned value in r10
  79   ///
  80   UINTN           r10;
  81   ///
  82   /// SAL returned value in r11
  83   ///
  84   UINTN           r11;
  85 } SAL_RETURN_REGS;
  86
  87 /**
  88   Prototype of SAL procedures.
  89
  90   @param  FunctionId         Functional identifier.
  91                              The upper 32 bits are ignored and only the lower 32 bits
  92                              are used. The following functional identifiers are defined:
  93                              0x01XXXXXX - Architected SAL functional group.
  94                              0x02XXXXXX to 0x03XXXXXX - OEM SAL functional group. Each OEM is
  95                              allowed to use the entire range in the 0x02XXXXXX to 0x03XXXXXX range.
  96                              0x04XXXXXX to 0xFFFFFFFF - Reserved.
  97   @param  Arg1               The first parameter of the architected/OEM specific SAL functions.
  98   @param  Arg2               The second parameter of the architected/OEM specific SAL functions.
  99   @param  Arg3               The third parameter passed to the ESAL function based
 100   @param  Arg4               The fourth parameter passed to the ESAL function based
 101   @param  Arg5               The fifth parameter passed to the ESAL function based
 102   @param  Arg6               The sixth parameter passed to the ESAL function
 103   @param  Arg7               The seventh parameter passed to the ESAL function based
 104
 105   @return r8                 Return status: positive number indicates successful,
 106                              negative number indicates failure.
 107           r9                 Other return parameter in r9.
 108           r10                Other return parameter in r10.
 109           r11                Other return parameter in r11.
 110
 111 **/
 112 typedef
 113 SAL_RETURN_REGS
 114 (EFIAPI *SAL_PROC) (
 115   IN UINT64 FunctionId,
 116   IN UINT64 Arg1,
 117   IN UINT64 Arg2,
 118   IN UINT64 Arg3,
 119   IN UINT64 Arg4,
 120   IN UINT64 Arg5,
 121   IN UINT64 Arg6,
 122   IN UINT64 Arg7
 123   );
 124
 125 //
 126 // SAL Procedure FunctionId definition
 127 //
 128
 129 ///
 130 /// Register software code locations with SAL.
 131 ///
 132 #define EFI_SAL_SET_VECTORS             0x01000000
 133 ///
 134 /// Return Machine State information obtained by SAL.
 135 ///
 136 #define EFI_SAL_GET_STATE_INFO          0x01000001
 137 ///
 138 /// Obtain size of Machine State information.
 139 ///
 140 #define EFI_SAL_GET_STATE_INFO_SIZE     0x01000002
 141 ///
 142 /// Clear Machine State information.
 143 ///
 144 #define EFI_SAL_CLEAR_STATE_INFO        0x01000003
 145 ///
 146 /// Cause the processor to go into a spin loop within SAL.
 147 ///
 148 #define EFI_SAL_MC_RENDEZ               0x01000004
 149 ///
 150 /// Register the machine check interface layer with SAL.
 151 ///
 152 #define EFI_SAL_MC_SET_PARAMS           0x01000005
 153 ///
 154 /// Register the physical addresses of locations needed by SAL.
 155 ///
 156 #define EFI_SAL_REGISTER_PHYSICAL_ADDR  0x01000006
 157 ///
 158 /// Flush the instruction or data caches.
 159 ///
 160 #define EFI_SAL_CACHE_FLUSH             0x01000008
 161 ///
 162 /// Initialize the instruction and data caches.
 163 ///
 164 #define EFI_SAL_CACHE_INIT              0x01000009
 165 ///
 166 /// Read from the PCI configuration space.
 167 ///
 168 #define EFI_SAL_PCI_CONFIG_READ         0x01000010
 169 ///
 170 /// Write to the PCI configuration space.
 171 ///
 172 #define EFI_SAL_PCI_CONFIG_WRITE        0x01000011
 173 ///
 174 /// Return the base frequency of the platform.
 175 ///
 176 #define EFI_SAL_FREQ_BASE               0x01000012
 177 ///
 178 /// Returns information on the physical processor mapping within the platform.
 179 ///
 180 #define EFI_SAL_PHYSICAL_ID_INFO        0x01000013
 181 ///
 182 /// Update the contents of firmware blocks.
 183 ///
 184 #define EFI_SAL_UPDATE_PAL              0x01000020
 185
 186 #define EFI_SAL_FUNCTION_ID_MASK        0x0000ffff
 187 #define EFI_SAL_MAX_SAL_FUNCTION_ID     0x00000021
 188
 189 //
 190 // SAL Procedure parameter definitions
 191 // Not much point in using typedefs or enums because all params
 192 // are UINT64 and the entry point is common
 193 //
 194
 195 //
 196 // Parameter of EFI_SAL_SET_VECTORS
 197 //
 198 // Vector type
 199 //
 200 #define EFI_SAL_SET_MCA_VECTOR          0x0
 201 #define EFI_SAL_SET_INIT_VECTOR         0x1
 202 #define EFI_SAL_SET_BOOT_RENDEZ_VECTOR  0x2
 203 ///
 204 /// Format of length_cs_n argument.
 205 ///
 206 typedef struct {
 207   UINT64  Length : 32;
 208   UINT64  ChecksumValid : 1;
 209   UINT64  Reserved1 : 7;
 210   UINT64  ByteChecksum : 8;
 211   UINT64  Reserved2 : 16;
 212 } SAL_SET_VECTORS_CS_N;
 213
 214 //
 215 // Parameter of EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE, and EFI_SAL_CLEAR_STATE_INFO
 216 //
 217 // Type of information
 218 //
 219 #define EFI_SAL_MCA_STATE_INFO  0x0
 220 #define EFI_SAL_INIT_STATE_INFO 0x1
 221 #define EFI_SAL_CMC_STATE_INFO  0x2
 222 #define EFI_SAL_CP_STATE_INFO   0x3
 223
 224 //
 225 // Parameter of EFI_SAL_MC_SET_PARAMS
 226 //
 227 // Unsigned 64-bit integer value for the parameter type of the machine check interface
 228 //
 229 #define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
 230 #define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
 231 #define EFI_SAL_MC_SET_CPE_PARAM    0x3
 232 //
 233 // Unsigned 64-bit integer value indicating whether interrupt vector or
 234 // memory address is specified
 235 //
 236 #define EFI_SAL_MC_SET_INTR_PARAM   0x1
 237 #define EFI_SAL_MC_SET_MEM_PARAM    0x2
 238
 239 //
 240 // Parameter of EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
 241 //
 242 // The encoded value of the entity whose physical address is registered
 243 //
 244 #define EFI_SAL_REGISTER_PAL_ADDR 0x0
 245
 246 //
 247 // Parameter of EFI_SAL_CACHE_FLUSH
 248 //
 249 // Unsigned 64-bit integer denoting type of cache flush operation
 250 //
 251 #define EFI_SAL_FLUSH_I_CACHE       0x01
 252 #define EFI_SAL_FLUSH_D_CACHE       0x02
 253 #define EFI_SAL_FLUSH_BOTH_CACHE    0x03
 254 #define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
 255
 256 //
 257 // Parameter of EFI_SAL_PCI_CONFIG_READ and EFI_SAL_PCI_CONFIG_WRITE
 258 //
 259 // PCI config size
 260 //
 261 #define EFI_SAL_PCI_CONFIG_ONE_BYTE   0x1
 262 #define EFI_SAL_PCI_CONFIG_TWO_BYTES  0x2
 263 #define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
 264 //
 265 // The type of PCI configuration address
 266 //
 267 #define EFI_SAL_PCI_COMPATIBLE_ADDRESS         0x0
 268 #define EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS  0x1
 269 ///
 270 /// Format of PCI Compatible Address
 271 ///
 272 typedef struct {
 273   UINT64  Register : 8;
 274   UINT64  Function : 3;
 275   UINT64  Device : 5;
 276   UINT64  Bus : 8;
 277   UINT64  Segment : 8;
 278   UINT64  Reserved : 32;
 279 } SAL_PCI_ADDRESS;
 280 ///
 281 /// Format of Extended Register Address
 282 ///
 283 typedef struct {
 284   UINT64  Register : 8;
 285   UINT64  ExtendedRegister : 4;
 286   UINT64  Function : 3;
 287   UINT64  Device : 5;
 288   UINT64  Bus : 8;
 289   UINT64  Segment : 16;
 290   UINT64  Reserved : 20;
 291 } SAL_PCI_EXTENDED_REGISTER_ADDRESS;
 292
 293 //
 294 // Parameter of EFI_SAL_FREQ_BASE
 295 //
 296 // Unsigned 64-bit integer specifying the type of clock source
 297 //
 298 #define EFI_SAL_CPU_INPUT_FREQ_BASE     0x0
 299 #define EFI_SAL_PLATFORM_IT_FREQ_BASE   0x1
 300 #define EFI_SAL_PLATFORM_RTC_FREQ_BASE  0x2
 301
 302 //
 303 // Parameter and return value of EFI_SAL_UPDATE_PAL
 304 //
 305 // Return parameter provides additional information on the
 306 // failure when the status field contains a value of -3,
 307 // returned in r9.
 308 //
 309 #define EFI_SAL_UPDATE_BAD_PAL_VERSION  ((UINT64) -1)
 310 #define EFI_SAL_UPDATE_PAL_AUTH_FAIL    ((UINT64) -2)
 311 #define EFI_SAL_UPDATE_PAL_BAD_TYPE     ((UINT64) -3)
 312 #define EFI_SAL_UPDATE_PAL_READONLY     ((UINT64) -4)
 313 #define EFI_SAL_UPDATE_PAL_WRITE_FAIL   ((UINT64) -10)
 314 #define EFI_SAL_UPDATE_PAL_ERASE_FAIL   ((UINT64) -11)
 315 #define EFI_SAL_UPDATE_PAL_READ_FAIL    ((UINT64) -12)
 316 #define EFI_SAL_UPDATE_PAL_CANT_FIT     ((UINT64) -13)
 317 ///
 318 /// 64-byte header of update data block.
 319 ///
 320 typedef struct {
 321   UINT32  Size;
 322   UINT32  MmddyyyyDate;
 323   UINT16  Version;
 324   UINT8   Type;
 325   UINT8   Reserved[5];
 326   UINT64  FwVendorId;
 327 } SAL_UPDATE_PAL_DATA_BLOCK;
 328 ///
 329 /// Data structure pointed by parameter param_buf.
 330 /// It is a 16-byte aligned data structure in memory with a length of 32 bytes
 331 /// that describes the new firmware. This information is organized in the form
 332 /// of a linked list with each element describing one firmware component.
 333 ///
 334 typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {
 335   struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;
 336   struct SAL_UPDATE_PAL_DATA_BLOCK  *DataBlock;
 337   UINT8                             StoreChecksum;
 338   UINT8                             Reserved[15];
 339 } SAL_UPDATE_PAL_INFO_BLOCK;
 340
 341 ///
 342 /// SAL System Table Definitions
 343 ///
 344 #pragma pack(1)
 345 typedef struct {
 346   ///
 347   /// The ASCII string representation of "SST_" which confirms the presence of the table.
 348   ///
 349   UINT32  Signature;
 350   ///
 351   /// The length of the entire table in bytes, starting from offset zero and including the
 352   /// header and all entries indicated by the EntryCount field.
 353   ///
 354   UINT32  Length;
 355   ///
 356   /// The revision number of the Itanium Processor Family System Abstraction Layer
 357   /// Specification supported by the SAL implementation in binary coded decimal (BCD) format.
 358   ///
 359   UINT16  SalRevision;
 360   ///
 361   /// The number of entries in the variable portion of the table.
 362   ///
 363   UINT16  EntryCount;
 364   ///
 365   /// A modulo checksum of the entire table and the entries following this table.
 366   ///
 367   UINT8   CheckSum;
 368   ///
 369   /// Unused, must be zero.
 370   ///
 371   UINT8   Reserved[7];
 372   ///
 373   /// Version Number of the SAL_A firmware implementation in BCD format.
 374   ///
 375   UINT16  SalAVersion;
 376   ///
 377   /// Version Number of the SAL_B firmware implementation in BCD format.
 378   ///
 379   UINT16  SalBVersion;
 380   ///
 381   /// An ASCII identification string which uniquely identifies the manufacturer
 382   /// of the system hardware.
 383   ///
 384   UINT8   OemId[32];
 385   ///
 386   /// An ASCII identification string which uniquely identifies a family of
 387   /// compatible products from the manufacturer.
 388   ///
 389   UINT8   ProductId[32];
 390   ///
 391   /// Unused, must be zero.
 392   ///
 393   UINT8   Reserved2[8];
 394 } SAL_SYSTEM_TABLE_HEADER;
 395
 396 #define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
 397 #define EFI_SAL_REVISION            0x0320
 398 //
 399 // SAL System Types
 400 //
 401 #define EFI_SAL_ST_ENTRY_POINT        0
 402 #define EFI_SAL_ST_MEMORY_DESCRIPTOR  1
 403 #define EFI_SAL_ST_PLATFORM_FEATURES  2
 404 #define EFI_SAL_ST_TR_USAGE           3
 405 #define EFI_SAL_ST_PTC                4
 406 #define EFI_SAL_ST_AP_WAKEUP          5
 407
 408 //
 409 // SAL System Type Sizes
 410 //
 411 #define EFI_SAL_ST_ENTRY_POINT_SIZE        48
 412 #define EFI_SAL_ST_MEMORY_DESCRIPTOR_SIZE  32
 413 #define EFI_SAL_ST_PLATFORM_FEATURES_SIZE  16
 414 #define EFI_SAL_ST_TR_USAGE_SIZE           32
 415 #define EFI_SAL_ST_PTC_SIZE                16
 416 #define EFI_SAL_ST_AP_WAKEUP_SIZE          16
 417
 418 ///
 419 /// Format of Entrypoint Descriptor Entry
 420 ///
 421 typedef struct {
 422   UINT8   Type;         ///< Type here should be 0
 423   UINT8   Reserved[7];
 424   UINT64  PalProcEntry;
 425   UINT64  SalProcEntry;
 426   UINT64  SalGlobalDataPointer;
 427   UINT64  Reserved2[2];
 428 } SAL_ST_ENTRY_POINT_DESCRIPTOR;
 429
 430 ///
 431 /// Format of Platform Features Descriptor Entry
 432 ///
 433 typedef struct {
 434   UINT8 Type;           ///< Type here should be 2
 435   UINT8 PlatformFeatures;
 436   UINT8 Reserved[14];
 437 } SAL_ST_PLATFORM_FEATURES;
 438
 439 //
 440 // Value of Platform Feature List
 441 //
 442 #define SAL_PLAT_FEAT_BUS_LOCK      0x01
 443 #define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
 444 #define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
 445
 446 ///
 447 /// Format of Translation Register Descriptor Entry
 448 ///
 449 typedef struct {
 450   UINT8   Type;         ///< Type here should be 3
 451   UINT8   TRType;
 452   UINT8   TRNumber;
 453   UINT8   Reserved[5];
 454   UINT64  VirtualAddress;
 455   UINT64  EncodedPageSize;
 456   UINT64  Reserved1;
 457 } SAL_ST_TR_DECRIPTOR;
 458
 459 //
 460 // Type of Translation Register
 461 //
 462 #define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
 463 #define EFI_SAL_ST_TR_USAGE_DATA        01
 464
 465 ///
 466 /// Definition of Coherence Domain Information
 467 ///
 468 typedef struct {
 469   UINT64  NumberOfProcessors;
 470   UINT64  LocalIDRegister;
 471 } SAL_COHERENCE_DOMAIN_INFO;
 472
 473 ///
 474 /// Format of Purge Translation Cache Coherence Domain Entry
 475 ///
 476 typedef struct {
 477   UINT8                     Type;       ///< Type here should be 4
 478   UINT8                     Reserved[3];
 479   UINT32                    NumberOfDomains;
 480   SAL_COHERENCE_DOMAIN_INFO *DomainInformation;
 481 } SAL_ST_CACHE_COHERENCE_DECRIPTOR;
 482
 483 ///
 484 /// Format of Application Processor Wake-Up Descriptor Entry
 485 ///
 486 typedef struct {
 487   UINT8   Type;                   ///< Type here should be 5
 488   UINT8   WakeUpType;
 489   UINT8   Reserved[6];
 490   UINT64  ExternalInterruptVector;
 491 } SAL_ST_AP_WAKEUP_DECRIPTOR;
 492
 493 ///
 494 /// Format of Firmware Interface Table (FIT) Entry
 495 ///
 496 typedef struct {
 497   UINT64  Address;
 498   UINT8   Size[3];
 499   UINT8   Reserved;
 500   UINT16  Revision;
 501   UINT8   Type : 7;
 502   UINT8   CheckSumValid : 1;
 503   UINT8   CheckSum;
 504 } EFI_SAL_FIT_ENTRY;
 505 //
 506 // FIT Types
 507 //
 508 #define EFI_SAL_FIT_FIT_HEADER_TYPE                0x00
 509 #define EFI_SAL_FIT_PAL_B_TYPE                     0x01
 510 //
 511 // Type from 0x02 to 0x0D is reserved.
 512 //
 513 #define EFI_SAL_FIT_PROCESSOR_SPECIFIC_PAL_A_TYPE  0x0E
 514 #define EFI_SAL_FIT_PAL_A_TYPE                     0x0F
 515 //
 516 // OEM-defined type range is from 0x10 to 0x7E.
 517 // Here we defined the PEI_CORE type as 0x10
 518 //
 519 #define EFI_SAL_FIT_PEI_CORE_TYPE                  0x10
 520 #define EFI_SAL_FIT_UNUSED_TYPE                    0x7F
 521
 522 //
 523 // FIT Entry
 524 //
 525 #define EFI_SAL_FIT_ENTRY_PTR   (0x100000000 - 32)  // 4GB - 24
 526 #define EFI_SAL_FIT_PALA_ENTRY  (0x100000000 - 48)  // 4GB - 32
 527 #define EFI_SAL_FIT_PALB_TYPE   01
 528
 529 //
 530 // Following definitions are for Error Record Structure
 531 //
 532
 533 ///
 534 /// Format of TimeStamp field in Record Header
 535 ///
 536 typedef struct {
 537   UINT8 Seconds;
 538   UINT8 Minutes;
 539   UINT8 Hours;
 540   UINT8 Reserved;
 541   UINT8 Day;
 542   UINT8 Month;
 543   UINT8 Year;
 544   UINT8 Century;
 545 } SAL_TIME_STAMP;
 546 ///
 547 /// Definition of Record Header
 548 ///
 549 typedef struct {
 550   UINT64          RecordId;
 551   UINT16          Revision;
 552   UINT8           ErrorSeverity;
 553   UINT8           ValidationBits;
 554   UINT32          RecordLength;
 555   SAL_TIME_STAMP  TimeStamp;
 556   UINT8           OemPlatformId[16];
 557 } SAL_RECORD_HEADER;
 558 ///
 559 /// Definition of Section Header
 560 ///
 561 typedef struct {
 562   GUID      Guid;
 563   UINT16    Revision;
 564   UINT8     ErrorRecoveryInfo;
 565   UINT8     Reserved;
 566   UINT32    SectionLength;
 567 } SAL_SEC_HEADER;
 568
 569 ///
 570 /// GUID of Processor Machine Check Errors
 571 ///
 572 #define SAL_PROCESSOR_ERROR_RECORD_INFO \
 573   { \
 574     0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 575   }
 576 //
 577 // Bit masks for valid bits of MOD_ERROR_INFO
 578 //
 579 #define CHECK_INFO_VALID_BIT_MASK   0x1
 580 #define REQUESTOR_ID_VALID_BIT_MASK 0x2
 581 #define RESPONDER_ID_VALID_BIT_MASK 0x4
 582 #define TARGER_ID_VALID_BIT_MASK    0x8
 583 #define PRECISE_IP_VALID_BIT_MASK   0x10
 584 ///
 585 /// Definition of MOD_ERROR_INFO_STRUCT
 586 ///
 587 typedef struct {
 588   UINT64  InfoValid : 1;
 589   UINT64  ReqValid : 1;
 590   UINT64  RespValid : 1;
 591   UINT64  TargetValid : 1;
 592   UINT64  IpValid : 1;
 593   UINT64  Reserved : 59;
 594   UINT64  Info;
 595   UINT64  Req;
 596   UINT64  Resp;
 597   UINT64  Target;
 598   UINT64  Ip;
 599 } MOD_ERROR_INFO;
 600 ///
 601 /// Definition of CPUID_INFO_STRUCT
 602 ///
 603 typedef struct {
 604   UINT8 CpuidInfo[40];
 605   UINT8 Reserved;
 606 } CPUID_INFO;
 607
 608 typedef struct {
 609   UINT64  FrLow;
 610   UINT64  FrHigh;
 611 } FR_STRUCT;
 612 //
 613 // Bit masks for PSI_STATIC_STRUCT.ValidFieldBits
 614 //
 615 #define MIN_STATE_VALID_BIT_MASK  0x1
 616 #define BR_VALID_BIT_MASK         0x2
 617 #define CR_VALID_BIT_MASK         0x4
 618 #define AR_VALID_BIT_MASK         0x8
 619 #define RR_VALID_BIT_MASK         0x10
 620 #define FR_VALID_BIT_MASK         0x20
 621 ///
 622 /// Definition of PSI_STATIC_STRUCT
 623 ///
 624 typedef struct {
 625   UINT64    ValidFieldBits;
 626   UINT8     MinStateInfo[1024];
 627   UINT64    Br[8];
 628   UINT64    Cr[128];
 629   UINT64    Ar[128];
 630   UINT64    Rr[8];
 631   FR_STRUCT Fr[128];
 632 } PSI_STATIC_STRUCT;
 633 //
 634 // Bit masks for SAL_PROCESSOR_ERROR_RECORD.ValidationBits
 635 //
 636 #define PROC_ERROR_MAP_VALID_BIT_MASK       0x1
 637 #define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
 638 #define PROC_CR_LID_VALID_BIT_MASK          0x4
 639 #define PROC_STATIC_STRUCT_VALID_BIT_MASK   0x8
 640 #define CPU_INFO_VALID_BIT_MASK             0x1000000
 641 ///
 642 /// Definition of Processor Machine Check Error Record
 643 ///
 644 typedef struct {
 645   SAL_SEC_HEADER    SectionHeader;
 646   UINT64            ValidationBits;
 647   UINT64            ProcErrorMap;
 648   UINT64            ProcStateParameter;
 649   UINT64            ProcCrLid;
 650   MOD_ERROR_INFO    CacheError[15];
 651   MOD_ERROR_INFO    TlbError[15];
 652   MOD_ERROR_INFO    BusError[15];
 653   MOD_ERROR_INFO    RegFileCheck[15];
 654   MOD_ERROR_INFO    MsCheck[15];
 655   CPUID_INFO        CpuInfo;
 656   PSI_STATIC_STRUCT PsiValidData;
 657 } SAL_PROCESSOR_ERROR_RECORD;
 658
 659 ///
 660 /// GUID of Platform Memory Device Error Info
 661 ///
 662 #define SAL_MEMORY_ERROR_RECORD_INFO \
 663   { \
 664     0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 665   }
 666 //
 667 // Bit masks for SAL_MEMORY_ERROR_RECORD.ValidationBits
 668 //
 669 #define MEMORY_ERROR_STATUS_VALID_BIT_MASK                0x1
 670 #define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK            0x2
 671 #define MEMORY_ADDR_BIT_MASK                              0x4
 672 #define MEMORY_NODE_VALID_BIT_MASK                        0x8
 673 #define MEMORY_CARD_VALID_BIT_MASK                        0x10
 674 #define MEMORY_MODULE_VALID_BIT_MASK                      0x20
 675 #define MEMORY_BANK_VALID_BIT_MASK                        0x40
 676 #define MEMORY_DEVICE_VALID_BIT_MASK                      0x80
 677 #define MEMORY_ROW_VALID_BIT_MASK                         0x100
 678 #define MEMORY_COLUMN_VALID_BIT_MASK                      0x200
 679 #define MEMORY_BIT_POSITION_VALID_BIT_MASK                0x400
 680 #define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK       0x800
 681 #define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK       0x1000
 682 #define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK             0x2000
 683 #define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK  0x4000
 684 #define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK             0x8000
 685 #define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK    0x10000
 686 ///
 687 /// Definition of Platform Memory Device Error Info Record
 688 ///
 689 typedef struct {
 690   SAL_SEC_HEADER  SectionHeader;
 691   UINT64          ValidationBits;
 692   UINT64          MemErrorStatus;
 693   UINT64          MemPhysicalAddress;
 694   UINT64          MemPhysicalAddressMask;
 695   UINT16          MemNode;
 696   UINT16          MemCard;
 697   UINT16          MemModule;
 698   UINT16          MemBank;
 699   UINT16          MemDevice;
 700   UINT16          MemRow;
 701   UINT16          MemColumn;
 702   UINT16          MemBitPosition;
 703   UINT64          ModRequestorId;
 704   UINT64          ModResponderId;
 705   UINT64          ModTargetId;
 706   UINT64          BusSpecificData;
 707   UINT8           MemPlatformOemId[16];
 708 } SAL_MEMORY_ERROR_RECORD;
 709
 710 ///
 711 /// GUID of Platform PCI Bus Error Info
 712 ///
 713 #define SAL_PCI_BUS_ERROR_RECORD_INFO \
 714   { \
 715     0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 716   }
 717 //
 718 // Bit masks for SAL_PCI_BUS_ERROR_RECORD.ValidationBits
 719 //
 720 #define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK     0x1
 721 #define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK       0x2
 722 #define PCI_BUS_ID_VALID_BIT_MASK               0x4
 723 #define PCI_BUS_ADDRESS_VALID_BIT_MASK          0x8
 724 #define PCI_BUS_DATA_VALID_BIT_MASK             0x10
 725 #define PCI_BUS_CMD_VALID_BIT_MASK              0x20
 726 #define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK     0x40
 727 #define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK     0x80
 728 #define PCI_BUS_TARGET_VALID_BIT_MASK           0x100
 729 #define PCI_BUS_OEM_ID_VALID_BIT_MASK           0x200
 730 #define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK  0x400
 731
 732 typedef struct {
 733   UINT8 BusNumber;
 734   UINT8 SegmentNumber;
 735 } PCI_BUS_ID;
 736 ///
 737 /// Definition of Platform PCI Bus Error Info Record
 738 ///
 739 typedef struct {
 740   SAL_SEC_HEADER  SectionHeader;
 741   UINT64          ValidationBits;
 742   UINT64          PciBusErrorStatus;
 743   UINT16          PciBusErrorType;
 744   PCI_BUS_ID      PciBusId;
 745   UINT32          Reserved;
 746   UINT64          PciBusAddress;
 747   UINT64          PciBusData;
 748   UINT64          PciBusCommand;
 749   UINT64          PciBusRequestorId;
 750   UINT64          PciBusResponderId;
 751   UINT64          PciBusTargetId;
 752   UINT8           PciBusOemId[16];
 753 } SAL_PCI_BUS_ERROR_RECORD;
 754
 755 ///
 756 /// GUID of Platform PCI Component Error Info
 757 ///
 758 #define SAL_PCI_COMP_ERROR_RECORD_INFO \
 759   { \
 760     0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 761   }
 762 //
 763 // Bit masks for SAL_PCI_COMPONENT_ERROR_RECORD.ValidationBits
 764 //
 765 #define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK    0x1
 766 #define PCI_COMP_INFO_VALID_BIT_MASK            0x2
 767 #define PCI_COMP_MEM_NUM_VALID_BIT_MASK         0x4
 768 #define PCI_COMP_IO_NUM_VALID_BIT_MASK          0x8
 769 #define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK   0x10
 770 #define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
 771 ///
 772 /// Format of PCI Component Information to identify the device
 773 ///
 774 typedef struct {
 775   UINT16  VendorId;
 776   UINT16  DeviceId;
 777   UINT8   ClassCode[3];
 778   UINT8   FunctionNumber;
 779   UINT8   DeviceNumber;
 780   UINT8   BusNumber;
 781   UINT8   SegmentNumber;
 782   UINT8   Reserved[5];
 783 } PCI_COMP_INFO;
 784 ///
 785 /// Definition of Platform PCI Component Error Info
 786 ///
 787 typedef struct {
 788   SAL_SEC_HEADER  SectionHeader;
 789   UINT64          ValidationBits;
 790   UINT64          PciComponentErrorStatus;
 791   PCI_COMP_INFO   PciComponentInfo;
 792   UINT32          PciComponentMemNum;
 793   UINT32          PciComponentIoNum;
 794   UINT8           PciBusOemId[16];
 795 } SAL_PCI_COMPONENT_ERROR_RECORD;
 796
 797 ///
 798 /// Platform SEL Device Error Info
 799 ///
 800 #define SAL_SEL_DEVICE_ERROR_RECORD_INFO \
 801   { \
 802     0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 803   }
 804 //
 805 // Bit masks for SAL_SEL_DEVICE_ERROR_RECORD.ValidationBits
 806 //
 807 #define SEL_RECORD_ID_VALID_BIT_MASK      0x1;
 808 #define SEL_RECORD_TYPE_VALID_BIT_MASK    0x2;
 809 #define SEL_GENERATOR_ID_VALID_BIT_MASK   0x4;
 810 #define SEL_EVM_REV_VALID_BIT_MASK        0x8;
 811 #define SEL_SENSOR_TYPE_VALID_BIT_MASK    0x10;
 812 #define SEL_SENSOR_NUM_VALID_BIT_MASK     0x20;
 813 #define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
 814 #define SEL_EVENT_DATA1_VALID_BIT_MASK    0x80;
 815 #define SEL_EVENT_DATA2_VALID_BIT_MASK    0x100;
 816 #define SEL_EVENT_DATA3_VALID_BIT_MASK    0x200;
 817 ///
 818 /// Definition of Platform SEL Device Error Info Record
 819 ///
 820 typedef struct {
 821   SAL_SEC_HEADER  SectionHeader;
 822   UINT64          ValidationBits;
 823   UINT16          SelRecordId;
 824   UINT8           SelRecordType;
 825   UINT32          TimeStamp;
 826   UINT16          GeneratorId;
 827   UINT8           EvmRevision;
 828   UINT8           SensorType;
 829   UINT8           SensorNum;
 830   UINT8           EventDirType;
 831   UINT8           Data1;
 832   UINT8           Data2;
 833   UINT8           Data3;
 834 } SAL_SEL_DEVICE_ERROR_RECORD;
 835
 836 ///
 837 /// GUID of Platform SMBIOS Device Error Info
 838 ///
 839 #define SAL_SMBIOS_ERROR_RECORD_INFO \
 840   { \
 841     0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 842   }
 843 //
 844 // Bit masks for SAL_SMBIOS_DEVICE_ERROR_RECORD.ValidationBits
 845 //
 846 #define SMBIOS_EVENT_TYPE_VALID_BIT_MASK  0x1
 847 #define SMBIOS_LENGTH_VALID_BIT_MASK      0x2
 848 #define SMBIOS_TIME_STAMP_VALID_BIT_MASK  0x4
 849 #define SMBIOS_DATA_VALID_BIT_MASK        0x8
 850 ///
 851 /// Definition of Platform SMBIOS Device Error Info Record
 852 ///
 853 typedef struct {
 854   SAL_SEC_HEADER  SectionHeader;
 855   UINT64          ValidationBits;
 856   UINT8           SmbiosEventType;
 857   UINT8           SmbiosLength;
 858   UINT8           SmbiosBcdTimeStamp[6];
 859 } SAL_SMBIOS_DEVICE_ERROR_RECORD;
 860
 861 ///
 862 /// GUID of Platform Specific Error Info
 863 ///
 864 #define SAL_PLATFORM_ERROR_RECORD_INFO \
 865   { \
 866     0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 867   }
 868 //
 869 // Bit masks for SAL_PLATFORM_SPECIFIC_ERROR_RECORD.ValidationBits
 870 //
 871 #define PLATFORM_ERROR_STATUS_VALID_BIT_MASK    0x1
 872 #define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK    0x2
 873 #define PLATFORM_RESPONDER_ID_VALID_BIT_MASK    0x4
 874 #define PLATFORM_TARGET_VALID_BIT_MASK          0x8
 875 #define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK   0x10
 876 #define PLATFORM_OEM_ID_VALID_BIT_MASK          0x20
 877 #define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
 878 #define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
 879 ///
 880 /// Definition of Platform Specific Error Info Record
 881 ///
 882 typedef struct {
 883   SAL_SEC_HEADER  SectionHeader;
 884   UINT64          ValidationBits;
 885   UINT64          PlatformErrorStatus;
 886   UINT64          PlatformRequestorId;
 887   UINT64          PlatformResponderId;
 888   UINT64          PlatformTargetId;
 889   UINT64          PlatformBusSpecificData;
 890   UINT8           OemComponentId[16];
 891 } SAL_PLATFORM_SPECIFIC_ERROR_RECORD;
 892
 893 ///
 894 /// Union of all the possible SAL Error Record Types
 895 ///
 896 typedef union {
 897   SAL_RECORD_HEADER                   *RecordHeader;
 898   SAL_PROCESSOR_ERROR_RECORD          *SalProcessorRecord;
 899   SAL_PCI_BUS_ERROR_RECORD            *SalPciBusRecord;
 900   SAL_PCI_COMPONENT_ERROR_RECORD      *SalPciComponentRecord;
 901   SAL_SEL_DEVICE_ERROR_RECORD         *ImpiRecord;
 902   SAL_SMBIOS_DEVICE_ERROR_RECORD      *SmbiosRecord;
 903   SAL_PLATFORM_SPECIFIC_ERROR_RECORD  *PlatformRecord;
 904   SAL_MEMORY_ERROR_RECORD             *MemoryRecord;
 905   UINT8                               *Raw;
 906 } SAL_ERROR_RECORDS_POINTERS;
 907
 908 #pragma pack()
 909
 910 #endif