MdePkg/Include/IndustryStandard/SdramSpdDdr3.h

   1 /** @file
   2   This file contains definitions for SPD DDR3.
   3
   4   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13   @par Revision Reference:
  14     - Serial Presence Detect (SPD) for DDR3 SDRAM Modules Document Release 6
  15       http://www.jedec.org/sites/default/files/docs/4_01_02_11R21A.pdf
  16 **/
  17
  18 #ifndef _SDRAM_SPD_DDR3_H_
  19 #define _SDRAM_SPD_DDR3_H_
  20
  21 #pragma pack (push, 1)
  22
  23 typedef union {
  24   struct {
  25     UINT8  BytesUsed                           :  4; ///< Bits 3:0
  26     UINT8  BytesTotal                          :  3; ///< Bits 6:4
  27     UINT8  CrcCoverage                         :  1; ///< Bits 7:7
  28   } Bits;
  29   UINT8  Data;
  30 } SPD3_DEVICE_DESCRIPTION_STRUCT;
  31
  32 typedef union {
  33   struct {
  34     UINT8  Minor                               :  4; ///< Bits 3:0
  35     UINT8  Major                               :  4; ///< Bits 7:4
  36   } Bits;
  37   UINT8  Data;
  38 } SPD3_REVISION_STRUCT;
  39
  40 typedef union {
  41   struct {
  42     UINT8  Type                                :  8; ///< Bits 7:0
  43   } Bits;
  44   UINT8  Data;
  45 } SPD3_DRAM_DEVICE_TYPE_STRUCT;
  46
  47 typedef union {
  48   struct {
  49     UINT8  ModuleType                          :  4; ///< Bits 3:0
  50     UINT8  Reserved                            :  4; ///< Bits 7:4
  51   } Bits;
  52   UINT8  Data;
  53 } SPD3_MODULE_TYPE_STRUCT;
  54
  55 typedef union {
  56   struct {
  57     UINT8  Density                             :  4; ///< Bits 3:0
  58     UINT8  BankAddress                         :  3; ///< Bits 6:4
  59     UINT8  Reserved                            :  1; ///< Bits 7:7
  60   } Bits;
  61   UINT8  Data;
  62 } SPD3_SDRAM_DENSITY_BANKS_STRUCT;
  63
  64 typedef union {
  65   struct {
  66     UINT8  ColumnAddress                       :  3; ///< Bits 2:0
  67     UINT8  RowAddress                          :  3; ///< Bits 5:3
  68     UINT8  Reserved                            :  2; ///< Bits 7:6
  69   } Bits;
  70   UINT8  Data;
  71 } SPD3_SDRAM_ADDRESSING_STRUCT;
  72
  73 typedef union {
  74   struct {
  75     UINT8  OperationAt1_50                     :  1; ///< Bits 0:0
  76     UINT8  OperationAt1_35                     :  1; ///< Bits 1:1
  77     UINT8  OperationAt1_25                     :  1; ///< Bits 2:2
  78     UINT8  Reserved                            :  5; ///< Bits 7:3
  79   } Bits;
  80   UINT8  Data;
  81 } SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT;
  82
  83 typedef union {
  84   struct {
  85     UINT8  SdramDeviceWidth                    :  3; ///< Bits 2:0
  86     UINT8  RankCount                           :  3; ///< Bits 5:3
  87     UINT8  Reserved                            :  2; ///< Bits 7:6
  88   } Bits;
  89   UINT8  Data;
  90 } SPD3_MODULE_ORGANIZATION_STRUCT;
  91
  92 typedef union {
  93   struct {
  94     UINT8  PrimaryBusWidth                     :  3; ///< Bits 2:0
  95     UINT8  BusWidthExtension                   :  2; ///< Bits 4:3
  96     UINT8  Reserved                            :  3; ///< Bits 7:5
  97   } Bits;
  98   UINT8  Data;
  99 } SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT;
 100
 101 typedef union {
 102   struct {
 103     UINT8  Divisor                             :  4; ///< Bits 3:0
 104     UINT8  Dividend                            :  4; ///< Bits 7:4
 105   } Bits;
 106   UINT8  Data;
 107 } SPD3_FINE_TIMEBASE_STRUCT;
 108
 109 typedef union {
 110   struct {
 111     UINT8  Dividend                            :  8; ///< Bits 7:0
 112   } Bits;
 113   UINT8  Data;
 114 } SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT;
 115
 116 typedef union {
 117   struct {
 118     UINT8  Divisor                             :  8; ///< Bits 7:0
 119   } Bits;
 120   UINT8  Data;
 121 } SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT;
 122
 123 typedef struct {
 124   SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend
 125   SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT  Divisor;  ///< Medium Timebase (MTB) Divisor
 126 } SPD3_MEDIUM_TIMEBASE;
 127
 128 typedef union {
 129   struct {
 130     UINT8  tCKmin                              :  8; ///< Bits 7:0
 131   } Bits;
 132   UINT8  Data;
 133 } SPD3_TCK_MIN_MTB_STRUCT;
 134
 135 typedef union {
 136   struct {
 137     UINT16 Cl4                                 :  1; ///< Bits 0:0
 138     UINT16 Cl5                                 :  1; ///< Bits 1:1
 139     UINT16 Cl6                                 :  1; ///< Bits 2:2
 140     UINT16 Cl7                                 :  1; ///< Bits 3:3
 141     UINT16 Cl8                                 :  1; ///< Bits 4:4
 142     UINT16 Cl9                                 :  1; ///< Bits 5:5
 143     UINT16 Cl10                                :  1; ///< Bits 6:6
 144     UINT16 Cl11                                :  1; ///< Bits 7:7
 145     UINT16 Cl12                                :  1; ///< Bits 8:8
 146     UINT16 Cl13                                :  1; ///< Bits 9:9
 147     UINT16 Cl14                                :  1; ///< Bits 10:10
 148     UINT16 Cl15                                :  1; ///< Bits 11:11
 149     UINT16 Cl16                                :  1; ///< Bits 12:12
 150     UINT16 Cl17                                :  1; ///< Bits 13:13
 151     UINT16 Cl18                                :  1; ///< Bits 14:14
 152     UINT16 Reserved                            :  1; ///< Bits 15:15
 153   } Bits;
 154   UINT16 Data;
 155   UINT8  Data8[2];
 156 } SPD3_CAS_LATENCIES_SUPPORTED_STRUCT;
 157
 158 typedef union {
 159   struct {
 160     UINT8  tAAmin                              :  8; ///< Bits 7:0
 161   } Bits;
 162   UINT8  Data;
 163 } SPD3_TAA_MIN_MTB_STRUCT;
 164
 165 typedef union {
 166   struct {
 167     UINT8  tWRmin                              :  8; ///< Bits 7:0
 168   } Bits;
 169   UINT8  Data;
 170 } SPD3_TWR_MIN_MTB_STRUCT;
 171
 172 typedef union {
 173   struct {
 174     UINT8  tRCDmin                             :  8; ///< Bits 7:0
 175   } Bits;
 176   UINT8  Data;
 177 } SPD3_TRCD_MIN_MTB_STRUCT;
 178
 179 typedef union {
 180   struct {
 181     UINT8  tRRDmin                             :  8; ///< Bits 7:0
 182   } Bits;
 183   UINT8  Data;
 184 } SPD3_TRRD_MIN_MTB_STRUCT;
 185
 186 typedef union {
 187   struct {
 188     UINT8  tRPmin                              :  8; ///< Bits 7:0
 189   } Bits;
 190   UINT8  Data;
 191 } SPD3_TRP_MIN_MTB_STRUCT;
 192
 193 typedef union {
 194   struct {
 195     UINT8  tRASminUpper                        :  4; ///< Bits 3:0
 196     UINT8  tRCminUpper                         :  4; ///< Bits 7:4
 197   } Bits;
 198   UINT8  Data;
 199 } SPD3_TRAS_TRC_MIN_MTB_STRUCT;
 200
 201 typedef union {
 202   struct {
 203     UINT8  tRASmin                             :  8; ///< Bits 7:0
 204   } Bits;
 205   UINT8  Data;
 206 } SPD3_TRAS_MIN_MTB_STRUCT;
 207
 208 typedef union {
 209   struct {
 210     UINT8  tRCmin                              :  8; ///< Bits 7:0
 211   } Bits;
 212   UINT8  Data;
 213 } SPD3_TRC_MIN_MTB_STRUCT;
 214
 215 typedef union {
 216   struct {
 217     UINT16 tRFCmin                             :  16; ///< Bits 15:0
 218   } Bits;
 219   UINT16 Data;
 220   UINT8  Data8[2];
 221 } SPD3_TRFC_MIN_MTB_STRUCT;
 222
 223 typedef union {
 224   struct {
 225     UINT8  tWTRmin                             :  8; ///< Bits 7:0
 226   } Bits;
 227   UINT8  Data;
 228 } SPD3_TWTR_MIN_MTB_STRUCT;
 229
 230 typedef union {
 231   struct {
 232     UINT8  tRTPmin                             :  8; ///< Bits 7:0
 233   } Bits;
 234   UINT8  Data;
 235 } SPD3_TRTP_MIN_MTB_STRUCT;
 236
 237 typedef union {
 238   struct {
 239     UINT8  tFAWminUpper                        :  4; ///< Bits 3:0
 240     UINT8  Reserved                            :  4; ///< Bits 7:4
 241   } Bits;
 242   UINT8  Data;
 243 } SPD3_TFAW_MIN_MTB_UPPER_STRUCT;
 244
 245 typedef union {
 246   struct {
 247     UINT8  tFAWmin                             :  8; ///< Bits 7:0
 248   } Bits;
 249   UINT8  Data;
 250 } SPD3_TFAW_MIN_MTB_STRUCT;
 251
 252 typedef union {
 253   struct {
 254     UINT8  Rzq6                                :  1; ///< Bits 0:0
 255     UINT8  Rzq7                                :  1; ///< Bits 1:1
 256     UINT8  Reserved                            :  5; ///< Bits 6:2
 257     UINT8  DllOff                              :  1; ///< Bits 7:7
 258   } Bits;
 259   UINT8  Data;
 260 } SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT;
 261
 262 typedef union {
 263   struct {
 264     UINT8  ExtendedTemperatureRange            :  1; ///< Bits 0:0
 265     UINT8  ExtendedTemperatureRefreshRate      :  1; ///< Bits 1:1
 266     UINT8  AutoSelfRefresh                     :  1; ///< Bits 2:2
 267     UINT8  OnDieThermalSensor                  :  1; ///< Bits 3:3
 268     UINT8  Reserved                            :  3; ///< Bits 6:4
 269     UINT8  PartialArraySelfRefresh             :  1; ///< Bits 7:7
 270   } Bits;
 271   UINT8  Data;
 272 } SPD3_SDRAM_THERMAL_REFRESH_STRUCT;
 273
 274 typedef union {
 275   struct {
 276     UINT8  ThermalSensorAccuracy               :  7; ///< Bits 6:0
 277     UINT8  ThermalSensorPresence               :  1; ///< Bits 7:7
 278   } Bits;
 279   UINT8  Data;
 280 } SPD3_MODULE_THERMAL_SENSOR_STRUCT;
 281
 282 typedef union {
 283   struct {
 284     UINT8  SignalLoading                       :  2; ///< Bits 1:0
 285     UINT8  Reserved                            :  2; ///< Bits 3:2
 286     UINT8  DieCount                            :  3; ///< Bits 6:4
 287     UINT8  SdramDeviceType                     :  1; ///< Bits 7:7
 288   } Bits;
 289   UINT8  Data;
 290 } SPD3_SDRAM_DEVICE_TYPE_STRUCT;
 291
 292 typedef union {
 293   struct {
 294     INT8  tCKminFine                           :  8; ///< Bits 7:0
 295   } Bits;
 296   INT8  Data;
 297 } SPD3_TCK_MIN_FTB_STRUCT;
 298
 299 typedef union {
 300   struct {
 301     INT8  tAAminFine                           :  8; ///< Bits 7:0
 302   } Bits;
 303   INT8  Data;
 304 } SPD3_TAA_MIN_FTB_STRUCT;
 305
 306 typedef union {
 307   struct {
 308     INT8  tRCDminFine                          :  8; ///< Bits 7:0
 309   } Bits;
 310   INT8  Data;
 311 } SPD3_TRCD_MIN_FTB_STRUCT;
 312
 313 typedef union {
 314   struct {
 315     INT8  tRPminFine                           :  8; ///< Bits 7:0
 316   } Bits;
 317   INT8  Data;
 318 } SPD3_TRP_MIN_FTB_STRUCT;
 319
 320 typedef union {
 321   struct {
 322     INT8  tRCminFine                           :  8; ///< Bits 7:0
 323   } Bits;
 324   INT8  Data;
 325 } SPD3_TRC_MIN_FTB_STRUCT;
 326
 327 typedef union {
 328   struct {
 329     UINT8  MaximumActivateCount                :  4; ///< Bits 3:0
 330     UINT8  MaximumActivateWindow               :  2; ///< Bits 5:4
 331     UINT8  VendorSpecific                      :  2; ///< Bits 7:6
 332   } Bits;
 333   UINT8  Data;
 334 } SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT;
 335
 336 typedef union {
 337   struct {
 338     UINT8  Height                              :  5; ///< Bits 4:0
 339     UINT8  RawCardExtension                    :  3; ///< Bits 7:5
 340   } Bits;
 341   UINT8  Data;
 342 } SPD3_UNBUF_MODULE_NOMINAL_HEIGHT;
 343
 344 typedef union {
 345   struct {
 346     UINT8  FrontThickness                      :  4; ///< Bits 3:0
 347     UINT8  BackThickness                       :  4; ///< Bits 7:4
 348   } Bits;
 349   UINT8  Data;
 350 } SPD3_UNBUF_MODULE_NOMINAL_THICKNESS;
 351
 352 typedef union {
 353   struct {
 354     UINT8  Card                                :  5; ///< Bits 4:0
 355     UINT8  Revision                            :  2; ///< Bits 6:5
 356     UINT8  Extension                           :  1; ///< Bits 7:7
 357   } Bits;
 358   UINT8  Data;
 359 } SPD3_UNBUF_REFERENCE_RAW_CARD;
 360
 361 typedef union {
 362   struct {
 363     UINT8  MappingRank1                        :  1; ///< Bits 0:0
 364     UINT8  Reserved                            :  7; ///< Bits 7:1
 365   } Bits;
 366   UINT8  Data;
 367 } SPD3_UNBUF_ADDRESS_MAPPING;
 368
 369 typedef union {
 370   struct {
 371     UINT8  Height                              :  5; ///< Bits 4:0
 372     UINT8  Reserved                            :  3; ///< Bits 7:5
 373   } Bits;
 374   UINT8  Data;
 375 } SPD3_RDIMM_MODULE_NOMINAL_HEIGHT;
 376
 377 typedef union {
 378   struct {
 379     UINT8  FrontThickness                      :  4; ///< Bits 3:0
 380     UINT8  BackThickness                       :  4; ///< Bits 7:4
 381   } Bits;
 382   UINT8  Data;
 383 } SPD3_RDIMM_MODULE_NOMINAL_THICKNESS;
 384
 385 typedef union {
 386   struct {
 387     UINT8  Card                                :  5; ///< Bits 4:0
 388     UINT8  Revision                            :  2; ///< Bits 6:5
 389     UINT8  Extension                           :  1; ///< Bits 7:7
 390   } Bits;
 391   UINT8  Data;
 392 } SPD3_RDIMM_REFERENCE_RAW_CARD;
 393
 394 typedef union {
 395   struct {
 396     UINT8  RegisterCount                       :  2; ///< Bits 1:0
 397     UINT8  DramRowCount                        :  2; ///< Bits 3:2
 398     UINT8  RegisterType                        :  4; ///< Bits 7:4
 399   } Bits;
 400   UINT8  Data;
 401 } SPD3_RDIMM_MODULE_ATTRIBUTES;
 402
 403 typedef union {
 404   struct {
 405     UINT8  HeatSpreaderThermalCharacteristics  :  7; ///< Bits 6:0
 406     UINT8  HeatSpreaderSolution                :  1; ///< Bits 7:7
 407   } Bits;
 408   UINT8  Data;
 409 } SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION;
 410
 411 typedef union {
 412   struct {
 413     UINT16 ContinuationCount                   :  7; ///< Bits 6:0
 414     UINT16 ContinuationParity                  :  1; ///< Bits 7:7
 415     UINT16 LastNonZeroByte                     :  8; ///< Bits 15:8
 416   } Bits;
 417   UINT16 Data;
 418   UINT8  Data8[2];
 419 } SPD3_MANUFACTURER_ID_CODE;
 420
 421 typedef union {
 422   struct {
 423     UINT8  RegisterRevisionNumber;             ///< Bits 7:0
 424   } Bits;
 425   UINT8  Data;
 426 } SPD3_RDIMM_REGISTER_REVISION_NUMBER;
 427
 428 typedef union {
 429   struct {
 430     UINT8 Bit0                                :  1; ///< Bits 0:0
 431     UINT8 Bit1                                :  1; ///< Bits 1:1
 432     UINT8 Bit2                                :  1; ///< Bits 2:2
 433     UINT8 Reserved                            :  5; ///< Bits 7:3
 434   } Bits;
 435   UINT8  Data;
 436 } SPD3_RDIMM_REGISTER_TYPE;
 437
 438 typedef union {
 439   struct {
 440     UINT8 Reserved                            :  4; ///< Bits 0:3
 441     UINT8 CommandAddressAOutputs              :  2; ///< Bits 5:4
 442     UINT8 CommandAddressBOutputs              :  2; ///< Bits 7:6
 443   } Bits;
 444   UINT8  Data;
 445 } SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS;
 446
 447 typedef union {
 448   struct {
 449     UINT8 ControlSignalsAOutputs              :  2; ///< Bits 0:1
 450     UINT8 ControlSignalsBOutputs              :  2; ///< Bits 3:2
 451     UINT8 Y1Y3ClockOutputs                    :  2; ///< Bits 5:4
 452     UINT8 Y0Y2ClockOutputs                    :  2; ///< Bits 7:6
 453   } Bits;
 454   UINT8  Data;
 455 } SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK;
 456
 457 typedef union {
 458   struct {
 459     UINT8 Reserved0                           :  4; ///< Bits 0:3
 460     UINT8 Reserved1                           :  4; ///< Bits 7:4
 461   } Bits;
 462   UINT8  Data;
 463 } SPD3_RDIMM_REGISTER_CONTROL_RESERVED;
 464
 465 typedef union {
 466   struct {
 467     UINT8  Height                             :  5; ///< Bits 4:0
 468     UINT8  Reserved                           :  3; ///< Bits 7:5
 469   } Bits;
 470   UINT8  Data;
 471 } SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT;
 472
 473 typedef union {
 474   struct {
 475     UINT8  FrontThickness                     :  4; ///< Bits 3:0
 476     UINT8  BackThickness                      :  4; ///< Bits 7:4
 477   } Bits;
 478   UINT8  Data;
 479 } SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS;
 480
 481 typedef union {
 482   struct {
 483     UINT8  Card                               :  5; ///< Bits 4:0
 484     UINT8  Revision                           :  2; ///< Bits 6:5
 485     UINT8  Extension                          :  1; ///< Bits 7:7
 486   } Bits;
 487   UINT8  Data;
 488 } SPD3_LRDIMM_REFERENCE_RAW_CARD;
 489
 490 typedef union {
 491   struct {
 492     UINT8  RegisterCount                      :  2; ///< Bits 1:0
 493     UINT8  DramRowCount                       :  2; ///< Bits 3:2
 494     UINT8  RegisterType                       :  4; ///< Bits 7:4
 495   } Bits;
 496   UINT8  Data;
 497 } SPD3_LRDIMM_MODULE_ATTRIBUTES;
 498
 499 typedef union {
 500   struct {
 501     UINT8 AddressCommandPrelaunch             :  1; ///< Bits 0:0
 502     UINT8 Rank1Rank5Swap                      :  1; ///< Bits 1:1
 503     UINT8 Reserved0                           :  1; ///< Bits 2:2
 504     UINT8 Reserved1                           :  1; ///< Bits 3:3
 505     UINT8 AddressCommandOutputs               :  2; ///< Bits 5:4
 506     UINT8 QxCS_nOutputs                       :  2; ///< Bits 7:6
 507   } Bits;
 508   UINT8  Data;
 509 } SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH;
 510
 511 typedef union {
 512   struct {
 513     UINT8 QxOdtOutputs                        :  2; ///< Bits 1:0
 514     UINT8 QxCkeOutputs                        :  2; ///< Bits 3:2
 515     UINT8 Y1Y3ClockOutputs                    :  2; ///< Bits 5:4
 516     UINT8 Y0Y2ClockOutputs                    :  2; ///< Bits 7:6
 517   } Bits;
 518   UINT8  Data;
 519 } SPD3_LRDIMM_TIMING_DRIVE_STRENGTH;
 520
 521 typedef union {
 522   struct {
 523     UINT8 YExtendedDelay                      :  2; ///< Bits 1:0
 524     UINT8 QxCS_n                              :  2; ///< Bits 3:2
 525     UINT8 QxOdt                               :  2; ///< Bits 5:4
 526     UINT8 QxCke                               :  2; ///< Bits 7:6
 527   } Bits;
 528   UINT8  Data;
 529 } SPD3_LRDIMM_EXTENDED_DELAY;
 530
 531 typedef union {
 532   struct {
 533     UINT8 DelayY                              :  3; ///< Bits 2:0
 534     UINT8 Reserved                            :  1; ///< Bits 3:3
 535     UINT8 QxCS_n                              :  4; ///< Bits 7:4
 536   } Bits;
 537   UINT8  Data;
 538 } SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA;
 539
 540 typedef union {
 541   struct {
 542     UINT8 QxCS_n                              :  4; ///< Bits 3:0
 543     UINT8 QxOdt                               :  4; ///< Bits 7:4
 544   } Bits;
 545   UINT8  Data;
 546 } SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE;
 547
 548 typedef union {
 549   struct {
 550     UINT8 RC8MdqOdtStrength                   :  3; ///< Bits 2:0
 551     UINT8 RC8Reserved                         :  1; ///< Bits 3:3
 552     UINT8 RC9MdqOdtStrength                   :  3; ///< Bits 6:4
 553     UINT8 RC9Reserved                         :  1; ///< Bits 7:7
 554   } Bits;
 555   UINT8  Data;
 556 } SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH;
 557
 558 typedef union {
 559   struct {
 560     UINT8 RC10DA3ValueR0                      :  1; ///< Bits 0:0
 561     UINT8 RC10DA4ValueR0                      :  1; ///< Bits 1:1
 562     UINT8 RC10DA3ValueR1                      :  1; ///< Bits 2:2
 563     UINT8 RC10DA4ValueR1                      :  1; ///< Bits 3:3
 564     UINT8 RC11DA3ValueR0                      :  1; ///< Bits 4:4
 565     UINT8 RC11DA4ValueR0                      :  1; ///< Bits 5:5
 566     UINT8 RC11DA3ValueR1                      :  1; ///< Bits 6:6
 567     UINT8 RC11DA4ValueR1                      :  1; ///< Bits 7:7
 568   } Bits;
 569   UINT8  Data;
 570 } SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL;
 571
 572 typedef union {
 573   struct {
 574     UINT8 Driver_Impedance                    :  2; ///< Bits 1:0
 575     UINT8 Rtt_Nom                             :  3; ///< Bits 4:2
 576     UINT8 Reserved                            :  1; ///< Bits 5:5
 577     UINT8 Rtt_WR                              :  2; ///< Bits 7:6
 578   } Bits;
 579   UINT8  Data;
 580 } SPD3_LRDIMM_MR_1_2;
 581
 582 typedef union {
 583   struct {
 584     UINT8 MinimumDelayTime                    :  7; ///< Bits 0:6
 585     UINT8 Reserved                            :  1; ///< Bits 7:7
 586   } Bits;
 587   UINT8  Data;
 588 } SPD3_LRDIMM_MODULE_DELAY_TIME;
 589
 590 typedef struct {
 591   UINT8  Year;                                 ///< Year represented in BCD (00h = 2000)
 592   UINT8  Week;                                 ///< Year represented in BCD (47h = week 47)
 593 } SPD3_MANUFACTURING_DATE;
 594
 595 typedef union {
 596   UINT32 Data;
 597   UINT16 SerialNumber16[2];
 598   UINT8  SerialNumber8[4];
 599 } SPD3_MANUFACTURER_SERIAL_NUMBER;
 600
 601 typedef struct {
 602   UINT8 Location;                              ///< Module Manufacturing Location
 603 } SPD3_MANUFACTURING_LOCATION;
 604
 605 typedef struct {
 606   SPD3_MANUFACTURER_ID_CODE            IdCode;                   ///< Module Manufacturer ID Code
 607   SPD3_MANUFACTURING_LOCATION          Location;                 ///< Module Manufacturing Location
 608   SPD3_MANUFACTURING_DATE              Date;                     ///< Module Manufacturing Year, in BCD (range: 2000-2255)
 609   SPD3_MANUFACTURER_SERIAL_NUMBER      SerialNumber;             ///< Module Serial Number
 610 } SPD3_UNIQUE_MODULE_ID;
 611
 612 typedef union {
 613   UINT16 Crc[1];
 614   UINT8  Data8[2];
 615 } SPD3_CYCLIC_REDUNDANCY_CODE;
 616
 617 typedef struct {
 618   SPD3_DEVICE_DESCRIPTION_STRUCT       Description;              ///< 0   Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
 619   SPD3_REVISION_STRUCT                 Revision;                 ///< 1   SPD Revision
 620   SPD3_DRAM_DEVICE_TYPE_STRUCT         DramDeviceType;           ///< 2   DRAM Device Type
 621   SPD3_MODULE_TYPE_STRUCT              ModuleType;               ///< 3   Module Type
 622   SPD3_SDRAM_DENSITY_BANKS_STRUCT      SdramDensityAndBanks;     ///< 4   SDRAM Density and Banks
 623   SPD3_SDRAM_ADDRESSING_STRUCT         SdramAddressing;          ///< 5   SDRAM Addressing
 624   SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT   ModuleNominalVoltage;     ///< 6   Module Nominal Voltage, VDD
 625   SPD3_MODULE_ORGANIZATION_STRUCT      ModuleOrganization;       ///< 7   Module Organization
 626   SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT  ModuleMemoryBusWidth;     ///< 8   Module Memory Bus Width
 627   SPD3_FINE_TIMEBASE_STRUCT            FineTimebase;             ///< 9   Fine Timebase (FTB) Dividend / Divisor
 628   SPD3_MEDIUM_TIMEBASE                 MediumTimebase;           ///< 10-11 Medium Timebase (MTB) Dividend
 629   SPD3_TCK_MIN_MTB_STRUCT              tCKmin;                   ///< 12  SDRAM Minimum Cycle Time (tCKmin)
 630   UINT8                                Reserved0;                ///< 13  Reserved
 631   SPD3_CAS_LATENCIES_SUPPORTED_STRUCT  CasLatencies;             ///< 14-15 CAS Latencies Supported
 632   SPD3_TAA_MIN_MTB_STRUCT              tAAmin;                   ///< 16  Minimum CAS Latency Time (tAAmin)
 633   SPD3_TWR_MIN_MTB_STRUCT              tWRmin;                   ///< 17  Minimum Write Recovery Time (tWRmin)
 634   SPD3_TRCD_MIN_MTB_STRUCT             tRCDmin;                  ///< 18  Minimum RAS# to CAS# Delay Time (tRCDmin)
 635   SPD3_TRRD_MIN_MTB_STRUCT             tRRDmin;                  ///< 19  Minimum Row Active to Row Active Delay Time (tRRDmin)
 636   SPD3_TRP_MIN_MTB_STRUCT              tRPmin;                   ///< 20  Minimum Row Precharge Delay Time (tRPmin)
 637   SPD3_TRAS_TRC_MIN_MTB_STRUCT         tRASMintRCMinUpper;       ///< 21  Upper Nibbles for tRAS and tRC
 638   SPD3_TRAS_MIN_MTB_STRUCT             tRASmin;                  ///< 22  Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
 639   SPD3_TRC_MIN_MTB_STRUCT              tRCmin;                   ///< 23  Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
 640   SPD3_TRFC_MIN_MTB_STRUCT             tRFCmin;                  ///< 24-25  Minimum Refresh Recovery Delay Time (tRFCmin)
 641   SPD3_TWTR_MIN_MTB_STRUCT             tWTRmin;                  ///< 26  Minimum Internal Write to Read Command Delay Time (tWTRmin)
 642   SPD3_TRTP_MIN_MTB_STRUCT             tRTPmin;                  ///< 27  Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
 643   SPD3_TFAW_MIN_MTB_UPPER_STRUCT       tFAWMinUpper;             ///< 28  Upper Nibble for tFAW
 644   SPD3_TFAW_MIN_MTB_STRUCT             tFAWmin;                  ///< 29  Minimum Four Activate Window Delay Time (tFAWmin)
 645   SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT  SdramOptionalFeatures;    ///< 30  SDRAM Optional Features
 646   SPD3_SDRAM_THERMAL_REFRESH_STRUCT    ThermalAndRefreshOptions; ///< 31  SDRAM Thermal And Refresh Options
 647   SPD3_MODULE_THERMAL_SENSOR_STRUCT    ModuleThermalSensor;      ///< 32  Module Thermal Sensor
 648   SPD3_SDRAM_DEVICE_TYPE_STRUCT        SdramDeviceType;          ///< 33  SDRAM Device Type
 649   SPD3_TCK_MIN_FTB_STRUCT              tCKminFine;               ///< 34  Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
 650   SPD3_TAA_MIN_FTB_STRUCT              tAAminFine;               ///< 35  Fine Offset for Minimum CAS Latency Time (tAAmin)
 651   SPD3_TRCD_MIN_FTB_STRUCT             tRCDminFine;              ///< 36  Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
 652   SPD3_TRP_MIN_FTB_STRUCT              tRPminFine;               ///< 37  Minimum Row Precharge Delay Time (tRPmin)
 653   SPD3_TRC_MIN_FTB_STRUCT              tRCminFine;               ///< 38  Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
 654   UINT8                                Reserved1[40 - 39 + 1];   ///< 39 - 40 Reserved
 655   SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT     MacValue;                 ///< 41  SDRAM Maximum Active Count (MAC) Value
 656   UINT8                                Reserved2[59 - 42 + 1];   ///< 42 - 59 Reserved
 657 } SPD3_BASE_SECTION;
 658
 659 typedef struct {
 660   SPD3_UNBUF_MODULE_NOMINAL_HEIGHT     ModuleNominalHeight;      ///< 60  Module Nominal Height
 661   SPD3_UNBUF_MODULE_NOMINAL_THICKNESS  ModuleMaximumThickness;   ///< 61  Module Maximum Thickness
 662   SPD3_UNBUF_REFERENCE_RAW_CARD        ReferenceRawCardUsed;     ///< 62  Reference Raw Card Used
 663   SPD3_UNBUF_ADDRESS_MAPPING           AddressMappingEdgeConn;   ///< 63  Address Mapping from Edge Connector to DRAM
 664   UINT8                                Reserved[116 - 64 + 1];   ///< 64-116 Reserved
 665 } SPD3_MODULE_UNBUFFERED;
 666
 667 typedef struct {
 668   SPD3_RDIMM_MODULE_NOMINAL_HEIGHT     ModuleNominalHeight;      ///< 60  Module Nominal Height
 669   SPD3_RDIMM_MODULE_NOMINAL_THICKNESS  ModuleMaximumThickness;   ///< 61  Module Maximum Thickness
 670   SPD3_RDIMM_REFERENCE_RAW_CARD        ReferenceRawCardUsed;     ///< 62  Reference Raw Card Used
 671   SPD3_RDIMM_MODULE_ATTRIBUTES         DimmModuleAttributes;     ///< 63  DIMM Module Attributes
 672   SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION       ThermalHeatSpreaderSolution; ///< 64     RDIMM Thermal Heat Spreader Solution
 673   SPD3_MANUFACTURER_ID_CODE                       RegisterManufacturerIdCode;  ///< 65-66  Register Manufacturer ID Code
 674   SPD3_RDIMM_REGISTER_REVISION_NUMBER             RegisterRevisionNumber;      ///< 67     Register Revision Number
 675   SPD3_RDIMM_REGISTER_TYPE                        RegisterType; ///< 68  Register Type
 676   SPD3_RDIMM_REGISTER_CONTROL_RESERVED            Rc1Rc0;       ///< 69  RC1 (MS Nibble) / RC0 (LS Nibble) - Reserved
 677   SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS     Rc3Rc2;       ///< 70  RC3 (MS Nibble) / RC2 (LS Nibble) - Drive Strength, Command/Address
 678   SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK       Rc5Rc4;       ///< 71  RC5 (MS Nibble) / RC4 (LS Nibble) - Drive Strength, Control and Clock
 679   SPD3_RDIMM_REGISTER_CONTROL_RESERVED            Rc7Rc6;       ///< 72  RC7 (MS Nibble) / RC6 (LS Nibble) - Reserved for Register Vendor
 680   SPD3_RDIMM_REGISTER_CONTROL_RESERVED            Rc9Rc8;       ///< 73  RC9 (MS Nibble) / RC8 (LS Nibble) - Reserved
 681   SPD3_RDIMM_REGISTER_CONTROL_RESERVED            Rc11Rc10;     ///< 74  RC11 (MS Nibble) / RC10 (LS Nibble) - Reserved
 682   SPD3_RDIMM_REGISTER_CONTROL_RESERVED            Rc13Rc12;     ///< 75  RC12 (MS Nibble) / RC12 (LS Nibble) - Reserved
 683   SPD3_RDIMM_REGISTER_CONTROL_RESERVED            Rc15Rc14;     ///< 76  RC15 (MS Nibble) / RC14 (LS Nibble) - Reserved
 684   UINT8                               Reserved[116 - 77 + 1];   ///< 77-116 Reserved
 685 } SPD3_MODULE_REGISTERED;
 686
 687 typedef struct {
 688   SPD3_UNBUF_MODULE_NOMINAL_HEIGHT     ModuleNominalHeight;     ///< 60  Module Nominal Height
 689   SPD3_UNBUF_MODULE_NOMINAL_THICKNESS  ModuleMaximumThickness;  ///< 61  Module Maximum Thickness
 690   SPD3_UNBUF_REFERENCE_RAW_CARD        ReferenceRawCardUsed;    ///< 62  Reference Raw Card Used
 691   UINT8                                Reserved[116 - 63 + 1];  ///< 63-116 Reserved
 692 } SPD3_MODULE_CLOCKED;
 693
 694 typedef struct {
 695   SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT     ModuleNominalHeight;    ///< 60  Module Nominal Height
 696   SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS  ModuleMaximumThickness; ///< 61  Module Maximum Thickness
 697   SPD3_LRDIMM_REFERENCE_RAW_CARD        ReferenceRawCardUsed;   ///< 62  Reference Raw Card Used
 698   SPD3_LRDIMM_MODULE_ATTRIBUTES         DimmModuleAttributes;   ///< 63  Module Attributes
 699   UINT8                                         MemoryBufferRevisionNumber;       ///< 64    Memory Buffer Revision Number
 700   SPD3_MANUFACTURER_ID_CODE                     ManufacturerIdCode;               ///< 65-66 Memory Buffer Manufacturer ID Code
 701   SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH     TimingControlDriveStrengthCaCs;   ///< 67    F0RC3 / F0RC2 - Timing Control & Drive Strength, CA & CS
 702   SPD3_LRDIMM_TIMING_DRIVE_STRENGTH             DriveStrength;                    ///< 68    F0RC5 / F0RC4 - Drive Strength, ODT & CKE and Y
 703   SPD3_LRDIMM_EXTENDED_DELAY                    ExtendedDelay;                    ///< 69    F1RC11 / F1RC8 - Extended Delay for Y, CS and ODT & CKE
 704   SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA    AdditiveDelayForCsCa;             ///< 70    F1RC13 / F1RC12 - Additive Delay for CS and CA
 705   SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE    AdditiveDelayForOdtCke;           ///< 71    F1RC15 / F1RC14 - Additive Delay for ODT & CKE
 706   SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH    MdqTerminationDriveStrengthFor800_1066; ///< 72    F1RC15 / F1RC14 - Additive Delay for ODT & CKE
 707   SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_0_1QxOdtControlFor800_1066;  ///< 73    F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066
 708   SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_2_3QxOdtControlFor800_1066;  ///< 74    F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066
 709   SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_4_5QxOdtControlFor800_1066;  ///< 75    F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066
 710   SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_6_7QxOdtControlFor800_1066;  ///< 76    F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066
 711   SPD3_LRDIMM_MR_1_2                            MR_1_2RegistersFor800_1066;       ///< 77    MR1,2 Registers for 800 & 1066
 712   SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH    MdqTerminationDriveStrengthFor1333_1600; ///< 78    F1RC15 / F1RC14 - Additive Delay for ODT & CKE
 713   SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_0_1QxOdtControlFor1333_1600; ///< 79    F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066
 714   SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_2_3QxOdtControlFor1333_1600; ///< 80    F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066
 715   SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_4_5QxOdtControlFor1333_1600; ///< 81    F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066
 716   SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_6_7QxOdtControlFor1333_1600; ///< 82    F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066
 717   SPD3_LRDIMM_MR_1_2                            MR_1_2RegistersFor1333_1600;      ///< 83    MR1,2 Registers for 800 & 1066
 718   SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH    MdqTerminationDriveStrengthFor1866_2133; ///< 84    F1RC15 / F1RC14 - Additive Delay for ODT & CKE
 719   SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_0_1QxOdtControlFor1866_2133; ///< 85    F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066
 720   SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_2_3QxOdtControlFor1866_2133; ///< 86    F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066
 721   SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_4_5QxOdtControlFor1866_2133; ///< 87    F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066
 722   SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_6_7QxOdtControlFor1866_2133; ///< 88    F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066
 723   SPD3_LRDIMM_MR_1_2                            MR_1_2RegistersFor1866_2133;      ///< 89    MR1,2 Registers for 800 & 1066
 724   SPD3_LRDIMM_MODULE_DELAY_TIME                 MinimumModuleDelayTimeFor1_5V;    ///< 90    Minimum Module Delay Time for 1.5 V
 725   SPD3_LRDIMM_MODULE_DELAY_TIME                 MaximumModuleDelayTimeFor1_5V;    ///< 91    Maximum Module Delay Time for 1.5 V
 726   SPD3_LRDIMM_MODULE_DELAY_TIME                 MinimumModuleDelayTimeFor1_35V;   ///< 92    Minimum Module Delay Time for 1.35 V
 727   SPD3_LRDIMM_MODULE_DELAY_TIME                 MaximumModuleDelayTimeFor1_35V;   ///< 93    Maximum Module Delay Time for 1.35 V
 728   SPD3_LRDIMM_MODULE_DELAY_TIME                 MinimumModuleDelayTimeFor1_25V;   ///< 94    Minimum Module Delay Time for 1.25 V
 729   SPD3_LRDIMM_MODULE_DELAY_TIME                 MaximumModuleDelayTimeFor1_25V;   ///< 95    Maximum Module Delay Time for 1.25 V
 730   UINT8                                         Reserved[101 - 96 + 1];           ///< 96-101  Reserved
 731   UINT8                                         PersonalityByte[116 - 102 + 1];   ///< 102-116 Memory Buffer Personality Bytes
 732 } SPD3_MODULE_LOADREDUCED;
 733
 734 typedef union {
 735   SPD3_MODULE_UNBUFFERED              Unbuffered;               ///< 128-255 Unbuffered Memory Module Types
 736   SPD3_MODULE_REGISTERED              Registered;               ///< 128-255 Registered Memory Module Types
 737   SPD3_MODULE_CLOCKED                 Clocked;                  ///< 128-255 Registered Memory Module Types
 738   SPD3_MODULE_LOADREDUCED             LoadReduced;              ///< 128-255 Load Reduced Memory Module Types
 739 } SPD3_MODULE_SPECIFIC;
 740
 741 typedef struct {
 742   UINT8                          ModulePartNumber[145 - 128 + 1];        ///< 128-145 Module Part Number
 743 } SPD3_MODULE_PART_NUMBER;
 744
 745 typedef struct {
 746   UINT8                          ModuleRevisionCode[147 - 146 + 1];      ///< 146-147 Module Revision Code
 747 } SPD3_MODULE_REVISION_CODE;
 748
 749 typedef struct {
 750   UINT8                          ManufacturerSpecificData[175 - 150 + 1];///< 150-175 Manufacturer's Specific Data
 751 } SPD3_MANUFACTURER_SPECIFIC;
 752
 753 ///
 754 /// DDR3 Serial Presence Detect structure
 755 ///
 756 typedef struct {
 757   SPD3_BASE_SECTION           General;                                ///< 0-59    General Section
 758   SPD3_MODULE_SPECIFIC        Module;                                 ///< 60-116  Module-Specific Section
 759   SPD3_UNIQUE_MODULE_ID       ModuleId;                               ///< 117-125 Unique Module ID
 760   SPD3_CYCLIC_REDUNDANCY_CODE Crc;                                    ///< 126-127 Cyclical Redundancy Code (CRC)
 761   SPD3_MODULE_PART_NUMBER     ModulePartNumber;                       ///< 128-145 Module Part Number
 762   SPD3_MODULE_REVISION_CODE   ModuleRevisionCode;                     ///< 146-147 Module Revision Code
 763   SPD3_MANUFACTURER_ID_CODE   DramIdCode;                             ///< 148-149 Dram Manufacturer ID Code
 764   SPD3_MANUFACTURER_SPECIFIC  ManufacturerSpecificData;               ///< 150-175 Manufacturer's Specific Data
 765   UINT8                       Reserved[255 - 176 + 1];                ///< 176-255 Open for Customer Use
 766 } SPD_DDR3;
 767
 768 #pragma pack (pop)
 769 #endif