MdePkg: Add TPM TIS definition.
[mirror_edk2.git] / MdePkg / Include / IndustryStandard / TpmTis.h
1 /** @file
2 TPM Interface Specification definition.
3 It covers both TPM1.2 and TPM2.0.
4
5 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #ifndef _TPM_TIS_H_
17 #define _TPM_TIS_H_
18
19 //
20 // Set structure alignment to 1-byte
21 //
22 #pragma pack (1)
23
24 //
25 // Register set map as specified in TIS specification Chapter 10
26 //
27 typedef struct {
28 ///
29 /// Used to gain ownership for this particular port.
30 ///
31 UINT8 Access; // 0
32 UINT8 Reserved1[7]; // 1
33 ///
34 /// Controls interrupts.
35 ///
36 UINT32 IntEnable; // 8
37 ///
38 /// SIRQ vector to be used by the TPM.
39 ///
40 UINT8 IntVector; // 0ch
41 UINT8 Reserved2[3]; // 0dh
42 ///
43 /// What caused interrupt.
44 ///
45 UINT32 IntSts; // 10h
46 ///
47 /// Shows which interrupts are supported by that particular TPM.
48 ///
49 UINT32 IntfCapability; // 14h
50 ///
51 /// Status Register. Provides status of the TPM.
52 ///
53 UINT8 Status; // 18h
54 ///
55 /// Number of consecutive writes that can be done to the TPM.
56 ///
57 UINT16 BurstCount; // 19h
58 UINT8 Reserved3[9];
59 ///
60 /// Read or write FIFO, depending on transaction.
61 ///
62 UINT32 DataFifo; // 24h
63 UINT8 Reserved4[0xed8]; // 28h
64 ///
65 /// Vendor ID
66 ///
67 UINT16 Vid; // 0f00h
68 ///
69 /// Device ID
70 ///
71 UINT16 Did; // 0f02h
72 ///
73 /// Revision ID
74 ///
75 UINT8 Rid; // 0f04h
76 UINT8 Reserved[0x7b]; // 0f05h
77 ///
78 /// Alias to I/O legacy space.
79 ///
80 UINT32 LegacyAddress1; // 0f80h
81 ///
82 /// Additional 8 bits for I/O legacy space extension.
83 ///
84 UINT32 LegacyAddress1Ex; // 0f84h
85 ///
86 /// Alias to second I/O legacy space.
87 ///
88 UINT32 LegacyAddress2; // 0f88h
89 ///
90 /// Additional 8 bits for second I/O legacy space extension.
91 ///
92 UINT32 LegacyAddress2Ex; // 0f8ch
93 ///
94 /// Vendor-defined configuration registers.
95 ///
96 UINT8 VendorDefined[0x70];// 0f90h
97 } TIS_PC_REGISTERS;
98
99 //
100 // Restore original structure alignment
101 //
102 #pragma pack ()
103
104 //
105 // Define pointer types used to access TIS registers on PC
106 //
107 typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;
108
109 //
110 // Define bits of ACCESS and STATUS registers
111 //
112
113 ///
114 /// This bit is a 1 to indicate that the other bits in this register are valid.
115 ///
116 #define TIS_PC_VALID BIT7
117 ///
118 /// Indicate that this locality is active.
119 ///
120 #define TIS_PC_ACC_ACTIVE BIT5
121 ///
122 /// Set to 1 to indicate that this locality had the TPM taken away while
123 /// this locality had the TIS_PC_ACC_ACTIVE bit set.
124 ///
125 #define TIS_PC_ACC_SEIZED BIT4
126 ///
127 /// Set to 1 to indicate that TPM MUST reset the
128 /// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
129 /// locality that is writing this bit.
130 ///
131 #define TIS_PC_ACC_SEIZE BIT3
132 ///
133 /// When this bit is 1, another locality is requesting usage of the TPM.
134 ///
135 #define TIS_PC_ACC_PENDIND BIT2
136 ///
137 /// Set to 1 to indicate that this locality is requesting to use TPM.
138 ///
139 #define TIS_PC_ACC_RQUUSE BIT1
140 ///
141 /// A value of 1 indicates that a T/OS has not been established on the platform
142 ///
143 #define TIS_PC_ACC_ESTABLISH BIT0
144
145 ///
146 /// This field indicates that STS_DATA and STS_EXPECT are valid
147 ///
148 #define TIS_PC_STS_VALID BIT7
149 ///
150 /// When this bit is 1, TPM is in the Ready state,
151 /// indicating it is ready to receive a new command.
152 ///
153 #define TIS_PC_STS_READY BIT6
154 ///
155 /// Write a 1 to this bit to cause the TPM to execute that command.
156 ///
157 #define TIS_PC_STS_GO BIT5
158 ///
159 /// This bit indicates that the TPM has data available as a response.
160 ///
161 #define TIS_PC_STS_DATA BIT4
162 ///
163 /// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
164 ///
165 #define TIS_PC_STS_EXPECT BIT3
166 ///
167 /// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.
168 ///
169 #define TIS_PC_STS_SELFTEST_DONE BIT2
170 ///
171 /// Writes a 1 to this bit to force the TPM to re-send the response.
172 ///
173 #define TIS_PC_STS_RETRY BIT1
174
175 //
176 // Default TimeOut value
177 //
178 #define TIS_TIMEOUT_A (750 * 1000) // 750ms
179 #define TIS_TIMEOUT_B (2000 * 1000) // 2s
180 #define TIS_TIMEOUT_C (750 * 1000) // 750ms
181 #define TIS_TIMEOUT_D (750 * 1000) // 750ms
182
183 #endif