f150fbc1b02bd24562a00d6ae926ff2fd2ade31c
[mirror_edk2.git] / MdePkg / Include / IndustryStandard / pci22.h
1 /** @file
2 Support for PCI 2.2 standard.
3
4 Copyright (c) 2006, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 Module Name: pci22.h
14
15 **/
16
17 #ifndef _PCI22_H
18 #define _PCI22_H
19
20 #define PCI_MAX_SEGMENT 0
21
22 #define PCI_MAX_BUS 255
23
24 #define PCI_MAX_DEVICE 31
25 #define PCI_MAX_FUNC 7
26
27 //
28 // Command
29 //
30 #define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20
31
32 #pragma pack(push, 1)
33 typedef struct {
34 UINT16 VendorId;
35 UINT16 DeviceId;
36 UINT16 Command;
37 UINT16 Status;
38 UINT8 RevisionID;
39 UINT8 ClassCode[3];
40 UINT8 CacheLineSize;
41 UINT8 LatencyTimer;
42 UINT8 HeaderType;
43 UINT8 BIST;
44 } PCI_DEVICE_INDEPENDENT_REGION;
45
46 typedef struct {
47 UINT32 Bar[6];
48 UINT32 CISPtr;
49 UINT16 SubsystemVendorID;
50 UINT16 SubsystemID;
51 UINT32 ExpansionRomBar;
52 UINT8 CapabilityPtr;
53 UINT8 Reserved1[3];
54 UINT32 Reserved2;
55 UINT8 InterruptLine;
56 UINT8 InterruptPin;
57 UINT8 MinGnt;
58 UINT8 MaxLat;
59 } PCI_DEVICE_HEADER_TYPE_REGION;
60
61 typedef struct {
62 PCI_DEVICE_INDEPENDENT_REGION Hdr;
63 PCI_DEVICE_HEADER_TYPE_REGION Device;
64 } PCI_TYPE00;
65
66 typedef struct {
67 UINT32 Bar[2];
68 UINT8 PrimaryBus;
69 UINT8 SecondaryBus;
70 UINT8 SubordinateBus;
71 UINT8 SecondaryLatencyTimer;
72 UINT8 IoBase;
73 UINT8 IoLimit;
74 UINT16 SecondaryStatus;
75 UINT16 MemoryBase;
76 UINT16 MemoryLimit;
77 UINT16 PrefetchableMemoryBase;
78 UINT16 PrefetchableMemoryLimit;
79 UINT32 PrefetchableBaseUpper32;
80 UINT32 PrefetchableLimitUpper32;
81 UINT16 IoBaseUpper16;
82 UINT16 IoLimitUpper16;
83 UINT8 CapabilityPtr;
84 UINT8 Reserved[3];
85 UINT32 ExpansionRomBAR;
86 UINT8 InterruptLine;
87 UINT8 InterruptPin;
88 UINT16 BridgeControl;
89 } PCI_BRIDGE_CONTROL_REGISTER;
90
91 typedef struct {
92 PCI_DEVICE_INDEPENDENT_REGION Hdr;
93 PCI_BRIDGE_CONTROL_REGISTER Bridge;
94 } PCI_TYPE01;
95
96 typedef union {
97 PCI_TYPE00 Device;
98 PCI_TYPE01 Bridge;
99 } PCI_TYPE_GENERIC;
100
101 typedef struct {
102 UINT32 CardBusSocketReg; // Cardus Socket/ExCA Base
103 // Address Register
104 //
105 UINT16 Reserved;
106 UINT16 SecondaryStatus; // Secondary Status
107 UINT8 PciBusNumber; // PCI Bus Number
108 UINT8 CardBusBusNumber; // CardBus Bus Number
109 UINT8 SubordinateBusNumber; // Subordinate Bus Number
110 UINT8 CardBusLatencyTimer; // CardBus Latency Timer
111 UINT32 MemoryBase0; // Memory Base Register 0
112 UINT32 MemoryLimit0; // Memory Limit Register 0
113 UINT32 MemoryBase1;
114 UINT32 MemoryLimit1;
115 UINT32 IoBase0;
116 UINT32 IoLimit0; // I/O Base Register 0
117 UINT32 IoBase1; // I/O Limit Register 0
118 UINT32 IoLimit1;
119 UINT8 InterruptLine; // Interrupt Line
120 UINT8 InterruptPin; // Interrupt Pin
121 UINT16 BridgeControl; // Bridge Control
122 } PCI_CARDBUS_CONTROL_REGISTER;
123
124 //
125 // Definitions of PCI class bytes and manipulation macros.
126 //
127 #define PCI_CLASS_OLD 0x00
128 #define PCI_CLASS_OLD_OTHER 0x00
129 #define PCI_CLASS_OLD_VGA 0x01
130
131 #define PCI_CLASS_MASS_STORAGE 0x01
132 #define PCI_CLASS_MASS_STORAGE_SCSI 0x00
133 #define PCI_CLASS_MASS_STORAGE_IDE 0x01 // obsolete
134 #define PCI_CLASS_IDE 0x01
135 #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
136 #define PCI_CLASS_MASS_STORAGE_IPI 0x03
137 #define PCI_CLASS_MASS_STORAGE_RAID 0x04
138 #define PCI_CLASS_MASS_STORAGE_OTHER 0x80
139
140 #define PCI_CLASS_NETWORK 0x02
141 #define PCI_CLASS_NETWORK_ETHERNET 0x00
142 #define PCI_CLASS_ETHERNET 0x00 // obsolete
143 #define PCI_CLASS_NETWORK_TOKENRING 0x01
144 #define PCI_CLASS_NETWORK_FDDI 0x02
145 #define PCI_CLASS_NETWORK_ATM 0x03
146 #define PCI_CLASS_NETWORK_ISDN 0x04
147 #define PCI_CLASS_NETWORK_OTHER 0x80
148
149 #define PCI_CLASS_DISPLAY 0x03
150 #define PCI_CLASS_DISPLAY_CTRL 0x03 // obsolete
151 #define PCI_CLASS_DISPLAY_VGA 0x00
152 #define PCI_CLASS_VGA 0x00 // obsolete
153 #define PCI_CLASS_DISPLAY_XGA 0x01
154 #define PCI_CLASS_DISPLAY_3D 0x02
155 #define PCI_CLASS_DISPLAY_OTHER 0x80
156 #define PCI_CLASS_DISPLAY_GFX 0x80
157 #define PCI_CLASS_GFX 0x80 // obsolete
158 #define PCI_CLASS_BRIDGE 0x06
159 #define PCI_CLASS_BRIDGE_HOST 0x00
160 #define PCI_CLASS_BRIDGE_ISA 0x01
161 #define PCI_CLASS_ISA 0x01 // obsolete
162 #define PCI_CLASS_BRIDGE_EISA 0x02
163 #define PCI_CLASS_BRIDGE_MCA 0x03
164 #define PCI_CLASS_BRIDGE_P2P 0x04
165 #define PCI_CLASS_BRIDGE_PCMCIA 0x05
166 #define PCI_CLASS_BRIDGE_NUBUS 0x06
167 #define PCI_CLASS_BRIDGE_CARDBUS 0x07
168 #define PCI_CLASS_BRIDGE_RACEWAY 0x08
169 #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
170 #define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete
171
172 #define PCI_CLASS_SCC 0x07 // Simple communications controllers
173 #define PCI_SUBCLASS_SERIAL 0x00
174 #define PCI_IF_GENERIC_XT 0x00
175 #define PCI_IF_16450 0x01
176 #define PCI_IF_16550 0x02
177 #define PCI_IF_16650 0x03
178 #define PCI_IF_16750 0x04
179 #define PCI_IF_16850 0x05
180 #define PCI_IF_16950 0x06
181 #define PCI_SUBCLASS_PARALLEL 0x01
182 #define PCI_IF_PARALLEL_PORT 0x00
183 #define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
184 #define PCI_IF_ECP_PARALLEL_PORT 0x02
185 #define PCI_IF_1284_CONTROLLER 0x03
186 #define PCI_IF_1284_DEVICE 0xFE
187 #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
188 #define PCI_SUBCLASS_MODEM 0x03
189 #define PCI_IF_GENERIC_MODEM 0x00
190 #define PCI_IF_16450_MODEM 0x01
191 #define PCI_IF_16550_MODEM 0x02
192 #define PCI_IF_16650_MODEM 0x03
193 #define PCI_IF_16750_MODEM 0x04
194 #define PCI_SUBCLASS_OTHER 0x80
195
196 #define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
197 #define PCI_SUBCLASS_PIC 0x00
198 #define PCI_IF_8259_PIC 0x00
199 #define PCI_IF_ISA_PIC 0x01
200 #define PCI_IF_EISA_PIC 0x02
201 #define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.
202 #define PCI_IF_APIC_CONTROLLER2 0x20
203 #define PCI_SUBCLASS_TIMER 0x02
204 #define PCI_IF_8254_TIMER 0x00
205 #define PCI_IF_ISA_TIMER 0x01
206 #define PCI_EISA_TIMER 0x02
207 #define PCI_SUBCLASS_RTC 0x03
208 #define PCI_IF_GENERIC_RTC 0x00
209 #define PCI_IF_ISA_RTC 0x00
210 #define PCI_SUBCLASS_PNP_CONTROLLER 0x04 // HotPlug Controller
211
212 #define PCI_CLASS_INPUT_DEVICE 0x09
213 #define PCI_SUBCLASS_KEYBOARD 0x00
214 #define PCI_SUBCLASS_PEN 0x01
215 #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
216 #define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
217 #define PCI_SUBCLASS_GAMEPORT 0x04
218
219 #define PCI_CLASS_DOCKING_STATION 0x0A
220
221 #define PCI_CLASS_PROCESSOR 0x0B
222 #define PCI_SUBCLASS_PROC_386 0x00
223 #define PCI_SUBCLASS_PROC_486 0x01
224 #define PCI_SUBCLASS_PROC_PENTIUM 0x02
225 #define PCI_SUBCLASS_PROC_ALPHA 0x10
226 #define PCI_SUBCLASS_PROC_POWERPC 0x20
227 #define PCI_SUBCLASS_PROC_MIPS 0x30
228 #define PCI_SUBCLASS_PROC_CO_PORC 0x40 // Co-Processor
229
230 #define PCI_CLASS_SERIAL 0x0C
231 #define PCI_CLASS_SERIAL_FIREWIRE 0x00
232 #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
233 #define PCI_CLASS_SERIAL_SSA 0x02
234 #define PCI_CLASS_SERIAL_USB 0x03
235 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
236 #define PCI_CLASS_SERIAL_SMB 0x05
237
238 #define PCI_CLASS_WIRELESS 0x0D
239 #define PCI_SUBCLASS_IRDA 0x00
240 #define PCI_SUBCLASS_IR 0x01
241 #define PCI_SUBCLASS_RF 0x02
242
243 #define PCI_CLASS_INTELLIGENT_IO 0x0E
244
245 #define PCI_CLASS_SATELLITE 0x0F
246 #define PCI_SUBCLASS_TV 0x01
247 #define PCI_SUBCLASS_AUDIO 0x02
248 #define PCI_SUBCLASS_VOICE 0x03
249 #define PCI_SUBCLASS_DATA 0x04
250
251 #define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller
252 #define PCI_SUBCLASS_NET_COMPUT 0x00
253 #define PCI_SUBCLASS_ENTERTAINMENT 0x10
254
255 #define PCI_CLASS_DPIO 0x11
256
257 #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
258 #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
259 #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
260
261 #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
262 #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
263 #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
264 #define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
265 #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
266 #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
267 #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
268 #define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
269 #define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
270 #define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
271 #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
272 #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
273 #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
274
275 #define HEADER_TYPE_DEVICE 0x00
276 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
277 #define HEADER_TYPE_CARDBUS_BRIDGE 0x02
278
279 #define HEADER_TYPE_MULTI_FUNCTION 0x80
280 #define HEADER_LAYOUT_CODE 0x7f
281
282 #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
283 #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
284 #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
285
286 #define PCI_DEVICE_ROMBAR 0x30
287 #define PCI_BRIDGE_ROMBAR 0x38
288
289 #define PCI_MAX_BAR 0x0006
290 #define PCI_MAX_CONFIG_OFFSET 0x0100
291
292 #define PCI_VENDOR_ID_OFFSET 0x00
293 #define PCI_DEVICE_ID_OFFSET 0x02
294 #define PCI_COMMAND_OFFSET 0x04
295 #define PCI_PRIMARY_STATUS_OFFSET 0x06
296 #define PCI_REVISION_ID_OFFSET 0x08
297 #define PCI_CLASSCODE_OFFSET 0x09
298 #define PCI_CACHELINE_SIZE_OFFSET 0x0C
299 #define PCI_LATENCY_TIMER_OFFSET 0x0D
300 #define PCI_HEADER_TYPE_OFFSET 0x0E
301 #define PCI_BIST_OFFSET 0x0F
302 #define PCI_BASE_ADDRESSREG_OFFSET 0x10
303 #define PCI_CARDBUS_CIS_OFFSET 0x28
304 #define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id
305 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
306 #define PCI_SID_OFFSET 0x2E // SubSystem ID
307 #define PCI_SUBSYSTEM_ID_OFFSET 0x2E
308 #define PCI_EXPANSION_ROM_BASE 0x30
309 #define PCI_CAPBILITY_POINTER_OFFSET 0x34
310 #define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register
311 #define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register
312 #define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register
313 #define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register
314
315 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
316 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
317
318 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
319 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
320 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
321
322 typedef union {
323 struct {
324 UINT32 Reg : 8;
325 UINT32 Func : 3;
326 UINT32 Dev : 5;
327 UINT32 Bus : 8;
328 UINT32 Reserved : 7;
329 UINT32 Enable : 1;
330 } Bits;
331 UINT32 Uint32;
332 } PCI_CONFIG_ACCESS_CF8;
333
334 #pragma pack()
335
336 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
337 #define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'I', 'R')
338 #define PCI_CODE_TYPE_PCAT_IMAGE 0x00
339 #define PCI_CODE_TYPE_EFI_IMAGE 0x03
340 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001
341
342 #define EFI_PCI_COMMAND_IO_SPACE 0x0001
343 #define EFI_PCI_COMMAND_MEMORY_SPACE 0x0002
344 #define EFI_PCI_COMMAND_BUS_MASTER 0x0004
345 #define EFI_PCI_COMMAND_SPECIAL_CYCLE 0x0008
346 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE 0x0010
347 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP 0x0020
348 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND 0x0040
349 #define EFI_PCI_COMMAND_STEPPING_CONTROL 0x0080
350 #define EFI_PCI_COMMAND_SERR 0x0100
351 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK 0x0200
352
353 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE 0x0001
354 #define EFI_PCI_BRIDGE_CONTROL_SERR 0x0002
355 #define EFI_PCI_BRIDGE_CONTROL_ISA 0x0004
356 #define EFI_PCI_BRIDGE_CONTROL_VGA 0x0008
357 #define EFI_PCI_BRIDGE_CONTROL_VGA_16 0x0010
358 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT 0x0020
359 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS 0x0040
360 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK 0x0080
361 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER 0x0100
362 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER 0x0200
363 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS 0x0400
364 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR 0x0800
365
366 //
367 // Following are the PCI-CARDBUS bridge control bit
368 //
369 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE 0x0080
370 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE 0x0100
371 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE 0x0200
372 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400
373
374 //
375 // Following are the PCI status control bit
376 //
377 #define EFI_PCI_STATUS_CAPABILITY 0x0010
378 #define EFI_PCI_STATUS_66MZ_CAPABLE 0x0020
379 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE 0x0080
380 #define EFI_PCI_MASTER_DATA_PARITY_ERROR 0x0100
381
382 #define EFI_PCI_CAPABILITY_PTR 0x34
383 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
384
385 #pragma pack(1)
386 typedef struct {
387 UINT16 Signature; // 0xaa55
388 UINT8 Reserved[0x16];
389 UINT16 PcirOffset;
390 } PCI_EXPANSION_ROM_HEADER;
391
392 typedef struct {
393 UINT16 Signature; // 0xaa55
394 UINT8 Size512;
395 UINT8 InitEntryPoint[3];
396 UINT8 Reserved[0x12];
397 UINT16 PcirOffset;
398 } EFI_LEGACY_EXPANSION_ROM_HEADER;
399
400 typedef struct {
401 UINT32 Signature; // "PCIR"
402 UINT16 VendorId;
403 UINT16 DeviceId;
404 UINT16 Reserved0;
405 UINT16 Length;
406 UINT8 Revision;
407 UINT8 ClassCode[3];
408 UINT16 ImageLength;
409 UINT16 CodeRevision;
410 UINT8 CodeType;
411 UINT8 Indicator;
412 UINT16 Reserved1;
413 } PCI_DATA_STRUCTURE;
414
415 //
416 // PCI Capability List IDs and records
417 //
418 #define EFI_PCI_CAPABILITY_ID_PMI 0x01
419 #define EFI_PCI_CAPABILITY_ID_AGP 0x02
420 #define EFI_PCI_CAPABILITY_ID_VPD 0x03
421 #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
422 #define EFI_PCI_CAPABILITY_ID_MSI 0x05
423 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
424 #define EFI_PCI_CAPABILITY_ID_PCIX 0x07
425
426 typedef struct {
427 UINT8 CapabilityID;
428 UINT8 NextItemPtr;
429 } EFI_PCI_CAPABILITY_HDR;
430
431 //
432 // Capability EFI_PCI_CAPABILITY_ID_PMI
433 //
434 typedef struct {
435 EFI_PCI_CAPABILITY_HDR Hdr;
436 UINT16 PMC;
437 UINT16 PMCSR;
438 UINT8 BridgeExtention;
439 UINT8 Data;
440 } EFI_PCI_CAPABILITY_PMI;
441
442 //
443 // Capability EFI_PCI_CAPABILITY_ID_AGP
444 //
445 typedef struct {
446 EFI_PCI_CAPABILITY_HDR Hdr;
447 UINT8 Rev;
448 UINT8 Reserved;
449 UINT32 Status;
450 UINT32 Command;
451 } EFI_PCI_CAPABILITY_AGP;
452
453 //
454 // Capability EFI_PCI_CAPABILITY_ID_VPD
455 //
456 typedef struct {
457 EFI_PCI_CAPABILITY_HDR Hdr;
458 UINT16 AddrReg;
459 UINT32 DataReg;
460 } EFI_PCI_CAPABILITY_VPD;
461
462 //
463 // Capability EFI_PCI_CAPABILITY_ID_SLOTID
464 //
465 typedef struct {
466 EFI_PCI_CAPABILITY_HDR Hdr;
467 UINT8 ExpnsSlotReg;
468 UINT8 ChassisNo;
469 } EFI_PCI_CAPABILITY_SLOTID;
470
471 //
472 // Capability EFI_PCI_CAPABILITY_ID_MSI
473 //
474 typedef struct {
475 EFI_PCI_CAPABILITY_HDR Hdr;
476 UINT16 MsgCtrlReg;
477 UINT32 MsgAddrReg;
478 UINT16 MsgDataReg;
479 } EFI_PCI_CAPABILITY_MSI32;
480
481 typedef struct {
482 EFI_PCI_CAPABILITY_HDR Hdr;
483 UINT16 MsgCtrlReg;
484 UINT32 MsgAddrRegLsdw;
485 UINT32 MsgAddrRegMsdw;
486 UINT16 MsgDataReg;
487 } EFI_PCI_CAPABILITY_MSI64;
488
489 //
490 // Capability EFI_PCI_CAPABILITY_ID_HOTPLUG
491 //
492 typedef struct {
493 EFI_PCI_CAPABILITY_HDR Hdr;
494 //
495 // not finished - fields need to go here
496 //
497 } EFI_PCI_CAPABILITY_HOTPLUG;
498
499 //
500 // Capability EFI_PCI_CAPABILITY_ID_PCIX
501 //
502 typedef struct {
503 EFI_PCI_CAPABILITY_HDR Hdr;
504 UINT16 CommandReg;
505 UINT32 StatusReg;
506 } EFI_PCI_CAPABILITY_PCIX;
507
508 typedef struct {
509 EFI_PCI_CAPABILITY_HDR Hdr;
510 UINT16 SecStatusReg;
511 UINT32 StatusReg;
512 UINT32 SplitTransCtrlRegUp;
513 UINT32 SplitTransCtrlRegDn;
514 } EFI_PCI_CAPABILITY_PCIX_BRDG;
515
516 #define DEVICE_ID_NOCARE 0xFFFF
517
518 #define PCI_ACPI_UNUSED 0
519 #define PCI_BAR_NOCHANGE 0
520 #define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
521 #define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
522 #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
523 #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
524
525 #define PCI_BAR_IDX0 0x00
526 #define PCI_BAR_IDX1 0x01
527 #define PCI_BAR_IDX2 0x02
528 #define PCI_BAR_IDX3 0x03
529 #define PCI_BAR_IDX4 0x04
530 #define PCI_BAR_IDX5 0x05
531 #define PCI_BAR_ALL 0xFF
532
533 #pragma pack(pop)
534
535 //
536 // NOTE: The following header files are included here for
537 // compatibility consideration.
538 //
539 #include "pci23.h"
540 #include "pci30.h"
541 #include "EfiPci.h"
542
543 #endif