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git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Include/Ipf/Pal.h
2 Main PAL API's defined in IPF PAL Spec.
4 Copyright (c) 2006 - 2007, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
21 // IPF Specific Functions
34 // CacheType of PAL_CACHE_FLUSH.
36 #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1
37 #define PAL_CACHE_FLUSH_DATA_ALL 2
38 #define PAL_CACHE_FLUSH_ALL 3
39 #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4
43 // Bitmask of Opearation of PAL_CACHE_FLUSH.
45 #define PAL_CACHE_FLUSH_INVIDED_LINES BIT0
46 #define PAL_CACHE_FLUSH_PROBE_INTERRUPT BIT1
50 Flush the instruction or data caches. It is required by IPF.
51 The PAL procedure supports the Static Registers calling
52 convention. It could be called at virtual mode and physical
55 @param Index Index of PAL_CACHE_FLUSH within the
56 list of PAL procedures.
58 @param CacheType Unsigned 64-bit integer indicating
61 @param Operation Formatted bit vector indicating the
62 operation of this call.
64 @param ProgressIndicator Unsigned 64-bit integer specifying
65 the starting position of the flush
68 @return R9 Unsigned 64-bit integer specifying the vector
69 number of the pending interrupt.
71 @return R10 Unsigned 64-bit integer specifying the
72 starting position of the flush operation.
74 @return R11 Unsigned 64-bit integer specifying the vector
75 number of the pending interrupt.
77 @return Status 2 - Call completed without error, but a PMI
78 was taken during the execution of this
81 @return Status 1 - Call has not completed flushing due to
84 @return Status 0 - Call completed without error
86 @return Status -2 - Invalid argument
88 @return Status -3 - Call completed with error
91 #define PAL_CACHE_FLUSH 1
95 // Attributes of PAL_CACHE_CONFIG_INFO1
97 #define PAL_CACHE_ATTR_WT 0
98 #define PAL_CACHE_ATTR_WB 1
101 // PAL_CACHE_CONFIG_INFO1.StoreHint
103 #define PAL_CACHE_STORE_TEMPORAL 0
104 #define PAL_CACHE_STORE_NONE_TEMPORAL 3
107 // PAL_CACHE_CONFIG_INFO1.StoreHint
109 #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0
110 #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3
113 // PAL_CACHE_CONFIG_INFO1.StoreHint
115 #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0
116 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1
117 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3
120 // Detail the characteristics of a given processor controlled
121 // cache in the cache hierarchy.
124 UINT64 IsUnified
: 1;
125 UINT64 Attributes
: 2;
126 UINT64 Associativity
:8;
129 UINT64 StoreLatency
:8;
132 } PAL_CACHE_INFO_RETURN1
;
135 // Detail the characteristics of a given processor controlled
136 // cache in the cache hierarchy.
140 UINT64 AliasBoundary
:8;
143 } PAL_CACHE_INFO_RETURN2
;
147 Return detailed instruction or data cache information. It is
148 required by IPF. The PAL procedure supports the Static
149 Registers calling convention. It could be called at virtual
150 mode and physical mode.
152 @param Index Index of PAL_CACHE_INFO within the list of
155 @param CacheLevel Unsigned 64-bit integer specifying the
156 level in the cache hierarchy for which
157 information is requested. This value must
158 be between 0 and one less than the value
159 returned in the cache_levels return value
160 from PAL_CACHE_SUMMARY.
162 @param CacheType Unsigned 64-bit integer with a value of 1
163 for instruction cache and 2 for data or
164 unified cache. All other values are
167 @param Reserved Should be 0.
170 @return R9 Detail the characteristics of a given
171 processor controlled cache in the cache
172 hierarchy. See PAL_CACHE_INFO_RETURN1.
174 @return R10 Detail the characteristics of a given
175 processor controlled cache in the cache
176 hierarchy. See PAL_CACHE_INFO_RETURN2.
178 @return R11 Reserved with 0.
181 @return Status 0 - Call completed without error
183 @return Status -2 - Invalid argument
185 @return Status -3 - Call completed with error
188 #define PAL_CACHE_INFO 2
193 // Level of PAL_CACHE_INIT.
195 #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL
198 // Restrict of PAL_CACHE_INIT.
200 #define PAL_CACHE_INIT_NO_RESTRICT 0
201 #define PAL_CACHE_INIT_RESTRICTED 1
205 Initialize the instruction or data caches. It is required by
206 IPF. The PAL procedure supports the Static Registers calling
207 convention. It could be called at physical mode.
209 @param Index Index of PAL_CACHE_INIT within the list of PAL
212 @param Level Unsigned 64-bit integer containing the level of
213 cache to initialize. If the cache level can be
214 initialized independently, only that level will
215 be initialized. Otherwise
216 implementation-dependent side-effects will
219 @param CacheType Unsigned 64-bit integer with a value of 1 to
220 initialize the instruction cache, 2 to
221 initialize the data cache, or 3 to
222 initialize both. All other values are
225 @param Restrict Unsigned 64-bit integer with a value of 0 or
226 1. All other values are reserved. If
227 restrict is 1 and initializing the specified
228 level and cache_type of the cache would
229 cause side-effects, PAL_CACHE_INIT will
230 return -4 instead of initializing the cache.
233 @return Status 0 - Call completed without error
235 @return Status -2 - Invalid argument
237 @return Status -3 - Call completed with error.
239 @return Status -4 - Call could not initialize the specified
240 level and cache_type of the cache without
241 side-effects and restrict was 1.
244 #define PAL_CACHE_INIT 3
248 // PAL_CACHE_PROTECTION.Method.
250 #define PAL_CACHE_PROTECTION_NONE_PROTECT 0
251 #define PAL_CACHE_PROTECTION_ODD_PROTECT 1
252 #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2
253 #define PAL_CACHE_PROTECTION_ECC_PROTECT 3
258 // PAL_CACHE_PROTECTION.TagOrData.
260 #define PAL_CACHE_PROTECTION_PROTECT_DATA 0
261 #define PAL_CACHE_PROTECTION_PROTECT_TAG 1
262 #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2
263 #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3
266 // 32-bit protection information structures.
275 } PAL_CACHE_PROTECTION
;
279 Return instruction or data cache protection information. It is
280 required by IPF. The PAL procedure supports the Static
281 Registers calling convention. It could be called at physical
282 mode and Virtual mode.
284 @param Index Index of PAL_CACHE_PROT_INFO within the list of
287 @param CacheLevel Unsigned 64-bit integer specifying the level
288 in the cache hierarchy for which information
289 is requested. This value must be between 0
290 and one less than the value returned in the
291 cache_levels return value from
294 @param CacheType Unsigned 64-bit integer with a value of 1
295 for instruction cache and 2 for data or
296 unified cache. All other values are
299 @return R9 Detail the characteristics of a given
300 processor controlled cache in the cache
301 hierarchy. See PAL_CACHE_PROTECTION[0..1].
303 @return R10 Detail the characteristics of a given
304 processor controlled cache in the cache
305 hierarchy. See PAL_CACHE_PROTECTION[2..3].
307 @return R11 Detail the characteristics of a given
308 processor controlled cache in the cache
309 hierarchy. See PAL_CACHE_PROTECTION[4..5].
312 @return Status 0 - Call completed without error
314 @return Status -2 - Invalid argument
316 @return Status -3 - Call completed with error.
319 #define PAL_CACHE_PROT_INFO 38
334 Returns information on which logical processors share caches.
337 @param CallingConvention Static Registers
339 @param Mode Physical/Virtual
342 #define PAL_CACHE_SHARED_INFO 43
347 Return a summary of the cache hierarchy. It is required by
350 @param CallingConvention Static Registers
352 @param Mode Physical/Virtual
355 #define PAL_CACHE_SUMMARY 4
359 Return a list of supported memory attributes.. It is required
362 @param CallingConvention Static Registers
364 @param Mode Physical/Virtual
367 #define PAL_MEM_ATTRIB 5
371 Used in architected sequence to transition pages from a
372 cacheable, speculative attribute to an uncacheable attribute.
373 It is required by IPF.
375 @param CallingConvention Static Registers
377 @param Mode Physical/Virtual
380 #define PAL_PREFETCH_VISIBILITY 41
384 Return information needed for ptc.e instruction to purge
385 entire TC. It is required by IPF.
387 @param CallingConvention Static Registers
389 @param Mode Physical/Virtual
392 #define PAL_PTCE_INFO 6
396 Return detailed information about virtual memory features
397 supported in the processor. It is required by IPF.
399 @param CallingConvention Static Registers
401 @param Mode Physical/Virtual
404 #define PAL_VM_INFO 7
409 Return virtual memory TC and hardware walker page sizes
410 supported in the processor. It is required by IPF.
412 @param CallingConvention Static Registers
417 #define PAL_VM_PAGE_SIZE 34
421 Return summary information about virtual memory features
422 supported in the processor. It is required by IPF.
424 @param CallingConvention Static Registers
426 @param Mode Physical/Virtual
429 #define PAL_VM_SUMMARY 8
433 Read contents of a translation register. It is required by
436 @param CallingConvention Stacked Register
441 #define PAL_VM_TR_READ 261
445 Return configurable processor bus interface features and their
446 current settings. It is required by IPF.
448 @param CallingConvention Static Registers
453 #define PAL_BUS_GET_FEATURES 9
458 Enable or disable configurable features in processor bus
459 interface. It is required by IPF.
461 @param CallingConvention Static Registers
466 #define PAL_BUS_SET_FEATURES 10
471 Return the number of instruction and data breakpoint
472 registers. It is required by IPF.
474 @param CallingConvention Static Registers
476 @param Mode Physical/Virtual
479 #define PAL_DEBUG_INFO 11
483 Return the fixed component of a processor¡¯s directed address.
484 It is required by IPF.
486 @param CallingConvention Static Registers
488 @param Mode Physical/Virtual
491 #define PAL_FIXED_ADDR 12
495 Return the frequency of the output clock for use by the
496 platform, if generated by the processor. It is optinal.
498 @param CallingConvention Static Registers
500 @param Mode Physical/Virtual
503 #define PAL_FREQ_BASE 13
507 Return ratio of processor, bus, and interval time counter to
508 processor input clock or output clock for platform use, if
509 generated by the processor. It is required by IPF.
511 @param CallingConvention Static Registers
513 @param Mode Physical/Virtual
516 #define PAL_FREQ_RATIOS 14
520 Return information on which logical processors map to a
521 physical processor die. It is optinal.
523 @param CallingConvention Static Registers
525 @param Mode Physical/Virtual
528 #define PAL_LOGICAL_TO_PHYSICAL 42
532 Return the number and type of performance monitors. It is
535 @param CallingConvention Static Registers
537 @param Mode Physical/Virtual
540 #define PAL_PERF_MON_INFO 15
544 Specify processor interrupt block address and I/O port space
545 address. It is required by IPF.
547 @param CallingConvention Static Registers
549 @param Mode Physical/Virtual
552 #define PAL_PLATFORM_ADDR 16
557 Return configurable processor features and their current
558 setting. It is required by IPF.
560 @param CallingConvention Static Registers
562 @param Mode Physical/Virtual
565 #define PAL_PROC_GET_FEATURES 17
570 Enable or disable configurable processor features. It is
573 @param CallingConvention Static Registers
578 #define PAL_PROC_SET_FEATURES 18
582 Return AR and CR register information. It is required by IPF.
584 @param CallingConvention Static Registers
586 @param Mode Physical/Virtual
589 #define PAL_REGISTER_INFO 39
593 Return RSE information. It is required by
596 @param CallingConvention Static Registers
598 @param Mode Physical/Virtual
601 #define PAL_RSE_INFO 19
605 Return version of PAL code. It is required by IPF.
607 @param CallingConvention Static Registers
609 @param Mode Physical/Virtual
612 #define PAL_VERSION 20
616 Clear all error information from processor error logging
617 registers. It is required by IPF.
619 @param CallingConvention Static Registers
621 @param Mode Physical/Virtual
624 #define PAL_MC_CLEAR_LOG 21
628 Ensure that all operations that could cause an MCA have
629 completed. It is required by IPF.
631 @param CallingConvention Static Registers
633 @param Mode Physical/Virtual
636 #define PAL_MC_DRAIN 22
640 Return Processor Dynamic State for logging by SAL. It is
643 @param CallingConvention Static Registers
648 #define PAL_MC_DYNAMIC_STATE 24
652 Return Processor Machine Check Information and Processor
653 Static State for logging by SAL. It is required by IPF.
655 @param CallingConvention Static Registers
657 @param Mode Physical/Virtual
660 #define PAL_MC_ERROR_INFO 25 Req. Static Both
664 Set/Reset Expected Machine Check Indicator. It is required by
667 @param CallingConvention Static Registers
672 #define PAL_MC_EXPECTED 23
676 Register min-state save area with PAL for machine checks and
677 inits. It is required by IPF.
679 @param CallingConvention Static Registers
684 #define PAL_MC_REGISTER_MEM 27
688 Restore minimal architected state and return to interrupted
689 process. It is required by IPF.
691 @param CallingConvention Static Registers
696 #define PAL_MC_RESUME 26
700 Enter the low-power HALT state or an implementation-dependent
701 low-power state. It is optinal.
703 @param CallingConvention Static Registers
713 Return the low power capabilities of the processor. It is
716 @param CallingConvention Stacked Register
718 @param Mode Physical/Virtual
721 #define PAL_HALT_INFO 257
726 Enter the low power LIGHT HALT state. It is required by
729 @param CallingConvention Static Registers
731 @param Mode Physical/Virtual
734 #define PAL_HALT_LIGHT 29
738 Initialize tags and data of a cache line for processor
739 testing. It is required by IPF.
741 @param CallingConvention Static Registers
746 #define PAL_CACHE_LINE_INIT 31
750 Read tag and data of a cache line for diagnostic testing. It
753 @param CallingConvention Satcked Register
758 #define PAL_CACHE_READ 259
762 Write tag and data of a cache for diagnostic testing. It is
765 @param CallingConvention Satcked Registers
770 #define PAL_CACHE_WRITE 260
774 Returns alignment and size requirements needed for the memory
775 buffer passed to the PAL_TEST_PROC procedure as well as
776 information on self-test control words for the processor self
777 tests. It is required by IPF.
779 @param CallingConvention Static Registers
784 #define PAL_TEST_INFO 37
788 Perform late processor self test. It is required by
791 @param CallingConvention Stacked Registers
796 #define PAL_TEST_PROC 258
800 Return information needed to relocate PAL procedures and PAL
801 PMI code to memory. It is required by IPF.
803 @param CallingConvention Static Registers
808 #define PAL_COPY_INFO 30
812 Relocate PAL procedures and PAL PMI code to memory. It is
815 @param CallingConvention Stacked Registers
820 #define PAL_COPY_PAL 256
824 Enter IA-32 System environment. It is optional.
826 @param CallingConvention Static Registers
831 #define PAL_ENTER_IA_32_ENV 33
835 Register PMI memory entrypoints with processor. It is required
838 @param CallingConvention Static Registers
843 #define PAL_PMI_ENTRYPOINT 32