Rename the PalApi.h to Pal.h.
[mirror_edk2.git] / MdePkg / Include / Ipf / Pal.h
1 /** @file
2 Main PAL API's defined in IPF PAL Spec.
3
4 Copyright (c) 2006 - 2007, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 Module Name: PalApi.h
14
15 **/
16
17 #ifndef __PAL_API_H__
18 #define __PAL_API_H__
19
20 //
21 // IPF Specific Functions
22 //
23
24 typedef struct {
25 UINT64 Status;
26 UINT64 r9;
27 UINT64 r10;
28 UINT64 r11;
29 } PAL_CALL_RETURN;
30
31
32
33 //
34 // CacheType of PAL_CACHE_FLUSH.
35 //
36 #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1
37 #define PAL_CACHE_FLUSH_DATA_ALL 2
38 #define PAL_CACHE_FLUSH_ALL 3
39 #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4
40
41
42 //
43 // Bitmask of Opearation of PAL_CACHE_FLUSH.
44 //
45 #define PAL_CACHE_FLUSH_INVIDED_LINES BIT0
46 #define PAL_CACHE_FLUSH_PROBE_INTERRUPT BIT1
47
48 /**
49
50 Flush the instruction or data caches. It is required by IPF.
51 The PAL procedure supports the Static Registers calling
52 convention. It could be called at virtual mode and physical
53 mode.
54
55 @param Index Index of PAL_CACHE_FLUSH within the
56 list of PAL procedures.
57
58 @param CacheType Unsigned 64-bit integer indicating
59 which cache to flush.
60
61 @param Operation Formatted bit vector indicating the
62 operation of this call.
63
64 @param ProgressIndicator Unsigned 64-bit integer specifying
65 the starting position of the flush
66 operation.
67
68 @return R9 Unsigned 64-bit integer specifying the vector
69 number of the pending interrupt.
70
71 @return R10 Unsigned 64-bit integer specifying the
72 starting position of the flush operation.
73
74 @return R11 Unsigned 64-bit integer specifying the vector
75 number of the pending interrupt.
76
77 @return Status 2 - Call completed without error, but a PMI
78 was taken during the execution of this
79 procedure.
80
81 @return Status 1 - Call has not completed flushing due to
82 a pending interrupt.
83
84 @return Status 0 - Call completed without error
85
86 @return Status -2 - Invalid argument
87
88 @return Status -3 - Call completed with error
89
90 **/
91 #define PAL_CACHE_FLUSH 1
92
93
94 //
95 // Attributes of PAL_CACHE_CONFIG_INFO1
96 //
97 #define PAL_CACHE_ATTR_WT 0
98 #define PAL_CACHE_ATTR_WB 1
99
100 //
101 // PAL_CACHE_CONFIG_INFO1.StoreHint
102 //
103 #define PAL_CACHE_STORE_TEMPORAL 0
104 #define PAL_CACHE_STORE_NONE_TEMPORAL 3
105
106 //
107 // PAL_CACHE_CONFIG_INFO1.StoreHint
108 //
109 #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0
110 #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3
111
112 //
113 // PAL_CACHE_CONFIG_INFO1.StoreHint
114 //
115 #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0
116 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1
117 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3
118
119 //
120 // Detail the characteristics of a given processor controlled
121 // cache in the cache hierarchy.
122 //
123 typedef struct {
124 UINT64 IsUnified : 1;
125 UINT64 Attributes : 2;
126 UINT64 Associativity:8;
127 UINT64 LineSize:8;
128 UINT64 Stride:8;
129 UINT64 StoreLatency:8;
130 UINT64 StoreHint:8;
131 UINT64 LoadHint:8;
132 } PAL_CACHE_INFO_RETURN1;
133
134 //
135 // Detail the characteristics of a given processor controlled
136 // cache in the cache hierarchy.
137 //
138 typedef struct {
139 UINT64 CacheSize:32;
140 UINT64 AliasBoundary:8;
141 UINT64 TagLsBits:8;
142 UINT64 TagMsBits:8;
143 } PAL_CACHE_INFO_RETURN2;
144
145 /**
146
147 Return detailed instruction or data cache information. It is
148 required by IPF. The PAL procedure supports the Static
149 Registers calling convention. It could be called at virtual
150 mode and physical mode.
151
152 @param Index Index of PAL_CACHE_INFO within the list of
153 PAL procedures.
154
155 @param CacheLevel Unsigned 64-bit integer specifying the
156 level in the cache hierarchy for which
157 information is requested. This value must
158 be between 0 and one less than the value
159 returned in the cache_levels return value
160 from PAL_CACHE_SUMMARY.
161
162 @param CacheType Unsigned 64-bit integer with a value of 1
163 for instruction cache and 2 for data or
164 unified cache. All other values are
165 reserved.
166
167 @param Reserved Should be 0.
168
169
170 @return R9 Detail the characteristics of a given
171 processor controlled cache in the cache
172 hierarchy. See PAL_CACHE_INFO_RETURN1.
173
174 @return R10 Detail the characteristics of a given
175 processor controlled cache in the cache
176 hierarchy. See PAL_CACHE_INFO_RETURN2.
177
178 @return R11 Reserved with 0.
179
180
181 @return Status 0 - Call completed without error
182
183 @return Status -2 - Invalid argument
184
185 @return Status -3 - Call completed with error
186
187 **/
188 #define PAL_CACHE_INFO 2
189
190
191
192 //
193 // Level of PAL_CACHE_INIT.
194 //
195 #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL
196
197 //
198 // Restrict of PAL_CACHE_INIT.
199 //
200 #define PAL_CACHE_INIT_NO_RESTRICT 0
201 #define PAL_CACHE_INIT_RESTRICTED 1
202
203 /**
204
205 Initialize the instruction or data caches. It is required by
206 IPF. The PAL procedure supports the Static Registers calling
207 convention. It could be called at physical mode.
208
209 @param Index Index of PAL_CACHE_INIT within the list of PAL
210 procedures.
211
212 @param Level Unsigned 64-bit integer containing the level of
213 cache to initialize. If the cache level can be
214 initialized independently, only that level will
215 be initialized. Otherwise
216 implementation-dependent side-effects will
217 occur.
218
219 @param CacheType Unsigned 64-bit integer with a value of 1 to
220 initialize the instruction cache, 2 to
221 initialize the data cache, or 3 to
222 initialize both. All other values are
223 reserved.
224
225 @param Restrict Unsigned 64-bit integer with a value of 0 or
226 1. All other values are reserved. If
227 restrict is 1 and initializing the specified
228 level and cache_type of the cache would
229 cause side-effects, PAL_CACHE_INIT will
230 return -4 instead of initializing the cache.
231
232
233 @return Status 0 - Call completed without error
234
235 @return Status -2 - Invalid argument
236
237 @return Status -3 - Call completed with error.
238
239 @return Status -4 - Call could not initialize the specified
240 level and cache_type of the cache without
241 side-effects and restrict was 1.
242
243 **/
244 #define PAL_CACHE_INIT 3
245
246
247 //
248 // PAL_CACHE_PROTECTION.Method.
249 //
250 #define PAL_CACHE_PROTECTION_NONE_PROTECT 0
251 #define PAL_CACHE_PROTECTION_ODD_PROTECT 1
252 #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2
253 #define PAL_CACHE_PROTECTION_ECC_PROTECT 3
254
255
256
257 //
258 // PAL_CACHE_PROTECTION.TagOrData.
259 //
260 #define PAL_CACHE_PROTECTION_PROTECT_DATA 0
261 #define PAL_CACHE_PROTECTION_PROTECT_TAG 1
262 #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2
263 #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3
264
265 //
266 // 32-bit protection information structures.
267 //
268 typedef struct {
269 UINT32 DataBits:8;
270 UINT32 TagProtLsb:6;
271 UINT32 TagProtMsb:6;
272 UINT32 ProtBits:6;
273 UINT32 Method:4;
274 UINT32 TagOrData:2;
275 } PAL_CACHE_PROTECTION;
276
277 /**
278
279 Return instruction or data cache protection information. It is
280 required by IPF. The PAL procedure supports the Static
281 Registers calling convention. It could be called at physical
282 mode and Virtual mode.
283
284 @param Index Index of PAL_CACHE_PROT_INFO within the list of
285 PAL procedures.
286
287 @param CacheLevel Unsigned 64-bit integer specifying the level
288 in the cache hierarchy for which information
289 is requested. This value must be between 0
290 and one less than the value returned in the
291 cache_levels return value from
292 PAL_CACHE_SUMMARY.
293
294 @param CacheType Unsigned 64-bit integer with a value of 1
295 for instruction cache and 2 for data or
296 unified cache. All other values are
297 reserved.
298
299 @return R9 Detail the characteristics of a given
300 processor controlled cache in the cache
301 hierarchy. See PAL_CACHE_PROTECTION[0..1].
302
303 @return R10 Detail the characteristics of a given
304 processor controlled cache in the cache
305 hierarchy. See PAL_CACHE_PROTECTION[2..3].
306
307 @return R11 Detail the characteristics of a given
308 processor controlled cache in the cache
309 hierarchy. See PAL_CACHE_PROTECTION[4..5].
310
311
312 @return Status 0 - Call completed without error
313
314 @return Status -2 - Invalid argument
315
316 @return Status -3 - Call completed with error.
317
318 **/
319 #define PAL_CACHE_PROT_INFO 38
320
321
322
323
324
325
326
327 ///
328 // ?????????
329
330
331
332 /**
333
334 Returns information on which logical processors share caches.
335 It is optional.
336
337 @param CallingConvention Static Registers
338
339 @param Mode Physical/Virtual
340
341 **/
342 #define PAL_CACHE_SHARED_INFO 43
343
344
345 /**
346
347 Return a summary of the cache hierarchy. It is required by
348 IPF.
349
350 @param CallingConvention Static Registers
351
352 @param Mode Physical/Virtual
353
354 **/
355 #define PAL_CACHE_SUMMARY 4
356
357 /**
358
359 Return a list of supported memory attributes.. It is required
360 by IPF.
361
362 @param CallingConvention Static Registers
363
364 @param Mode Physical/Virtual
365
366 **/
367 #define PAL_MEM_ATTRIB 5
368
369 /**
370
371 Used in architected sequence to transition pages from a
372 cacheable, speculative attribute to an uncacheable attribute.
373 It is required by IPF.
374
375 @param CallingConvention Static Registers
376
377 @param Mode Physical/Virtual
378
379 **/
380 #define PAL_PREFETCH_VISIBILITY 41
381
382 /**
383
384 Return information needed for ptc.e instruction to purge
385 entire TC. It is required by IPF.
386
387 @param CallingConvention Static Registers
388
389 @param Mode Physical/Virtual
390
391 **/
392 #define PAL_PTCE_INFO 6
393
394 /**
395
396 Return detailed information about virtual memory features
397 supported in the processor. It is required by IPF.
398
399 @param CallingConvention Static Registers
400
401 @param Mode Physical/Virtual
402
403 **/
404 #define PAL_VM_INFO 7
405
406
407 /**
408
409 Return virtual memory TC and hardware walker page sizes
410 supported in the processor. It is required by IPF.
411
412 @param CallingConvention Static Registers
413
414 @param Mode Physical
415
416 **/
417 #define PAL_VM_PAGE_SIZE 34
418
419 /**
420
421 Return summary information about virtual memory features
422 supported in the processor. It is required by IPF.
423
424 @param CallingConvention Static Registers
425
426 @param Mode Physical/Virtual
427
428 **/
429 #define PAL_VM_SUMMARY 8
430
431 /**
432
433 Read contents of a translation register. It is required by
434 IPF.
435
436 @param CallingConvention Stacked Register
437
438 @param Mode Physical
439
440 **/
441 #define PAL_VM_TR_READ 261
442
443 /**
444
445 Return configurable processor bus interface features and their
446 current settings. It is required by IPF.
447
448 @param CallingConvention Static Registers
449
450 @param Mode Physical
451
452 **/
453 #define PAL_BUS_GET_FEATURES 9
454
455
456 /**
457
458 Enable or disable configurable features in processor bus
459 interface. It is required by IPF.
460
461 @param CallingConvention Static Registers
462
463 @param Mode Physical
464
465 **/
466 #define PAL_BUS_SET_FEATURES 10
467
468
469 /**
470
471 Return the number of instruction and data breakpoint
472 registers. It is required by IPF.
473
474 @param CallingConvention Static Registers
475
476 @param Mode Physical/Virtual
477
478 **/
479 #define PAL_DEBUG_INFO 11
480
481 /**
482
483 Return the fixed component of a processor¡¯s directed address.
484 It is required by IPF.
485
486 @param CallingConvention Static Registers
487
488 @param Mode Physical/Virtual
489
490 **/
491 #define PAL_FIXED_ADDR 12
492
493 /**
494
495 Return the frequency of the output clock for use by the
496 platform, if generated by the processor. It is optinal.
497
498 @param CallingConvention Static Registers
499
500 @param Mode Physical/Virtual
501
502 **/
503 #define PAL_FREQ_BASE 13
504
505 /**
506
507 Return ratio of processor, bus, and interval time counter to
508 processor input clock or output clock for platform use, if
509 generated by the processor. It is required by IPF.
510
511 @param CallingConvention Static Registers
512
513 @param Mode Physical/Virtual
514
515 **/
516 #define PAL_FREQ_RATIOS 14
517
518 /**
519
520 Return information on which logical processors map to a
521 physical processor die. It is optinal.
522
523 @param CallingConvention Static Registers
524
525 @param Mode Physical/Virtual
526
527 **/
528 #define PAL_LOGICAL_TO_PHYSICAL 42
529
530 /**
531
532 Return the number and type of performance monitors. It is
533 required by IPF.
534
535 @param CallingConvention Static Registers
536
537 @param Mode Physical/Virtual
538
539 **/
540 #define PAL_PERF_MON_INFO 15
541
542 /**
543
544 Specify processor interrupt block address and I/O port space
545 address. It is required by IPF.
546
547 @param CallingConvention Static Registers
548
549 @param Mode Physical/Virtual
550
551 **/
552 #define PAL_PLATFORM_ADDR 16
553
554
555 /**
556
557 Return configurable processor features and their current
558 setting. It is required by IPF.
559
560 @param CallingConvention Static Registers
561
562 @param Mode Physical/Virtual
563
564 **/
565 #define PAL_PROC_GET_FEATURES 17
566
567
568 /**
569
570 Enable or disable configurable processor features. It is
571 required by IPF.
572
573 @param CallingConvention Static Registers
574
575 @param Mode Physical
576
577 **/
578 #define PAL_PROC_SET_FEATURES 18
579
580 /**
581
582 Return AR and CR register information. It is required by IPF.
583
584 @param CallingConvention Static Registers
585
586 @param Mode Physical/Virtual
587
588 **/
589 #define PAL_REGISTER_INFO 39
590
591 /**
592
593 Return RSE information. It is required by
594 IPF.
595
596 @param CallingConvention Static Registers
597
598 @param Mode Physical/Virtual
599
600 **/
601 #define PAL_RSE_INFO 19
602
603 /**
604
605 Return version of PAL code. It is required by IPF.
606
607 @param CallingConvention Static Registers
608
609 @param Mode Physical/Virtual
610
611 **/
612 #define PAL_VERSION 20
613
614 /**
615
616 Clear all error information from processor error logging
617 registers. It is required by IPF.
618
619 @param CallingConvention Static Registers
620
621 @param Mode Physical/Virtual
622
623 **/
624 #define PAL_MC_CLEAR_LOG 21
625
626 /**
627
628 Ensure that all operations that could cause an MCA have
629 completed. It is required by IPF.
630
631 @param CallingConvention Static Registers
632
633 @param Mode Physical/Virtual
634
635 **/
636 #define PAL_MC_DRAIN 22
637
638 /**
639
640 Return Processor Dynamic State for logging by SAL. It is
641 optional.
642
643 @param CallingConvention Static Registers
644
645 @param Mode Physical
646
647 **/
648 #define PAL_MC_DYNAMIC_STATE 24
649
650 /**
651
652 Return Processor Machine Check Information and Processor
653 Static State for logging by SAL. It is required by IPF.
654
655 @param CallingConvention Static Registers
656
657 @param Mode Physical/Virtual
658
659 **/
660 #define PAL_MC_ERROR_INFO 25 Req. Static Both
661
662 /**
663
664 Set/Reset Expected Machine Check Indicator. It is required by
665 IPF.
666
667 @param CallingConvention Static Registers
668
669 @param Mode Physical
670
671 **/
672 #define PAL_MC_EXPECTED 23
673
674 /**
675
676 Register min-state save area with PAL for machine checks and
677 inits. It is required by IPF.
678
679 @param CallingConvention Static Registers
680
681 @param Mode Physical
682
683 **/
684 #define PAL_MC_REGISTER_MEM 27
685
686 /**
687
688 Restore minimal architected state and return to interrupted
689 process. It is required by IPF.
690
691 @param CallingConvention Static Registers
692
693 @param Mode Physical
694
695 **/
696 #define PAL_MC_RESUME 26
697
698 /**
699
700 Enter the low-power HALT state or an implementation-dependent
701 low-power state. It is optinal.
702
703 @param CallingConvention Static Registers
704
705 @param Mode Physical
706
707 **/
708 #define PAL_HALT 28
709
710
711 /**
712
713 Return the low power capabilities of the processor. It is
714 required by IPF.
715
716 @param CallingConvention Stacked Register
717
718 @param Mode Physical/Virtual
719
720 **/
721 #define PAL_HALT_INFO 257
722
723
724 /**
725
726 Enter the low power LIGHT HALT state. It is required by
727 IPF.
728
729 @param CallingConvention Static Registers
730
731 @param Mode Physical/Virtual
732
733 **/
734 #define PAL_HALT_LIGHT 29
735
736 /**
737
738 Initialize tags and data of a cache line for processor
739 testing. It is required by IPF.
740
741 @param CallingConvention Static Registers
742
743 @param Mode Physical
744
745 **/
746 #define PAL_CACHE_LINE_INIT 31
747
748 /**
749
750 Read tag and data of a cache line for diagnostic testing. It
751 is optional.
752
753 @param CallingConvention Satcked Register
754
755 @param Mode Physical
756
757 **/
758 #define PAL_CACHE_READ 259
759
760 /**
761
762 Write tag and data of a cache for diagnostic testing. It is
763 optional.
764
765 @param CallingConvention Satcked Registers
766
767 @param Mode Physical
768
769 **/
770 #define PAL_CACHE_WRITE 260
771
772 /**
773
774 Returns alignment and size requirements needed for the memory
775 buffer passed to the PAL_TEST_PROC procedure as well as
776 information on self-test control words for the processor self
777 tests. It is required by IPF.
778
779 @param CallingConvention Static Registers
780
781 @param Mode Physical
782
783 **/
784 #define PAL_TEST_INFO 37
785
786 /**
787
788 Perform late processor self test. It is required by
789 IPF.
790
791 @param CallingConvention Stacked Registers
792
793 @param Mode Physical
794
795 **/
796 #define PAL_TEST_PROC 258
797
798 /**
799
800 Return information needed to relocate PAL procedures and PAL
801 PMI code to memory. It is required by IPF.
802
803 @param CallingConvention Static Registers
804
805 @param Mode Physical
806
807 **/
808 #define PAL_COPY_INFO 30
809
810 /**
811
812 Relocate PAL procedures and PAL PMI code to memory. It is
813 required by IPF.
814
815 @param CallingConvention Stacked Registers
816
817 @param Mode Physical
818
819 **/
820 #define PAL_COPY_PAL 256
821
822 /**
823
824 Enter IA-32 System environment. It is optional.
825
826 @param CallingConvention Static Registers
827
828 @param Mode Physical
829
830 **/
831 #define PAL_ENTER_IA_32_ENV 33
832
833 /**
834
835 Register PMI memory entrypoints with processor. It is required
836 by IPF.
837
838 @param CallingConvention Static Registers
839
840 @param Mode Physical
841
842 **/
843 #define PAL_PMI_ENTRYPOINT 32
844
845
846
847 #endif