2 Main SAL API's defined in SAL 3.0 specification.
4 Copyright (c) 2006, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 typedef UINTN EFI_SAL_STATUS
;
23 // EFI_SAL_STATUS defines
25 #define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)
26 #define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)
27 #define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)
28 #define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)
29 #define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)
30 #define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
31 #define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)
32 #define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)
35 // Delivery Mode of IPF CPU.
38 EFI_DELIVERY_MODE_INT
,
39 EFI_DELIVERY_MODE_MPreserved1
,
40 EFI_DELIVERY_MODE_PMI
,
41 EFI_DELIVERY_MODE_MPreserved2
,
42 EFI_DELIVERY_MODE_NMI
,
43 EFI_DELIVERY_MODE_INIT
,
44 EFI_DELIVERY_MODE_MPreserved3
,
45 EFI_DELIVERY_MODE_ExtINT
49 // Return values from SAL
52 EFI_SAL_STATUS Status
; // register r8
58 typedef SAL_RETURN_REGS (EFIAPI
*SAL_PROC
)
71 // SAL Procedure FunctionId definition
73 #define EFI_SAL_SET_VECTORS 0x01000000
74 #define EFI_SAL_GET_STATE_INFO 0x01000001
75 #define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002
76 #define EFI_SAL_CLEAR_STATE_INFO 0x01000003
77 #define EFI_SAL_MC_RENDEZ 0x01000004
78 #define EFI_SAL_MC_SET_PARAMS 0x01000005
79 #define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006
80 #define EFI_SAL_CACHE_FLUSH 0x01000008
81 #define EFI_SAL_CACHE_INIT 0x01000009
82 #define EFI_SAL_PCI_CONFIG_READ 0x01000010
83 #define EFI_SAL_PCI_CONFIG_WRITE 0x01000011
84 #define EFI_SAL_FREQ_BASE 0x01000012
85 #define EFI_SAL_UPDATE_PAL 0x01000020
87 #define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff
88 #define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021
91 // SAL Procedure parameter definitions
92 // Not much point in using typedefs or enums because all params
93 // are UINT64 and the entry point is common
95 // EFI_SAL_SET_VECTORS
97 #define EFI_SAL_SET_MCA_VECTOR 0x0
98 #define EFI_SAL_SET_INIT_VECTOR 0x1
99 #define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2
103 UINT64 ChecksumValid
: 1;
104 UINT64 Reserved1
: 7;
105 UINT64 ByteChecksum
: 8;
106 UINT64 Reserved2
: 16;
107 } SAL_SET_VECTORS_CS_N
;
110 // EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,
111 // EFI_SAL_CLEAR_STATE_INFO
113 #define EFI_SAL_MCA_STATE_INFO 0x0
114 #define EFI_SAL_INIT_STATE_INFO 0x1
115 #define EFI_SAL_CMC_STATE_INFO 0x2
116 #define EFI_SAL_CP_STATE_INFO 0x3
119 // EFI_SAL_MC_SET_PARAMS
121 #define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
122 #define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
123 #define EFI_SAL_MC_SET_CPE_PARAM 0x3
125 #define EFI_SAL_MC_SET_INTR_PARAM 0x1
126 #define EFI_SAL_MC_SET_MEM_PARAM 0x2
129 // EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
131 #define EFI_SAL_REGISTER_PAL_ADDR 0x0
134 // EFI_SAL_CACHE_FLUSH
136 #define EFI_SAL_FLUSH_I_CACHE 0x01
137 #define EFI_SAL_FLUSH_D_CACHE 0x02
138 #define EFI_SAL_FLUSH_BOTH_CACHE 0x03
139 #define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
142 // EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE
144 #define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1
145 #define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2
146 #define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
154 UINT64 Reserved
: 32;
160 #define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0
161 #define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1
162 #define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2
165 // EFI_SAL_UPDATE_PAL
167 #define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)
168 #define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)
169 #define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)
170 #define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)
171 #define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)
172 #define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)
173 #define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)
174 #define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)
183 } SAL_UPDATE_PAL_DATA_BLOCK
;
185 typedef struct _SAL_UPDATE_PAL_INFO_BLOCK
{
186 struct _SAL_UPDATE_PAL_INFO_BLOCK
*Next
;
187 struct SAL_UPDATE_PAL_DATA_BLOCK
*DataBlock
;
190 } SAL_UPDATE_PAL_INFO_BLOCK
;
193 // SAL System Table Definitions
208 } SAL_SYSTEM_TABLE_HEADER
;
211 #define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
212 #define EFI_SAL_REVISION 0x0300
216 #define EFI_SAL_ST_ENTRY_POINT 0
217 #define EFI_SAL_ST_MEMORY_DESCRIPTOR 1
218 #define EFI_SAL_ST_PLATFORM_FEATURES 2
219 #define EFI_SAL_ST_TR_USAGE 3
220 #define EFI_SAL_ST_PTC 4
221 #define EFI_SAL_ST_AP_WAKEUP 5
225 UINT8 Type
; // Type == 0
229 UINT64 SalGlobalDataPointer
;
231 } SAL_ST_ENTRY_POINT_DESCRIPTOR
;
234 // Not needed for Itanium-based OS boot
237 UINT8 Type
; // Type == 1
238 UINT8 NeedVirtualRegistration
;
239 UINT8 MemoryAttributes
;
240 UINT8 PageAccessRights
;
241 UINT8 SupportedAttributes
;
245 UINT64 PhysicalMemoryAddress
;
249 } SAL_ST_MEMORY_DESCRIPTOR_ENTRY
;
255 #define SAL_MDT_ATTRIB_WB 0x00
257 // #define SAL_MDT_ATTRIB_UC 0x02
259 #define SAL_MDT_ATTRIB_UC 0x04
260 #define SAL_MDT_ATTRIB_UCE 0x05
261 #define SAL_MDT_ATTRIB_WC 0x06
264 // Supported memory Attributes
266 #define SAL_MDT_SUPPORT_WB 0x1
267 #define SAL_MDT_SUPPORT_UC 0x2
268 #define SAL_MDT_SUPPORT_UCE 0x4
269 #define SAL_MDT_SUPPORT_WC 0x8
272 // Virtual address registration
274 #define SAL_MDT_NO_VA 0x00
275 #define SAL_MDT_NEED_VA 0x01
279 #define SAL_REGULAR_MEMORY 0x0000
280 #define SAL_MMIO_MAPPING 0x0001
281 #define SAL_SAPIC_IPI_BLOCK 0x0002
282 #define SAL_IO_PORT_MAPPING 0x0003
283 #define SAL_FIRMWARE_MEMORY 0x0004
284 #define SAL_BLACK_HOLE 0x000A
288 #define SAL_MDT_USAGE_UNSPECIFIED 0x00
289 #define SAL_PAL_CODE 0x01
290 #define SAL_BOOTSERVICE_CODE 0x02
291 #define SAL_BOOTSERVICE_DATA 0x03
292 #define SAL_RUNTIMESERVICE_CODE 0x04
293 #define SAL_RUNTIMESERVICE_DATA 0x05
294 #define SAL_IA32_OPTIONROM 0x06
295 #define SAL_IA32_SYSTEMROM 0x07
296 #define SAL_PMI_CODE 0x0a
297 #define SAL_PMI_DATA 0x0b
301 UINT8 Type
; // Type == 2
302 UINT8 PlatformFeatures
;
304 } SAL_ST_PLATFORM_FEATURES
;
307 #define SAL_PLAT_FEAT_BUS_LOCK 0x01
308 #define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
309 #define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
313 UINT8 Type
; // Type == 3
317 UINT64 VirtualAddress
;
318 UINT64 EncodedPageSize
;
320 } SAL_ST_TR_DECRIPTOR
;
323 #define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
324 #define EFI_SAL_ST_TR_USAGE_DATA 01
328 UINT64 NumberOfProcessors
;
329 UINT64 LocalIDRegister
;
330 } SAL_COHERENCE_DOMAIN_INFO
;
335 UINT8 Type
; // Type == 4
337 UINT32 NumberOfDomains
;
338 SAL_COHERENCE_DOMAIN_INFO
*DomainInformation
;
339 } SAL_ST_CACHE_COHERENCE_DECRIPTOR
;
344 UINT8 Type
; // Type == 5
347 UINT64 ExternalInterruptVector
;
348 } SAL_ST_AP_WAKEUP_DECRIPTOR
;
353 #define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24
354 #define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32
355 #define EFI_SAL_FIT_PALB_TYPE 01
363 UINT8 CheckSumValid
: 1;
368 // SAL Common Record Header
390 UINT8 ValidationBits
;
392 SAL_TIME_STAMP TimeStamp
;
393 UINT8 OemPlatformId
[16];
399 UINT8 ErrorRecoveryInfo
;
401 UINT32 SectionLength
;
405 // SAL Processor Record
407 #define SAL_PROCESSOR_ERROR_RECORD_INFO \
409 0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
412 #define CHECK_INFO_VALID_BIT_MASK 0x1
413 #define REQUESTOR_ID_VALID_BIT_MASK 0x2
414 #define RESPONDER_ID_VALID_BIT_MASK 0x4
415 #define TARGER_ID_VALID_BIT_MASK 0x8
416 #define PRECISE_IP_VALID_BIT_MASK 0x10
419 UINT64 InfoValid
: 1;
421 UINT64 RespValid
: 1;
422 UINT64 TargetValid
: 1;
424 UINT64 Reserved
: 59;
442 #define MIN_STATE_VALID_BIT_MASK 0x1
443 #define BR_VALID_BIT_MASK 0x2
444 #define CR_VALID_BIT_MASK 0x4
445 #define AR_VALID_BIT_MASK 0x8
446 #define RR_VALID_BIT_MASK 0x10
447 #define FR_VALID_BIT_MASK 0x20
450 UINT64 ValidFieldBits
;
451 UINT8 MinStateInfo
[1024];
459 #define PROC_ERROR_MAP_VALID_BIT_MASK 0x1
460 #define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
461 #define PROC_CR_LID_VALID_BIT_MASK 0x4
462 #define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8
463 #define CPU_INFO_VALID_BIT_MASK 0x1000000
466 SAL_SEC_HEADER SectionHeader
;
467 UINT64 ValidationBits
;
469 UINT64 ProcStateParameter
;
471 MOD_ERROR_INFO CacheError
[15];
472 MOD_ERROR_INFO TlbError
[15];
473 MOD_ERROR_INFO BusError
[15];
474 MOD_ERROR_INFO RegFileCheck
[15];
475 MOD_ERROR_INFO MsCheck
[15];
477 PSI_STATIC_STRUCT PsiValidData
;
478 } SAL_PROCESSOR_ERROR_RECORD
;
481 // Sal Platform memory Error Record
483 #define SAL_MEMORY_ERROR_RECORD_INFO \
485 0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
488 #define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1
489 #define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2
490 #define MEMORY_ADDR_BIT_MASK 0x4
491 #define MEMORY_NODE_VALID_BIT_MASK 0x8
492 #define MEMORY_CARD_VALID_BIT_MASK 0x10
493 #define MEMORY_MODULE_VALID_BIT_MASK 0x20
494 #define MEMORY_BANK_VALID_BIT_MASK 0x40
495 #define MEMORY_DEVICE_VALID_BIT_MASK 0x80
496 #define MEMORY_ROW_VALID_BIT_MASK 0x100
497 #define MEMORY_COLUMN_VALID_BIT_MASK 0x200
498 #define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400
499 #define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800
500 #define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000
501 #define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000
502 #define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000
503 #define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000
504 #define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000
507 SAL_SEC_HEADER SectionHeader
;
508 UINT64 ValidationBits
;
509 UINT64 MemErrorStatus
;
510 UINT64 MemPhysicalAddress
;
511 UINT64 MemPhysicalAddressMask
;
519 UINT16 MemBitPosition
;
520 UINT64 ModRequestorId
;
521 UINT64 ModResponderId
;
523 UINT64 BusSpecificData
;
524 UINT8 MemPlatformOemId
[16];
525 } SAL_MEMORY_ERROR_RECORD
;
530 #define SAL_PCI_BUS_ERROR_RECORD_INFO \
532 0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
535 #define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1
536 #define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2
537 #define PCI_BUS_ID_VALID_BIT_MASK 0x4
538 #define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8
539 #define PCI_BUS_DATA_VALID_BIT_MASK 0x10
540 #define PCI_BUS_CMD_VALID_BIT_MASK 0x20
541 #define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40
542 #define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80
543 #define PCI_BUS_TARGET_VALID_BIT_MASK 0x100
544 #define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200
545 #define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400
553 SAL_SEC_HEADER SectionHeader
;
554 UINT64 ValidationBits
;
555 UINT64 PciBusErrorStatus
;
556 UINT16 PciBusErrorType
;
559 UINT64 PciBusAddress
;
561 UINT64 PciBusCommand
;
562 UINT64 PciBusRequestorId
;
563 UINT64 PciBusResponderId
;
564 UINT64 PciBusTargetId
;
565 UINT8 PciBusOemId
[16];
566 } SAL_PCI_BUS_ERROR_RECORD
;
569 // PCI Component Errors
571 #define SAL_PCI_COMP_ERROR_RECORD_INFO \
573 0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
576 #define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1
577 #define PCI_COMP_INFO_VALID_BIT_MASK 0x2
578 #define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4
579 #define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8
580 #define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10
581 #define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
587 UINT8 FunctionNumber
;
595 SAL_SEC_HEADER SectionHeader
;
596 UINT64 ValidationBits
;
597 UINT64 PciComponentErrorStatus
;
598 PCI_COMP_INFO PciComponentInfo
;
599 UINT32 PciComponentMemNum
;
600 UINT32 PciComponentIoNum
;
601 UINT8 PciBusOemId
[16];
602 } SAL_PCI_COMPONENT_ERROR_RECORD
;
605 // Sal Device Errors Info.
607 #define SAL_DEVICE_ERROR_RECORD_INFO \
609 0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
612 #define SEL_RECORD_ID_VALID_BIT_MASK 0x1;
613 #define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;
614 #define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;
615 #define SEL_EVM_REV_VALID_BIT_MASK 0x8;
616 #define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;
617 #define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;
618 #define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
619 #define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;
620 #define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;
621 #define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;
624 SAL_SEC_HEADER SectionHeader
;
625 UINT64 ValidationBits
;
637 } SAL_DEVICE_ERROR_RECORD
;
640 // Sal SMBIOS Device Errors Info.
642 #define SAL_SMBIOS_ERROR_RECORD_INFO \
644 0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
647 #define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1
648 #define SMBIOS_LENGTH_VALID_BIT_MASK 0x2
649 #define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4
650 #define SMBIOS_DATA_VALID_BIT_MASK 0x8
653 SAL_SEC_HEADER SectionHeader
;
654 UINT64 ValidationBits
;
655 UINT8 SmbiosEventType
;
657 UINT8 SmbiosBcdTimeStamp
[6];
658 } SAL_SMBIOS_DEVICE_ERROR_RECORD
;
661 // Sal Platform Specific Errors Info.
663 #define SAL_PLATFORM_ERROR_RECORD_INFO \
665 0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
668 #define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1
669 #define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2
670 #define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4
671 #define PLATFORM_TARGET_VALID_BIT_MASK 0x8
672 #define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10
673 #define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20
674 #define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
675 #define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
678 SAL_SEC_HEADER SectionHeader
;
679 UINT64 ValidationBits
;
680 UINT64 PlatformErrorStatus
;
681 UINT64 PlatformRequestorId
;
682 UINT64 PlatformResponderId
;
683 UINT64 PlatformTargetId
;
684 UINT64 PlatformBusSpecificData
;
685 UINT8 OemComponentId
[16];
686 } SAL_PLATFORM_SPECIFIC_ERROR_RECORD
;
689 // Union of all the possible Sal Record Types
692 SAL_RECORD_HEADER
*RecordHeader
;
693 SAL_PROCESSOR_ERROR_RECORD
*SalProcessorRecord
;
694 SAL_PCI_BUS_ERROR_RECORD
*SalPciBusRecord
;
695 SAL_PCI_COMPONENT_ERROR_RECORD
*SalPciComponentRecord
;
696 SAL_DEVICE_ERROR_RECORD
*ImpiRecord
;
697 SAL_SMBIOS_DEVICE_ERROR_RECORD
*SmbiosRecord
;
698 SAL_PLATFORM_SPECIFIC_ERROR_RECORD
*PlatformRecord
;
699 SAL_MEMORY_ERROR_RECORD
*MemoryRecord
;
701 } SAL_ERROR_RECORDS_POINTERS
;