4 Copyright (c) 2006 -2007, Intel Corporation All rights
5 reserved. This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 Module Name: PalCallLib.h
18 #ifndef __PAL_CALL_LIB_H__
19 #define __PAL_CALL_LIB_H__
21 typedef int PAL_CALL_RETURN
;
23 // CacheType of PAL_CACHE_FLUSH.
25 #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1
26 #define PAL_CACHE_FLUSH_DATA_ALL 2
27 #define PAL_CACHE_FLUSH_ALL 3
28 #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4
32 // Bitmask of Opearation of PAL_CACHE_FLUSH.
34 #define PAL_CACHE_FLUSH_INVIDED_LINES BIT0
35 #define PAL_CACHE_FLUSH_PROBE_INTERRUPT BIT1
39 PAL Procedure - PAL_CACHE_FLUSH.
41 Flush the instruction or data caches. It is required by IPF.
42 The PAL procedure supports the Static Registers calling
43 convention. It could be called at virtual mode and physical
46 @param Index Index of PAL_CACHE_FLUSH within the
47 list of PAL procedures.
49 @param CacheType Unsigned 64-bit integer indicating
52 @param Operation Formatted bit vector indicating the
53 operation of this call.
55 @param ProgressIndicator Unsigned 64-bit integer specifying
56 the starting position of the flush
59 @return R9 Unsigned 64-bit integer specifying the vector
60 number of the pending interrupt.
62 @return R10 Unsigned 64-bit integer specifying the
63 starting position of the flush operation.
65 @return R11 Unsigned 64-bit integer specifying the vector
66 number of the pending interrupt.
68 @return Status 2 - Call completed without error, but a PMI
69 was taken during the execution of this
72 @return Status 1 - Call has not completed flushing due to
75 @return Status 0 - Call completed without error
77 @return Status -2 - Invalid argument
79 @return Status -3 - Call completed with error
82 #define PAL_CACHE_FLUSH 1
86 // Attributes of PAL_CACHE_CONFIG_INFO1
88 #define PAL_CACHE_ATTR_WT 0
89 #define PAL_CACHE_ATTR_WB 1
92 // PAL_CACHE_CONFIG_INFO1.StoreHint
94 #define PAL_CACHE_STORE_TEMPORAL 0
95 #define PAL_CACHE_STORE_NONE_TEMPORAL 3
98 // PAL_CACHE_CONFIG_INFO1.StoreHint
100 #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0
101 #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3
104 // PAL_CACHE_CONFIG_INFO1.StoreHint
106 #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0
107 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1
108 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3
111 // Detail the characteristics of a given processor controlled
112 // cache in the cache hierarchy.
115 UINT64 IsUnified
: 1;
116 UINT64 Attributes
: 2;
117 UINT64 Associativity
:8;
120 UINT64 StoreLatency
:8;
123 } PAL_CACHE_INFO_RETURN1
;
126 // Detail the characteristics of a given processor controlled
127 // cache in the cache hierarchy.
131 UINT64 AliasBoundary
:8;
134 } PAL_CACHE_INFO_RETURN2
;
138 PAL Procedure - PAL_CACHE_INFO.
140 Return detailed instruction or data cache information. It is
141 required by IPF. The PAL procedure supports the Static
142 Registers calling convention. It could be called at virtual
143 mode and physical mode.
145 @param Index Index of PAL_CACHE_INFO within the list of
148 @param CacheLevel Unsigned 64-bit integer specifying the
149 level in the cache hierarchy for which
150 information is requested. This value must
151 be between 0 and one less than the value
152 returned in the cache_levels return value
153 from PAL_CACHE_SUMMARY.
155 @param CacheType Unsigned 64-bit integer with a value of 1
156 for instruction cache and 2 for data or
157 unified cache. All other values are
160 @param Reserved Should be 0.
163 @return R9 Detail the characteristics of a given
164 processor controlled cache in the cache
165 hierarchy. See PAL_CACHE_INFO_RETURN1.
167 @return R10 Detail the characteristics of a given
168 processor controlled cache in the cache
169 hierarchy. See PAL_CACHE_INFO_RETURN2.
171 @return R11 Reserved with 0.
174 @return Status 0 - Call completed without error
176 @return Status -2 - Invalid argument
178 @return Status -3 - Call completed with error
181 #define PAL_CACHE_INFO 2
186 // Level of PAL_CACHE_INIT.
188 #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL
191 // Restrict of PAL_CACHE_INIT.
193 #define PAL_CACHE_INIT_NO_RESTRICT 0
194 #define PAL_CACHE_INIT_RESTRICTED 1
198 PAL Procedure - PAL_CACHE_INIT.
200 Initialize the instruction or data caches. It is required by
201 IPF. The PAL procedure supports the Static Registers calling
202 convention. It could be called at physical mode.
204 @param Index Index of PAL_CACHE_INIT within the list of PAL
207 @param Level Unsigned 64-bit integer containing the level of
208 cache to initialize. If the cache level can be
209 initialized independently, only that level will
210 be initialized. Otherwise
211 implementation-dependent side-effects will
214 @param CacheType Unsigned 64-bit integer with a value of 1 to
215 initialize the instruction cache, 2 to
216 initialize the data cache, or 3 to
217 initialize both. All other values are
220 @param Restrict Unsigned 64-bit integer with a value of 0 or
221 1. All other values are reserved. If
222 restrict is 1 and initializing the specified
223 level and cache_type of the cache would
224 cause side-effects, PAL_CACHE_INIT will
225 return -4 instead of initializing the cache.
228 @return Status 0 - Call completed without error
230 @return Status -2 - Invalid argument
232 @return Status -3 - Call completed with error.
234 @return Status -4 - Call could not initialize the specified
235 level and cache_type of the cache without
236 side-effects and restrict was 1.
239 #define PAL_CACHE_INIT 3
243 // PAL_CACHE_PROTECTION.Method.
245 #define PAL_CACHE_PROTECTION_NONE_PROTECT 0
246 #define PAL_CACHE_PROTECTION_ODD_PROTECT 1
247 #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2
248 #define PAL_CACHE_PROTECTION_ECC_PROTECT 3
253 // PAL_CACHE_PROTECTION.TagOrData.
255 #define PAL_CACHE_PROTECTION_PROTECT_DATA 0
256 #define PAL_CACHE_PROTECTION_PROTECT_TAG 1
257 #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2
258 #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3
261 // 32-bit protection information structures.
270 } PAL_CACHE_PROTECTION
;
274 PAL Procedure - PAL_CACHE_PROT_INFO.
276 Return instruction or data cache protection information. It is
277 required by IPF. The PAL procedure supports the Static
278 Registers calling convention. It could be called at physical
279 mode and Virtual mode.
281 @param Index Index of PAL_CACHE_PROT_INFO within the list of
284 @param CacheLevel Unsigned 64-bit integer specifying the level
285 in the cache hierarchy for which information
286 is requested. This value must be between 0
287 and one less than the value returned in the
288 cache_levels return value from
291 @param CacheType Unsigned 64-bit integer with a value of 1
292 for instruction cache and 2 for data or
293 unified cache. All other values are
296 @return R9 Detail the characteristics of a given
297 processor controlled cache in the cache
298 hierarchy. See PAL_CACHE_PROTECTION[0..1].
300 @return R10 Detail the characteristics of a given
301 processor controlled cache in the cache
302 hierarchy. See PAL_CACHE_PROTECTION[2..3].
304 @return R11 Detail the characteristics of a given
305 processor controlled cache in the cache
306 hierarchy. See PAL_CACHE_PROTECTION[4..5].
309 @return Status 0 - Call completed without error
311 @return Status -2 - Invalid argument
313 @return Status -3 - Call completed with error.
316 #define PAL_CACHE_PROT_INFO 38
320 @param ThreadId The thread identifier of the logical
321 processor for which information is being
322 returned. This value will be unique on a per
325 @param CoreId The core identifier of the logical processor
326 for which information is being returned.
327 This value will be unique on a per physical
328 processor package basis.
332 UINT64 ThreadId
: 16;
333 UINT64 Reserved1
: 16;
335 UINT64 Reserved2
: 16;
336 } PAL_PCOC_N_CACHE_INFO1
;
340 @param LogicalAddress Logical address: geographical address
341 of the logical processor for which
342 information is being returned. This is
343 the same value that is returned by the
344 PAL_FIXED_ADDR procedure when it is
345 called on the logical processor.
349 UINT64 LogicalAddress
: 16;
350 UINT64 Reserved1
: 16;
351 UINT64 Reserved2
: 32;
352 } PAL_PCOC_N_CACHE_INFO2
;
356 PAL Procedure - PAL_CACHE_SHARED_INFO.
358 Returns information on which logical processors share caches.
359 It is optional. The PAL procedure supports the Static
360 Registers calling convention. It could be called at physical
361 mode and Virtual mode.
363 @param Index Index of PAL_CACHE_SHARED_INFO within the list
366 @param CacheLevel Unsigned 64-bit integer specifying the
367 level in the cache hierarchy for which
368 information is requested. This value must
369 be between 0 and one less than the value
370 returned in the cache_levels return value
371 from PAL_CACHE_SUMMARY.
373 @param CacheType Unsigned 64-bit integer with a value of 1
374 for instruction cache and 2 for data or
375 unified cache. All other values are
378 @param ProcNumber Unsigned 64-bit integer that specifies for
379 which logical processor information is
380 being requested. This input argument must
381 be zero for the first call to this
382 procedure and can be a maximum value of
383 one less than the number of logical
384 processors sharing this cache, which is
385 returned by the num_shared return value.
387 @return R9 Unsigned integer that returns the number of
388 logical processors that share the processor
389 cache level and type, for which information was
392 @return R10 The format of PAL_PCOC_N_CACHE_INFO1.
394 @return R11 The format of PAL_PCOC_N_CACHE_INFO2.
396 @return Status 0 - Call completed without error
398 @return Status -1 - Unimplemented procedure
400 @return Status -2 - Invalid argument
402 @return Status -3 - Call completed with error.
405 #define PAL_CACHE_SHARED_INFO 43
410 PAL Procedure - PAL_CACHE_SUMMARY.
412 Return a summary of the cache hierarchy. It is required by
413 IPF. The PAL procedure supports the Static Registers calling
414 convention. It could be called at physical mode and Virtual
417 @param Index Index of PAL_CACHE_SUMMARY within the list of
421 @return R9 CacheLevels Unsigned 64-bit integer denoting the
422 number of levels of cache
423 implemented by the processor.
424 Strictly, this is the number of
425 levels for which the cache
426 controller is integrated into the
427 processor (the cache SRAMs may be
428 external to the processor).
430 @return R10 UniqueCaches Unsigned 64-bit integer denoting the
431 number of unique caches implemented
432 by the processor. This has a maximum
433 of 2*cache_levels, but may be less
434 if any of the levels in the cache
435 hierarchy are unified caches or do
436 not have both instruction and data
439 @return Status 0 - Call completed without error
441 @return Status -2 - Invalid argument
443 @return Status -3 - Call completed with error.
446 #define PAL_CACHE_SUMMARY 4
450 // Virtual Memory Attributes implemented by processor.
452 #define PAL_MEMORY_ATTR_WB 0
453 #define PAL_MEMORY_ATTR_WC 6
454 #define PAL_MEMORY_ATTR_UC 4
455 #define PAL_MEMORY_ATTR_UCE 5
456 #define PAL_MEMORY_ATTR_NATPAGE 7
460 PAL Procedure - PAL_MEM_ATTRIB.
462 Return a list of supported memory attributes.. It is required
463 by IPF. The PAL procedure supports the Static Registers calling
464 convention. It could be called at physical mode and Virtual
467 @param Index Index of PAL_MEM_ATTRIB within the list of PAL
471 @return R9 Attributes 8-bit vector of memory attributes
472 implemented by processor. See Virtual
473 Memory Attributes above.
475 @return Status 0 - Call completed without error
477 @return Status -2 - Invalid argument
479 @return Status -3 - Call completed with error.
483 #define PAL_MEM_ATTRIB 5
487 PAL Procedure - PAL_PREFETCH_VISIBILITY.
489 Used in architected sequence to transition pages from a
490 cacheable, speculative attribute to an uncacheable attribute.
491 It is required by IPF. The PAL procedure supports the Static
492 Registers calling convention. It could be called at physical
493 mode and Virtual mode.
495 @param Index Index of PAL_PREFETCH_VISIBILITY within the list
498 @param TransitionType Unsigned integer specifying the type
499 of memory attribute transition that is
502 @return Status 1 Call completed without error; this
503 call is not necessary on remote
506 @return Status 0 - Call completed without error
508 @return Status -2 - Invalid argument
510 @return Status -3 - Call completed with error.
513 #define PAL_PREFETCH_VISIBILITY 41
517 PAL Procedure - PAL_PTCE_INFO.
519 Return information needed for ptc.e instruction to purge
520 entire TC. It is required by IPF. The PAL procedure supports
521 the Static Registers calling convention. It could be called at
522 physical mode and Virtual mode.
524 @param Index Index of PAL_PTCE_INFO within the list
527 @return R9 Unsigned 64-bit integer denoting the beginning
528 address to be used by the first PTCE instruction
531 @return R10 Two unsigned 32-bit integers denoting the loop
532 counts of the outer (loop 1) and inner (loop 2)
533 purge loops. count1 (loop 1) is contained in bits
534 63:32 of the parameter, and count2 (loop 2) is
535 contained in bits 31:0 of the parameter.
537 @return R11 Two unsigned 32-bit integers denoting the loop
538 strides of the outer (loop 1) and inner (loop 2)
539 purge loops. stride1 (loop 1) is contained in bits
540 63:32 of the parameter, and stride2 (loop 2) is
541 contained in bits 31:0 of the parameter.
543 @return Status 0 - Call completed without error
545 @return Status -2 - Invalid argument
547 @return Status -3 - Call completed with error.
550 #define PAL_PTCE_INFO 6
556 @param NumberSets Unsigned 8-bit integer denoting the number
557 of hash sets for the specified level
558 (1=fully associative)
560 @param NumberWays Unsigned 8-bit integer denoting the
561 associativity of the specified level
564 @param NumberEntries Unsigned 16-bit integer denoting the
565 number of entries in the specified TC.
568 @param PageSizeIsOptimized Flag denoting whether the
569 specified level is optimized for
570 the region's preferred page size
571 (1=optimized) tc_pages indicates
572 which page sizes are usable by
573 this translation cache.
575 @param TcIsUnified Flag denoting whether the specified TC is
578 @param EntriesReduction Flag denoting whether installed
579 translation registers will reduce
580 the number of entries within the
587 UINT64 NumberEntries
:16;
588 UINT64 PageSizeIsOptimized
:1;
589 UINT64 TcIsUnified
:1;
590 UINT64 EntriesReduction
:1;
595 PAL Procedure - PAL_VM_INFO.
597 Return detailed information about virtual memory features
598 supported in the processor. It is required by IPF. The PAL
599 procedure supports the Static Registers calling convention. It
600 could be called at physical mode and Virtual mode.
602 @param Index Index of PAL_VM_INFO within the list
605 @param TcLevel Unsigned 64-bit integer specifying the level
606 in the TLB hierarchy for which information is
607 required. This value must be between 0 and one
608 less than the value returned in the
609 vm_info_1.num_tc_levels return value from
612 @param TcType Unsigned 64-bit integer with a value of 1 for
613 instruction translation cache and 2 for data
614 or unified translation cache. All other values
617 @return R9 8-byte formatted value returning information
618 about the specified TC. See PAL_TC_INFO above.
620 @return R10 64-bit vector containing a bit for each page
621 size supported in the specified TC, where bit
622 position n indicates a page size of 2**n.
624 @return Status 0 - Call completed without error
626 @return Status -2 - Invalid argument
628 @return Status -3 - Call completed with error.
631 #define PAL_VM_INFO 7
636 PAL Procedure - PAL_VM_PAGE_SIZE.
638 Return virtual memory TC and hardware walker page sizes
639 supported in the processor. It is required by IPF. The PAL
640 procedure supports the Static Registers calling convention. It
641 could be called at physical mode and Virtual mode.
643 @param Index Index of PAL_VM_PAGE_SIZE within the list
647 @return R9 64-bit vector containing a bit for each
648 architected page size that is supported for
649 TLB insertions and region registers.
651 @return R10 64-bit vector containing a bit for each
652 architected page size supported for TLB purge
655 @return Status 0 - Call completed without error
657 @return Status -2 - Invalid argument
659 @return Status -3 - Call completed with error.
662 #define PAL_VM_PAGE_SIZE 34
666 @param WalkerPresent 1-bit flag indicating whether a hardware
667 TLB walker is implemented (1 = walker
670 @param WidthOfPhysicalAddress Unsigned 7-bit integer
671 denoting the number of bits of
672 physical address implemented.
674 @param WidthOfKey Unsigned 8-bit integer denoting the number
675 of bits mplemented in the PKR.key field.
677 @param MaxPkrIndex Unsigned 8-bit integer denoting the
678 maximum PKR index (number of PKRs-1).
680 @param HashTagId Unsigned 8-bit integer which uniquely
681 identifies the processor hash and tag
684 @param MaxDtrIndex Unsigned 8 bit integer denoting the
685 maximum data translation register index
686 (number of dtr entries - 1).
688 @param MaxItrIndex Unsigned 8 bit integer denoting the
689 maximum instruction translation register
690 index (number of itr entries - 1).
692 @param NumberOfUniqueTc Unsigned 8-bit integer denoting the
693 number of unique TCs implemented.
697 @param NumberOfTcLevels Unsigned 8-bit integer denoting the
702 UINT64 WalkerPresent
:1;
703 UINT64 WidthOfPhysicalAddress
: 7;
705 UINT64 MaxPkrIndex
:8;
707 UINT64 MaxDtrIndex
:8;
708 UINT64 MaxItrIndex
:8;
709 UINT64 NumberOfUniqueTc
:8;
710 UINT64 NumberOfTcLevels
:8;
715 @param WidthOfVirtualAddress Unsigned 8-bit integer denoting
716 is the total number of virtual
719 @param WidthOfRid Unsigned 8-bit integer denoting the number
720 of bits implemented in the RR.rid field.
722 @param MaxPurgedTlbs Unsigned 16 bit integer denoting the
723 maximum number of concurrent outstanding
724 TLB purges allowed by the processor. A
725 value of 0 indicates one outstanding
726 purge allowed. A value of 216-1
727 indicates no limit on outstanding
728 purges. All other values indicate the
729 actual number of concurrent outstanding
734 UINT64 WidthOfVirtualAddress
:8;
736 UINT64 MaxPurgedTlbs
:16;
742 PAL Procedure - PAL_VM_SUMMARY.
744 Return summary information about virtual memory features
745 supported in the processor. It is required by IPF. The PAL
746 procedure supports the Static Registers calling convention. It
747 could be called at physical mode and Virtual mode.
749 @param Index Index of PAL_VM_SUMMARY within the list
753 @return R9 8-byte formatted value returning global virtual
754 memory information. See PAL_VM_INFO1 above.
756 @return R10 8-byte formatted value returning global virtual
757 memory information. See PAL_VM_INFO2 above.
759 @return Status 0 - Call completed without error
761 @return Status -2 - Invalid argument
763 @return Status -3 - Call completed with error.
766 #define PAL_VM_SUMMARY 8
770 // Bit mask of TR_valid flag.
772 #define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0
773 #define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1
774 #define PAL_TR_DIRTY_IS_VALID BIT2
775 #define PAL_TR_MEMORY_ATTR_IS_VALID BIT3
780 PAL Procedure - PAL_VM_TR_READ.
782 Read contents of a translation register. It is required by
783 IPF. The PAL procedure supports the Stacked Register calling
784 convention. It could be called at physical mode.
786 @param Index Index of PAL_VM_TR_READ within the list
789 @param RegNumber Unsigned 64-bit number denoting which TR to
792 @param TrType Unsigned 64-bit number denoting whether to
793 read an ITR (0) or DTR (1). All other values
796 @param TrBuffer 64-bit pointer to the 32-byte memory buffer in
797 which translation data is returned.
799 @return R9 Formatted bit vector denoting which fields are
800 valid. See TR_valid above.
802 @return Status 0 - Call completed without error
804 @return Status -2 - Invalid argument
806 @return Status -3 - Call completed with error.
809 #define PAL_VM_TR_READ 261
815 // Bit Mask of Processor Bus Fesatures .
820 When 0, bus data errors are detected and single bit errors are
821 corrected. When 1, no error detection or correction is done.
824 #define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63
829 When 0, bus address errors are signalled on the bus. When 1,
830 no bus errors are signalled on the bus. If Disable Bus Address
831 Error Checking is 1, this bit is ignored.
834 #define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62
841 When 0, bus errors are detected, single bit errors are
842 corrected., and a CMCI or MCA is generated internally to the
843 processor. When 1, no bus address errors are detected or
847 #define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61
852 When 0, bus protocol errors (BINIT#) are signaled by the
853 processor on the bus. When 1, bus protocol errors (BINIT#) are
854 not signaled on the bus. If Disable Bus Initialization Event
855 Checking is 1, this bit is ignored.
858 #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60
863 When 0, bus protocol errors (BINIT#) are detected and sampled
864 and an MCA is generated internally to the processor. When 1,
865 the processor will ignore bus protocol error conditions
869 #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59
875 When 0, BERR# is signalled if a bus error is detected. When 1,
876 bus errors are not signalled on the bus.
879 #define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58
886 When 0, BERR# is signalled when internal processor requestor
887 initiated bus errors are detected. When 1, internal requester
888 bus errors are not signalled on the bus.
891 #define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57
896 When 0, the processor takes an MCA if BERR# is asserted. When
897 1, the processor ignores the BERR# signal.
900 #define PAL_BUS_DISABLE_ERROR_CHECK BIT56
905 When 0, the processor asserts BINIT# if it detects a parity
906 error on the signals which identify the transactions to which
907 this is a response. When 1, the processor ignores parity on
911 #define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55
916 When 0, the in-order transaction queue is limited only by the
917 number of hardware entries. When 1, the processor's in-order
918 transactions queue is limited to one entry.
921 #define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54
925 Enable a bus cache line replacement transaction when a cache
926 line in the exclusive state is replaced from the highest level
927 processor cache and is not present in the lower level processor
928 caches. When 0, no bus cache line replacement transaction will
929 be seen on the bus. When 1, bus cache line replacement
930 transactions will be seen on the bus when the above condition is
934 #define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53
939 Enable a bus cache line replacement transaction when a cache
940 line in the shared or exclusive state is replaced from the
941 highest level processor cache and is not present in the lower
942 level processor caches.
943 When 0, no bus cache line replacement transaction will be seen
944 on the bus. When 1, bus cache line replacement transactions
945 will be seen on the bus when the above condition is detected.
948 #define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52
954 When 0, the data bus is configured at the 2x data transfer
955 rate.When 1, the data bus is configured at the 1x data
956 transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the
957 processor executes locked transactions atomically. When 1, the
958 processor masks the bus lock signal and executes locked
959 transactions as a non-atomic series of transactions.
962 #define PAL_BUS_ENABLE_HALF_TRANSFER BIT30
966 When 0, the processor will deassert bus request when finished
967 with each transaction. When 1, the processor will continue to
968 assert bus request after it has finished, if it was the last
969 agent to own the bus and if there are no other pending
973 #define PAL_BUS_REQUEST_BUS_PARKING BIT29
978 PAL Procedure - PAL_BUS_GET_FEATURES.
980 Return configurable processor bus interface features and their
981 current settings. It is required by IPF. The PAL procedure
982 supports the Stacked Register calling convention. It could be
983 called at physical mode.
985 @param Index Index of PAL_BUS_GET_FEATURES within the list
988 @return R9 64-bit vector of features implemented.
989 (1=implemented, 0=not implemented)
991 @return R10 64-bit vector of current feature settings.
993 @return R11 64-bit vector of features controllable by
994 software. (1=controllable, 0= not controllable)
996 @return Status 0 - Call completed without error
998 @return Status -2 - Invalid argument
1000 @return Status -3 - Call completed with error.
1003 #define PAL_BUS_GET_FEATURES 9
1007 PAL Procedure - PAL_BUS_SET_FEATURES.
1009 Enable or disable configurable features in processor bus
1010 interface. It is required by IPF. It is required by IPF. The PAL procedure
1011 supports the Static Registers calling convention. It could be
1012 called at physical mode.
1014 @param Index Index of PAL_BUS_SET_FEATURES within the list
1017 @param FeatureSelect 64-bit vector denoting desired state of
1018 each feature (1=select, 0=non-select).
1020 @return Status 0 - Call completed without error
1022 @return Status -2 - Invalid argument
1024 @return Status -3 - Call completed with error.
1027 #define PAL_BUS_SET_FEATURES 10
1032 PAL Procedure - PAL_DEBUG_INFO.
1034 Return the number of instruction and data breakpoint
1035 registers. It is required by IPF. It is required by IPF. The
1036 PAL procedure supports the Static Registers calling
1037 convention. It could be called at physical mode and virtual
1040 @param Index Index of PAL_DEBUG_INFO within the list of PAL
1043 @return R9 Unsigned 64-bit integer denoting the number of
1044 pairs of instruction debug registers implemented
1047 @return R10 Unsigned 64-bit integer denoting the number of
1048 pairs of data debug registers implemented by the
1051 @return Status 0 - Call completed without error
1053 @return Status -2 - Invalid argument
1055 @return Status -3 - Call completed with error.
1058 #define PAL_DEBUG_INFO 11
1062 PAL Procedure - PAL_FIXED_ADDR.
1064 Return the fixed component of a processor¡¯s directed address.
1065 It is required by IPF. It is required by IPF. The PAL
1066 procedure supports the Static Registers calling convention. It
1067 could be called at physical mode and virtual mode.
1069 @param Index Index of PAL_FIXED_ADDR within the list of PAL
1072 @return R9 Fixed geographical address of this processor.
1075 @return Status 0 - Call completed without error
1077 @return Status -2 - Invalid argument
1079 @return Status -3 - Call completed with error.
1082 #define PAL_FIXED_ADDR 12
1086 PAL Procedure - PAL_FREQ_BASE.
1088 Return the frequency of the output clock for use by the
1089 platform, if generated by the processor. It is optinal. The
1090 PAL procedure supports the Static Registers calling
1091 convention. It could be called at physical mode and virtual
1094 @param Index Index of PAL_FREQ_BASE within the list of PAL
1097 @return R9 Base frequency of the platform if generated by the
1101 @return Status 0 - Call completed without error
1103 @return Status -1 - Unimplemented procedure
1105 @return Status -2 - Invalid argument
1107 @return Status -3 - Call completed with error.
1110 #define PAL_FREQ_BASE 13
1115 PAL Procedure - PAL_FREQ_RATIOS.
1117 Return ratio of processor, bus, and interval time counter to
1118 processor input clock or output clock for platform use, if
1119 generated by the processor. It is required by IPF. The PAL
1120 procedure supports the Static Registers calling convention. It
1121 could be called at physical mode and virtual mode.
1123 @param Index Index of PAL_FREQ_RATIOS within the list of PAL
1126 @return R9 Ratio of the processor frequency to the input
1127 clock of the processor, if the platform clock is
1128 generated externally or to the output clock to the
1129 platform, if the platform clock is generated by
1132 @return R10 Ratio of the bus frequency to the input clock of
1133 the processor, if the platform clock is generated
1134 externally or to the output clock to the platform,
1135 if the platform clock is generated by the
1138 @return R11 Ratio of the interval timer counter rate to input
1139 clock of the processor, if the platform clock is
1140 generated externally or to the output clock to the
1141 platform, if the platform clock is generated by
1144 @return Status 0 - Call completed without error
1146 @return Status -2 - Invalid argument
1148 @return Status -3 - Call completed with error.
1151 #define PAL_FREQ_RATIOS 14
1155 @param NumberOfLogicalProcessors Total number of logical
1156 processors on this physical
1157 processor package that are
1160 @param ThreadsPerCore Number of threads per core.
1162 @param CoresPerProcessor Total number of cores on this
1163 physical processor package.
1165 @param PhysicalProcessorPackageId Physical processor package
1166 identifier which was
1167 assigned at reset by the
1169 controller. This value may
1170 or may not be unique
1171 across the entire platform
1172 since it depends on the
1173 platform vendor's policy.
1176 UINT64 NumberOfLogicalProcessors
:16;
1177 UINT64 ThreadsPerCore
:8;
1179 UINT64 CoresPerProcessor
;
1181 UINT64 PhysicalProcessorPackageId
:8;
1183 } PAL_LOGICAL_PROCESSPR_OVERVIEW
;
1187 @param ThreadId The thread identifier of the logical
1188 processor for which information is being
1189 returned. This value will be unique on a per
1192 @param CoreId The core identifier of the logical processor
1193 for which information is being returned.
1194 This value will be unique on a per physical
1195 processor package basis.
1200 UINT64 Reserved1
:16;
1202 UINT64 Reserved2
:16;
1203 } PAL_LOGICAL_PROCESSORN_INFO1
;
1208 @param LogicalAddress Geographical address of the logical
1209 processor for which information is being
1210 returned. This is the same value that is
1211 returned by the PAL_FIXED_ADDR procedure
1212 when it is called on the logical
1218 UINT64 LogicalAddress
:16;
1220 } PAL_LOGICAL_PROCESSORN_INFO2
;
1224 PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.
1226 Return information on which logical processors map to a
1227 physical processor die. It is optinal. The PAL procedure
1228 supports the Static Registers calling convention. It could be
1229 called at physical mode and virtual mode.
1231 @param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL
1234 @param ProcessorNumber Signed 64-bit integer that specifies
1235 for which logical processor
1236 information is being requested. When
1237 this input argument is -1, information
1238 is returned about the logical
1239 processor on which the procedure call
1240 is made. This input argument must be
1241 in the range of 1 up to one less than
1242 the number of logical processors
1243 returned by num_log in the
1244 log_overview return value.
1247 @return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.
1249 @return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.
1251 @return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.
1254 @return Status 0 - Call completed without error
1256 @return Status -1 - Unimplemented procedure
1258 @return Status -2 - Invalid argument
1260 @return Status -3 - Call completed with error.
1263 #define PAL_LOGICAL_TO_PHYSICAL 42
1268 @param NumberOfPmcPairs Unsigned 8-bit number defining the
1269 number of generic PMC/PMD pairs.
1271 @param WidthOfCounter Unsigned 8-bit number in the range
1272 0:60 defining the number of
1273 implemented counter bits.
1275 @param TypeOfCycleCounting Unsigned 8-bit number defining the
1276 event type for counting processor
1280 @param TypeOfRetiredInstructionBundle Retired Unsigned 8-bit
1282 event type for retired
1283 instruction bundles.
1287 UINT64 NumberOfPmcPairs
:8;
1288 UINT64 WidthOfCounter
:8;
1289 UINT64 TypeOfCycleCounting
:8;
1290 UINT64 TypeOfRetiredInstructionBundle
:8;
1292 } PAL_PERFORMANCE_INFO
;
1296 PAL Procedure - PAL_PERF_MON_INFO.
1298 Return the number and type of performance monitors. It is
1299 required by IPF. The PAL procedure supports the Static
1300 Registers calling convention. It could be called at physical
1301 mode and virtual mode.
1303 @param Index Index of PAL_PERF_MON_INFO within the list of
1306 @param PerformanceBuffer An address to an 8-byte aligned
1307 128-byte memory buffer.
1310 @return R9 Information about the performance monitors
1311 implemented. See PAL_PERFORMANCE_INFO;
1313 @return Status 0 - Call completed without error
1315 @return Status -2 - Invalid argument
1317 @return Status -3 - Call completed with error.
1320 #define PAL_PERF_MON_INFO 15
1324 PAL Procedure - PAL_PLATFORM_ADDR.
1326 Specify processor interrupt block address and I/O port space
1327 address. It is required by IPF. The PAL procedure supports the
1328 Static Registers calling convention. It could be called at
1329 physical mode and virtual mode.
1331 @param Index Index of PAL_PLATFORM_ADDR within the list of
1334 @param Type Unsigned 64-bit integer specifying the type of
1335 block. 0 indicates that the processor interrupt
1336 block pointer should be initialized. 1 indicates
1337 that the processor I/O block pointer should be
1340 @param Address Unsigned 64-bit integer specifying the address
1341 to which the processor I/O block or interrupt
1342 block shall be set. The address must specify
1343 an implemented physical address on the
1344 processor model, bit 63 is ignored.
1347 @return Status 0 - Call completed without error
1349 @return Status -1 - Unimplemented procedure.
1351 @return Status -2 - Invalid argument
1353 @return Status -3 - Call completed with error.
1356 #define PAL_PLATFORM_ADDR 16
1361 @param EnableBerrPromotion Bit63. Enable BERR promotion. When
1362 1, the Bus Error (BERR) signal is
1363 promoted to the Bus Initialization
1364 (BINIT) signal, and the BINIT pin
1365 is asserted on the occurrence of
1366 each Bus Error. Setting this bit
1367 has no effect if BINIT signalling
1369 PAL_BUS_GET/SET_FEATURES)
1371 @param EnableMcaPromotion Bit62, Enable MCA promotion. When
1372 1, machine check aborts (MCAs) are
1373 promoted to the Bus Error signal,
1374 and the BERR pin is assert on each
1375 occurrence of an MCA. Setting this
1376 bit has no effect if BERR
1377 signalling is disabled. (See
1378 PAL_BUS_GET/SET_FEATURES)
1380 @param EnableMcaToBinitPromotion Bit61, Enable MCA to BINIT
1381 promotion. When 1, machine
1382 check aborts (MCAs) are
1384 Initialization signal, and
1385 the BINIT pin is assert on
1386 each occurrence of an MCA.
1387 Setting this bit has no
1388 effect if BINIT signalling
1390 PAL_BUS_GET/SET_FEATURES)
1392 @param EnableCmciPromotion Bit60, Enable CMCI promotion When
1393 1, Corrected Machine Check
1394 Interrupts (CMCI) are promoted to
1395 MCAs. They are also further
1396 promoted to BERR if bit 39, Enable
1397 MCA promotion, is also set and
1398 they are promoted to BINIT if bit
1399 38, Enable MCA to BINIT promotion,
1400 is also set. This bit has no
1401 effect if MCA signalling is
1403 PAL_BUS_GET/SET_FEATURES)
1405 @param DisableCache Bit59, Disable Cache. When 0, the
1406 processor performs cast outs on
1407 cacheable pages and issues and responds
1408 to coherency requests normally. When 1,
1409 the processor performs a memory access
1410 for each reference regardless of cache
1411 contents and issues no coherence
1412 requests and responds as if the line
1413 were not present. Cache contents cannot
1414 be relied upon when the cache is
1415 disabled. WARNING: Semaphore
1416 instructions may not be atomic or may
1417 cause Unsupported Data Reference faults
1418 if caches are disabled.
1420 @param DisableCoherency Bit58, Disable Coherency. When 0,
1421 the processor uses normal coherency
1422 requests and responses. When 1, the
1423 processor answers all requests as if
1424 the line were not present.
1426 @param DisableDPM Bit57, Disable Dynamic Power Management
1427 (DPM). When 0, the hardware may reduce
1428 power consumption by removing the clock
1429 input from idle functional units. When 1,
1430 all functional units will receive clock
1431 input, even when idle.
1433 @param DisableBinitWithTimeout Bit56, Disable a BINIT on
1434 internal processor time-out.
1435 When 0, the processor may
1436 generate a BINIT on an
1437 internal processor time-out.
1438 When 1, the processor will not
1439 generate a BINIT on an
1440 internal processor time-out.
1441 The event is silently ignored.
1444 @param EnableEnvNotification Bit55, Enable external
1445 notification when the processor
1446 detects hardware errors caused
1447 by environmental factors that
1449 deterministic behavior of the
1450 processor. When 1, this bit will
1451 enable external notification,
1452 when 0 external notification is
1453 not provided. The type of
1454 external notification of these
1455 errors is processor-dependent. A
1456 loss of processor deterministic
1457 behavior is considered to have
1459 environmentally induced errors
1460 cause the processor to deviate
1461 from its normal execution and
1462 eventually causes different
1463 behavior which can be observed
1464 at the processor bus pins.
1465 Processor errors that do not
1466 have this effects (i.e.,
1467 software induced machine checks)
1468 may or may not be promoted
1469 depending on the processor
1472 @param EnableVmsw Bit54, Enable the use of the vmsw
1473 instruction. When 0, the vmsw instruction
1474 causes a Virtualization fault when
1475 executed at the most privileged level.
1476 When 1, this bit will enable normal
1477 operation of the vmsw instruction.
1479 @param EnableMcaOnDataPoisoning Bit53, Enable MCA signaling
1480 on data-poisoning event
1481 detection. When 0, a CMCI
1482 will be signaled on error
1483 detection. When 1, an MCA
1484 will be signaled on error
1485 detection. If this feature
1486 is not supported, then the
1487 corresponding argument is
1488 ignored when calling
1489 PAL_PROC_SET_FEATURES. Note
1490 that the functionality of
1491 this bit is independent of
1492 the setting in bit 60
1493 (Enable CMCI promotion), and
1494 that the bit 60 setting does
1495 not affect CMCI signaling
1496 for data-poisoning related
1497 events. Volume 2: Processor
1498 Abstraction Layer 2:431
1499 PAL_PROC_GET_FEATURES
1501 @param DisablePState Bit52, Disable P-states. When 1, the PAL
1502 P-state procedures (PAL_PSTATE_INFO,
1503 PAL_SET_PSTATE, PAL_GET_PSTATE) will
1504 return with a status of -1
1505 (Unimplemented procedure).
1507 @param DisableBranchPrediction Bit47, Disable Dynamic branch
1508 prediction. When 0, the
1509 processor may predict branch
1510 targets and speculatively
1511 execute, but may not commit
1512 results. When 1, the processor
1513 must wait until branch targets
1514 are known to execute.
1516 @param DisableDynamicInsCachePrefetch Bit46, Disable
1517 DynamicInstruction Cache
1518 Prefetch. When 0, the
1519 processor may prefetch
1521 instruction which has
1522 not been executed, but
1525 instructions may not be
1526 fetched until needed or
1527 hinted for execution.
1528 (Prefetch for a hinted
1529 branch is allowed even
1530 when dynamic instruction
1534 @param DisableDynamicDataCachePrefetch Bit45, Disable Dynamic
1535 Data Cache Prefetch.
1536 When 0, the processor
1537 may prefetch into the
1538 caches any data which
1539 has not been accessed
1541 execution, but which
1543 accessed. When 1, no
1545 until it is needed for
1546 instruction execution
1550 @param DisableSpontaneousDeferral Bit44, Disable Spontaneous
1551 Deferral. When 1, the
1552 processor may optionally
1553 defer speculative loads
1554 that do not encounter any
1555 exception conditions, but
1557 implementation-dependent
1558 conditions (e.g., cache
1559 miss). When 0, spontaneous
1560 deferral is disabled.
1562 @param DisableDynamicPrediction Bit43, Disable Dynamic
1563 Predicate Prediction. When
1564 0, the processor may predict
1565 predicate results and
1566 execute speculatively, but
1567 may not commit results until
1568 the actual predicates are
1569 known. When 1, the processor
1570 shall not execute predicated
1571 instructions until the
1572 actual predicates are known.
1574 @param NoXr1ThroughXr3 Bit42, No XR1 through XR3 implemented.
1575 Denotes whether XR1 XR3 are
1576 implemented for machine check
1577 recovery. This feature may only be
1578 interrogated by PAL_PROC_GET_FEATURES.
1579 It may not be enabled or disabled by
1580 PAL_PROC_SET_FEATURES. The
1581 corresponding argument is ignored.
1583 @param NoXipXpsrXfs Bit41, No XIP, XPSR, and XFS
1584 implemented. Denotes whether XIP, XPSR,
1585 and XFS are implemented for machine
1586 check recovery. This feature may only be
1587 interrogated by PAL_PROC_GET_FEATURES.
1588 It may not be enabled or disabled by
1589 PAL_PROC_SET_FEATURES. The corresponding
1590 argument is ignored.
1592 @param NoVM Bit40, No Virtual Machine features implemented.
1593 Denotes whether PSR.vm is implemented. This
1594 feature may only be interrogated by
1595 PAL_PROC_GET_FEATURES. It may not be enabled or
1596 disabled by PAL_PROC_SET_FEATURES. The
1597 corresponding argument is ignored.
1599 @param NoVariablePState Bit39, No Variable P-state
1600 performance: A value of 1, indicates
1601 that a processor implements
1602 techniques to optimize performance
1603 for the given P-state power budget
1604 by dynamically varying the
1605 frequency, such that maximum
1606 performance is achieved for the
1607 power budget. A value of 0,
1608 indicates that P-states have no
1609 frequency variation or very small
1610 frequency variations for their given
1611 power budget. This feature may only
1613 PAL_PROC_GET_FEATURES. it may not be
1614 enabled or disabled by
1615 PAL_PROC_SET_FEATURES. The
1616 corresponding argument is ignored.
1619 @param NoSimpleImpInUndefinedIns Bit38, No Simple
1621 unimplemented instruction
1622 addresses. Denotes how an
1623 unimplemented instruction
1624 address is recorded in IIP
1626 Instruction Address trap or
1627 fault. When 1, the full
1628 unimplemented address is
1629 recorded in IIP; when 0, the
1630 address is sign extended
1631 (virtual addresses) or zero
1633 addresses). This feature may
1634 only be interrogated by
1635 PAL_PROC_GET_FEATURES. It
1636 may not be enabled or
1638 PAL_PROC_SET_FEATURES. The
1639 corresponding argument is
1642 @param NoPresentPmi Bit37, No INIT, PMI, and LINT pins
1643 present. Denotes the absence of INIT,
1644 PMI, LINT0 and LINT1 pins on the
1645 processor. When 1, the pins are absent.
1646 When 0, the pins are present. This
1647 feature may only be interrogated by
1648 PAL_PROC_GET_FEATURES. It may not be
1649 enabled or disabled by
1650 PAL_PROC_SET_FEATURES. The corresponding
1651 argument is ignored.
1653 @param FaultInUndefinedIns Bit36, No Unimplemented
1654 instruction address reported as
1655 fault. Denotes how the processor
1656 reports the detection of
1657 unimplemented instruction
1658 addresses. When 1, the processor
1659 reports an Unimplemented
1660 Instruction Address fault on the
1661 unimplemented address; when 0, it
1662 reports an Unimplemented
1663 Instruction Address trap on the
1664 previous instruction in program
1665 order. This feature may only be
1667 PAL_PROC_GET_FEATURES. It may not
1668 be enabled or disabled by
1669 PAL_PROC_SET_FEATURES. The
1670 corresponding argument is
1675 UINT64 Reserved1
:36;
1676 UINT64 FaultInUndefinedIns
:1;
1677 UINT64 NoPresentPmi
:1;
1678 UINT64 NoSimpleImpInUndefinedIns
:1;
1679 UINT64 NoVariablePState
:1;
1681 UINT64 NoXipXpsrXfs
:1;
1682 UINT64 NoXr1ThroughXr3
:1;
1683 UINT64 DisableDynamicPrediction
:1;
1684 UINT64 DisableSpontaneousDeferral
:1;
1685 UINT64 DisableDynamicDataCachePrefetch
:1;
1686 UINT64 DisableDynamicInsCachePrefetch
:1;
1687 UINT64 DisableBranchPrediction
:1;
1689 UINT64 DisablePState
:1;
1690 UINT64 EnableMcaOnDataPoisoning
:1;
1691 UINT64 EnableVmsw
:1;
1692 UINT64 EnableEnvNotification
:1;
1693 UINT64 DisableBinitWithTimeout
:1;
1694 UINT64 DisableDPM
:1;
1695 UINT64 DisableCoherency
:1;
1696 UINT64 DisableCache
:1;
1697 UINT64 EnableCmciPromotion
:1;
1698 UINT64 EnableMcaToBinitPromotion
:1;
1699 UINT64 EnableMcaPromotion
:1;
1700 UINT64 EnableBerrPromotion
:1;
1701 } PAL_PROCESSOR_FEATURES
;
1705 PAL Procedure - PAL_PROC_GET_FEATURES.
1707 Return configurable processor features and their current
1708 setting. It is required by IPF. The PAL procedure supports the
1709 Static Registers calling convention. It could be called at
1710 physical mode and virtual mode.
1712 @param Index Index of PAL_PROC_GET_FEATURES within the list of
1715 @param Reserved Reserved parameter.
1717 @param FeatureSet Feature set information is being requested
1721 @return R9 64-bit vector of features implemented. See
1722 PAL_PROCESSOR_FEATURES.
1724 @return R10 64-bit vector of current feature settings. See
1725 PAL_PROCESSOR_FEATURES.
1727 @return R11 64-bit vector of features controllable by
1730 @return Status 1 - Call completed without error; The
1731 feature_set passed is not supported but a
1732 feature_set of a larger value is supported.
1734 @return Status 0 - Call completed without error
1736 @return Status -2 - Invalid argument
1738 @return Status -3 - Call completed with error.
1740 @return Status -8 - feature_set passed is beyond the maximum
1741 feature_set supported
1744 #define PAL_PROC_GET_FEATURES 17
1749 PAL Procedure - PAL_PROC_SET_FEATURES.
1751 Enable or disable configurable processor features. It is
1752 required by IPF. The PAL procedure supports the Static
1753 Registers calling convention. It could be called at physical
1756 @param Index Index of PAL_PROC_SET_FEATURES within the list of
1759 @param FeatureSelect 64-bit vector denoting desired state of
1760 each feature (1=select, 0=non-select).
1762 @param FeatureSet Feature set to apply changes to. See
1763 PAL_PROC_GET_FEATURES for more information
1768 @return Status 1 - Call completed without error; The
1769 feature_set passed is not supported but a
1770 feature_set of a larger value is supported
1772 @return Status 0 - Call completed without error
1774 @return Status -2 - Invalid argument
1776 @return Status -3 - Call completed with error.
1778 @return Status -8 - feature_set passed is beyond the maximum
1779 feature_set supported
1782 #define PAL_PROC_SET_FEATURES 18
1786 // Value of PAL_REGISTER_INFO.InfoRequest.
1788 #define PAL_APPLICATION_REGISTER_IMPLEMENTED 0
1789 #define PAL_APPLICATION_REGISTER_READABLE 1
1790 #define PAL_CONTROL_REGISTER_IMPLEMENTED 2
1791 #define PAL_CONTROL_REGISTER_READABLE 3
1796 PAL Procedure - PAL_REGISTER_INFO.
1798 Return AR and CR register information. It is required by IPF.
1799 The PAL procedure supports the Static Registers calling
1800 convention. It could be called at physical mode and virtual
1803 @param Index Index of PAL_REGISTER_INFO within the list of
1806 @param InfoRequest Unsigned 64-bit integer denoting what
1807 register information is requested. See
1808 PAL_REGISTER_INFO.InfoRequest above.
1810 @return R9 64-bit vector denoting information for registers
1811 0-63. Bit 0 is register 0, bit 63 is register 63.
1813 @return R10 64-bit vector denoting information for registers
1814 64-127. Bit 0 is register 64, bit 63 is register
1818 @return Status 0 - Call completed without error
1820 @return Status -2 - Invalid argument
1822 @return Status -3 - Call completed with error.
1826 #define PAL_REGISTER_INFO 39
1830 PAL Procedure - PAL_RSE_INFO.
1832 Return RSE information. It is required by IPF. The PAL
1833 procedure supports the Static Registers calling convention. It
1834 could be called at physical mode and virtual mode.
1836 @param Index Index of PAL_RSE_INFO within the list of
1839 @param InfoRequest Unsigned 64-bit integer denoting what
1840 register information is requested. See
1841 PAL_REGISTER_INFO.InfoRequest above.
1843 @return R9 Number of physical stacked general registers.
1845 @return R10 RSE hints supported by processor.
1847 @return Status 0 - Call completed without error
1849 @return Status -2 - Invalid argument
1851 @return Status -3 - Call completed with error.
1855 #define PAL_RSE_INFO 19
1859 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
1860 number that provides identification
1861 information about the PAL_B firmware.
1863 @param PalVendor Is an unsigned 8-bit integer indicating the
1864 vendor of the PAL code.
1866 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)
1867 number that provides identification
1868 information about the PAL_A firmware. In
1869 the split PAL_A model, this return value
1870 is the version number of the
1871 processor-specific PAL_A. The generic
1872 PAL_A version is not returned by this
1873 procedure in the split PAL_A model.
1877 UINT64 VersionOfPalB
:16;
1880 UINT64 VersionOfPalA
:16;
1881 UINT64 Reserved2
:16;
1886 PAL Procedure - PAL_VERSION.
1888 Return version of PAL code. It is required by IPF. The PAL
1889 procedure supports the Static Registers calling convention. It
1890 could be called at physical mode and virtual mode.
1892 @param Index Index of PAL_VERSION within the list of
1895 @param InfoRequest Unsigned 64-bit integer denoting what
1896 register information is requested. See
1897 PAL_REGISTER_INFO.InfoRequest above.
1899 @return R9 8-byte formatted value returning the minimum PAL
1900 version needed for proper operation of the
1901 processor. See PAL_VERSION_INFO above.
1903 @return R10 8-byte formatted value returning the current PAL
1904 version running on the processor. See
1905 PAL_VERSION_INFO above.
1907 @return Status 0 - Call completed without error
1909 @return Status -2 - Invalid argument
1911 @return Status -3 - Call completed with error.
1915 #define PAL_VERSION 20
1920 // Vectors of PAL_MC_CLEAR_LOG.pending
1922 #define PAL_MC_PENDING BIT0
1923 #define PAL_INIT_PENDING BIT1
1927 PAL Procedure - PAL_MC_CLEAR_LOG.
1929 Clear all error information from processor error logging
1930 registers. It is required by IPF. The PAL procedure supports
1931 the Static Registers calling convention. It could be called at
1932 physical mode and virtual mode.
1934 @param Index Index of PAL_MC_CLEAR_LOG within the list of
1938 @return R9 64-bit vector denoting whether an event is
1939 pending. See PAL_MC_CLEAR_LOG.pending above.
1942 @return Status 0 - Call completed without error
1944 @return Status -2 - Invalid argument
1946 @return Status -3 - Call completed with error.
1950 #define PAL_MC_CLEAR_LOG 21
1954 PAL Procedure - PAL_MC_DRAIN.
1956 Ensure that all operations that could cause an MCA have
1957 completed. It is required by IPF. The PAL procedure supports
1958 the Static Registers calling convention. It could be called at
1959 physical mode and virtual mode.
1961 @param Index Index of PAL_MC_DRAIN within the list of PAL
1965 @return Status 0 - Call completed without error
1967 @return Status -2 - Invalid argument
1969 @return Status -3 - Call completed with error.
1973 #define PAL_MC_DRAIN 22
1978 PAL Procedure - PAL_MC_DYNAMIC_STATE.
1980 Return Processor Dynamic State for logging by SAL. It is
1981 optional. The PAL procedure supports the Static Registers
1982 calling convention. It could be called at physical mode.
1984 @param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL
1987 @param Offset Offset of the next 8 bytes of Dynamic Processor
1988 State to return. (multiple of 8).
1990 @return R9 Unsigned 64-bit integer denoting bytes of Dynamic
1991 Processor State returned.
1993 @return R10 Next 8 bytes of Dynamic Processor State.
1995 @return Status 0 - Call completed without error
1997 @return Status -1 - Unimplemented procedure.
1999 @return Status -2 - Invalid argument
2001 @return Status -3 - Call completed with error.
2005 #define PAL_MC_DYNAMIC_STATE 24
2010 // Values of PAL_MC_ERROR_INFO.InfoIndex.
2012 #define PAL_PROCESSOR_ERROR_MAP 0
2013 #define PAL_PROCESSOR_STATE_PARAM 1
2014 #define PAL_STRUCTURE_SPECIFIC_ERROR 2
2018 @param CoreId Bit3:0, Processor core ID (default is 0 for
2019 processors with a single core)
2021 @param ThreadId Bit7:4, Logical thread ID (default is 0 for
2022 processors that execute a single thread)
2024 @param InfoOfInsCache Bit11:8, Error information is
2025 available for 1st, 2nd, 3rd, and 4th
2026 level instruction caches.
2028 @param InfoOfDataCache Bit15:12, Error information is
2029 available for 1st, 2nd, 3rd, and 4th
2030 level data/unified caches.
2032 @param InfoOfInsTlb Bit19:16 Error information is available
2033 for 1st, 2nd, 3rd, and 4th level
2036 @param InfoOfDataTlb Bit23:20, Error information is available
2037 for 1st, 2nd, 3rd, and 4th level
2040 @param InfoOfProcessorBus Bit27:24 Error information is
2041 available for the 1st, 2nd, 3rd,
2042 and 4th level processor bus
2045 @param InfoOfRegisterFile Bit31:28 Error information is
2046 available on register file
2049 @param InfoOfMicroArch Bit47:32, Error information is
2050 available on micro-architectural
2057 UINT64 InfoOfInsCache
:4;
2058 UINT64 InfoOfDataCache
:4;
2059 UINT64 InfoOfInsTlb
:4;
2060 UINT64 InfoOfDataTlb
:4;
2061 UINT64 InfoOfProcessorBus
:4;
2062 UINT64 InfoOfRegisterFile
:4;
2063 UINT64 InfoOfMicroArch
:4;
2065 } PAL_MC_ERROR_INFO_LEVEL_INDEX
;
2068 // Value of PAL_MC_ERROR_INFO.ErrorTypeIndex
2070 #define PAL_ERR_INFO_BY_LEVEL_INDEX 0
2071 #define PAL_ERR_INFO_TARGET_ADDRESS 1
2072 #define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2
2073 #define PAL_ERR_INFO_REPONSER_INDENTIFIER 3
2074 #define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4
2078 @param Operation Bit3:0, Type of cache operation that caused
2079 the machine check: 0 - unknown or internal
2080 error 1 - load 2 - store 3 - instruction
2081 fetch or instruction prefetch 4 - data
2082 prefetch (both hardware and software) 5 -
2083 snoop (coherency check) 6 - cast out
2084 (explicit or implicit write-back of a cache
2085 line) 7 - move in (cache line fill)
2087 @param FailedCacheLevel Bit5:4 Level of cache where the
2088 error occurred. A value of 0
2089 indicates the first level of cache.
2091 @param FailedInDataPart Bit8, Failure located in the data
2092 part of the cache line.
2094 @param FailedInTagPart Bit9, Failure located in the tag part
2097 @param FailedInDataCache Bit10, Failure located in the data
2100 @param FailedInInsCache Bit11, Failure located in the
2104 @param Mesi Bit14:12, 0 - cache line is invalid. 1 - cache
2105 line is held shared. 2 - cache line is held
2106 exclusive. 3 - cache line is modified. All other
2107 values are reserved.
2109 @param MesiIsValid Bit15, The mesi field in the cache_check
2112 @param FailedWay Bit20:16, Failure located in the way of
2113 the cache indicated by this value.
2115 @param WayIndexIsValid Bit21, The way and index field in the
2116 cache_check parameter is valid.
2118 @param MultipleBitsError Bit23, A multiple-bit error was
2119 detected, and data was poisoned for
2120 the corresponding cache line during
2123 @param IndexOfCacheLineError Bit51:32, Index of the cache
2124 line where the error occurred.
2126 @param InstructionSet Bit54, Instruction set. If this value
2127 is set to zero, the instruction that
2128 generated the machine check was an
2129 Intel Itanium instruction. If this bit
2130 is set to one, the instruction that
2131 generated the machine check was IA-32
2134 @param InstructionSetIsValid Bit55, The is field in the
2135 cache_check parameter is valid.
2137 @param PrivilegeLevel Bit57:56, Privilege level. The
2138 privilege level of the instruction
2139 bundle responsible for generating the
2142 @param PrivilegeLevelIsValide Bit58, The pl field of the
2143 cache_check parameter is
2146 @param McCorrected Bit59, Machine check corrected: This bit
2147 is set to one to indicate that the machine
2148 check has been corrected.
2150 @param TargetAddressIsValid Bit60, Target address is valid:
2151 This bit is set to one to
2152 indicate that a valid target
2153 address has been logged.
2155 @param RequesterIdentifier Bit61, Requester identifier: This
2156 bit is set to one to indicate that
2157 a valid requester identifier has
2160 @param ResponserIdentifier Bit62, Responder identifier: This
2161 bit is set to one to indicate that
2162 a valid responder identifier has
2165 @param PreciseInsPointer Bit63, Precise instruction pointer.
2166 This bit is set to one to indicate
2167 that a valid precise instruction
2168 pointer has been logged.
2173 UINT64 FailedCacheLevel
:2;
2175 UINT64 FailedInDataPart
:1;
2176 UINT64 FailedInTagPart
:1;
2177 UINT64 FailedInDataCache
:1;
2178 UINT64 FailedInInsCache
:1;
2180 UINT64 MesiIsValid
:1;
2182 UINT64 WayIndexIsValid
:1;
2185 UINT64 MultipleBitsError
:1;
2187 UINT64 IndexOfCacheLineError
:20;
2189 UINT64 InstructionSet
:1;
2190 UINT64 InstructionSetIsValid
:1;
2192 UINT64 PrivilegeLevel
:2;
2193 UINT64 PrivilegeLevelIsValide
:1;
2195 UINT64 McCorrected
:1;
2197 UINT64 TargetAddressIsValid
:1;
2198 UINT64 RequesterIdentifier
:1;
2199 UINT64 ResponserIdentifier
:1;
2200 UINT64 PreciseInsPointer
:1;
2202 } PAL_CACHE_CHECK_INFO
;
2206 @param FailedSlot Bit7:0, Slot number of the translation
2207 register where the failure occurred.
2209 @param FailedSlotIsValid Bit8, The tr_slot field in the
2210 TLB_check parameter is valid.
2212 @param TlbLevel Bit11:10, The level of the TLB where the
2213 error occurred. A value of 0 indicates the
2216 @param FailedInDataTr Bit16, Error occurred in the data
2217 translation registers.
2219 @param FailedInInsTr Bit17, Error occurred in the instruction
2220 translation registers
2222 @param FailedInDataTc Bit18, Error occurred in data
2225 @param FailedInInsTc Bit19, Error occurred in the instruction
2228 @param FailedOperation Bit23:20, Type of cache operation that
2229 caused the machine check: 0 - unknown
2230 1 - TLB access due to load instruction
2231 2 - TLB access due to store
2232 instruction 3 - TLB access due to
2233 instruction fetch or instruction
2234 prefetch 4 - TLB access due to data
2235 prefetch (both hardware and software)
2236 5 - TLB shoot down access 6 - TLB
2237 probe instruction (probe, tpa) 7 -
2238 move in (VHPT fill) 8 - purge (insert
2239 operation that purges entries or a TLB
2240 purge instruction) All other values
2243 @param InstructionSet Bit54, Instruction set. If this value
2244 is set to zero, the instruction that
2245 generated the machine check was an
2246 Intel Itanium instruction. If this bit
2247 is set to one, the instruction that
2248 generated the machine check was IA-32
2251 @param InstructionSetIsValid Bit55, The is field in the
2252 TLB_check parameter is valid.
2254 @param PrivelegeLevel Bit57:56, Privilege level. The
2255 privilege level of the instruction
2256 bundle responsible for generating the
2259 @param PrivelegeLevelIsValid Bit58, The pl field of the
2260 TLB_check parameter is valid.
2262 @param McCorrected Bit59, Machine check corrected: This bit
2263 is set to one to indicate that the machine
2264 check has been corrected.
2266 @param TargetAddressIsValid Bit60, Target address is valid:
2267 This bit is set to one to
2268 indicate that a valid target
2269 address has been logged.
2271 @param RequesterIdentifier Bit61 Requester identifier: This
2272 bit is set to one to indicate that
2273 a valid requester identifier has
2276 @param ResponserIdentifier Bit62, Responder identifier: This
2277 bit is set to one to indicate that
2278 a valid responder identifier has
2281 @param PreciseInsPointer Bit63 Precise instruction pointer.
2282 This bit is set to one to indicate
2283 that a valid precise instruction
2284 pointer has been logged.
2287 UINT64 FailedSlot
:8;
2288 UINT64 FailedSlotIsValid
:1;
2289 UINT64 Reserved1
:1;
2291 UINT64 Reserved2
:4;
2292 UINT64 FailedInDataTr
:1;
2293 UINT64 FailedInInsTr
:1;
2294 UINT64 FailedInDataTc
:1;
2295 UINT64 FailedInInsTc
:1;
2296 UINT64 FailedOperation
:4;
2297 UINT64 Reserved3
:30;
2298 UINT64 InstructionSet
:1;
2299 UINT64 InstructionSetIsValid
:1;
2300 UINT64 PrivelegeLevel
:2;
2301 UINT64 PrivelegeLevelIsValid
:1;
2302 UINT64 McCorrected
:1;
2303 UINT64 TargetAddressIsValid
:1;
2304 UINT64 RequesterIdentifier
:1;
2305 UINT64 ResponserIdentifier
:1;
2306 UINT64 PreciseInsPointer
:1;
2307 } PAL_TLB_CHECK_INFO
;
2311 PAL Procedure - PAL_MC_ERROR_INFO.
2313 Return Processor Machine Check Information and Processor
2314 Static State for logging by SAL. It is required by IPF. The
2315 PAL procedure supports the Static Registers calling
2316 convention. It could be called at physical and virtual mode.
2318 @param Index Index of PAL_MC_ERROR_INFO within the list of PAL
2321 @param InfoIndex Unsigned 64-bit integer identifying the
2322 error information that is being requested.
2323 See PAL_MC_ERROR_INFO.InfoIndex.
2325 @param LevelIndex 8-byte formatted value identifying the
2326 structure to return error information
2327 on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.
2329 @param ErrorTypeIndex Unsigned 64-bit integer denoting the
2330 type of error information that is
2331 being requested for the structure
2332 identified in LevelIndex.
2335 @return R9 Error information returned. The format of this
2336 value is dependant on the input values passed.
2338 @return R10 If this value is zero, all the error information
2339 specified by err_type_index has been returned. If
2340 this value is one, more structure-specific error
2341 information is available and the caller needs to
2342 make this procedure call again with level_index
2343 unchanged and err_type_index, incremented.
2346 @return Status 0 - Call completed without error
2348 @return Status -2 - Invalid argument
2350 @return Status -3 - Call completed with error.
2352 @return Status -6 - Argument was valid, but no error
2353 information was available
2357 #define PAL_MC_ERROR_INFO 25
2361 PAL Procedure - PAL_MC_EXPECTED.
2363 Set/Reset Expected Machine Check Indicator. It is required by
2364 IPF. The PAL procedure supports the Static Registers calling
2365 convention. It could be called at physical mode.
2367 @param Index Index of PAL_MC_EXPECTED within the list of PAL
2370 @param Expected Unsigned integer with a value of 0 or 1 to
2371 set or reset the hardware resource
2372 PALE_CHECK examines for expected machine
2376 @return R9 Unsigned integer denoting whether a machine check
2377 was previously expected.
2380 @return Status 0 - Call completed without error
2382 @return Status -2 - Invalid argument
2384 @return Status -3 - Call completed with error.
2387 #define PAL_MC_EXPECTED 23
2391 PAL Procedure - PAL_MC_REGISTER_MEM.
2393 Register min-state save area with PAL for machine checks and
2394 inits. It is required by IPF. The PAL procedure supports the
2395 Static Registers calling convention. It could be called at
2398 @param Index Index of PAL_MC_REGISTER_MEM within the list of PAL
2401 @param Address Physical address of the buffer to be
2402 registered with PAL.
2406 @return Status 0 - Call completed without error
2408 @return Status -2 - Invalid argument
2410 @return Status -3 - Call completed with error.
2413 #define PAL_MC_REGISTER_MEM 27
2417 PAL Procedure - PAL_MC_RESUME.
2419 Restore minimal architected state and return to interrupted
2420 process. It is required by IPF. The PAL procedure supports the
2421 Static Registers calling convention. It could be called at
2424 @param Index Index of PAL_MC_RESUME within the list of PAL
2427 @param SetCmci Unsigned 64 bit integer denoting whether to
2428 set the CMC interrupt. A value of 0 indicates
2429 not to set the interrupt, a value of 1
2430 indicated to set the interrupt, and all other
2431 values are reserved.
2433 @param SavePtr Physical address of min-state save area used
2434 to used to restore processor state.
2436 @param NewContext Unsigned 64-bit integer denoting whether
2437 the caller is returning to a new context.
2438 A value of 0 indicates the caller is
2439 returning to the interrupted context, a
2440 value of 1 indicates that the caller is
2441 returning to a new context.
2445 @return Status -2 - Invalid argument
2447 @return Status -3 - Call completed with error.
2450 #define PAL_MC_RESUME 26
2454 PAL Procedure - PAL_HALT.
2456 Enter the low-power HALT state or an implementation-dependent
2457 low-power state. It is optinal. The PAL procedure supports the
2458 Static Registers calling convention. It could be called at
2461 @param Index Index of PAL_HALT within the list of PAL
2464 @param HaltState Unsigned 64-bit integer denoting low power
2467 @param IoDetailPtr 8-byte aligned physical address pointer to
2468 information on the type of I/O
2469 (load/store) requested.
2472 @return R9 Value returned if a load instruction is requested
2473 in the io_detail_ptr
2476 @return Status 0 - Call completed without error
2478 @return Status -1 - Unimplemented procedure
2480 @return Status -2 - Invalid argument
2482 @return Status -3 - Call completed with error.
2490 PAL Procedure - PAL_HALT_INFO.
2492 Return the low power capabilities of the processor. It is
2493 required by IPF. The PAL procedure supports the
2494 Stacked Registers calling convention. It could be called at
2495 physical and virtual mode.
2497 @param Index Index of PAL_HALT_INFO within the list of PAL
2500 @param PowerBuffer 64-bit pointer to a 64-byte buffer aligned
2501 on an 8-byte boundary.
2505 @return Status 0 - Call completed without error
2507 @return Status -2 - Invalid argument
2509 @return Status -3 - Call completed with error.
2512 #define PAL_HALT_INFO 257
2517 PAL Procedure - PAL_HALT_LIGHT.
2519 Enter the low power LIGHT HALT state. It is required by
2520 IPF. The PAL procedure supports the Static Registers calling
2521 convention. It could be called at physical and virtual mode.
2523 @param Index Index of PAL_HALT_LIGHT within the list of PAL
2527 @return Status 0 - Call completed without error
2529 @return Status -2 - Invalid argument
2531 @return Status -3 - Call completed with error.
2534 #define PAL_HALT_LIGHT 29
2538 PAL Procedure - PAL_CACHE_LINE_INIT.
2540 Initialize tags and data of a cache line for processor
2541 testing. It is required by IPF. The PAL procedure supports the
2542 Static Registers calling convention. It could be called at
2543 physical and virtual mode.
2545 @param Index Index of PAL_CACHE_LINE_INIT within the list of PAL
2548 @param Address Unsigned 64-bit integer value denoting the
2549 physical address from which the physical page
2550 number is to be generated. The address must be
2551 an implemented physical address, bit 63 must
2554 @param DataValue 64-bit data value which is used to
2555 initialize the cache line.
2558 @return Status 0 - Call completed without error
2560 @return Status -2 - Invalid argument
2562 @return Status -3 - Call completed with error.
2565 #define PAL_CACHE_LINE_INIT 31
2569 PAL Procedure - PAL_CACHE_READ.
2571 Read tag and data of a cache line for diagnostic testing. It
2572 is optional. The PAL procedure supports the
2573 Satcked Registers calling convention. It could be called at
2576 @param Index Index of PAL_CACHE_READ within the list of PAL
2579 @param LineId 8-byte formatted value describing where in the
2580 cache to read the data.
2582 @param Address 64-bit 8-byte aligned physical address from
2583 which to read the data. The address must be an
2584 implemented physical address on the processor
2585 model with bit 63 set to zero.
2587 @return R9 Right-justified value returned from the cache
2590 @return R10 The number of bits returned in data.
2592 @return R11 The status of the cache line.
2596 @return Status 1 - The word at address was found in the
2597 cache, but the line was invalid.
2599 @return Status 0 - Call completed without error
2601 @return Status -2 - Invalid argument
2603 @return Status -3 - Call completed with error.
2605 @return Status -5 - The word at address was not found in the
2608 @return Status -7 - The operation requested is not supported
2609 for this cache_type and level.
2612 #define PAL_CACHE_READ 259
2617 Write tag and data of a cache for diagnostic testing. It is
2618 optional. The PAL procedure supports the Satcked Registers
2619 calling convention. It could be called at physical mode.
2621 @param Index Index of PAL_CACHE_WRITE within the list of PAL
2624 @param LineId 8-byte formatted value describing where in the
2625 cache to write the data.
2627 @param Address 64-bit 8-byte aligned physical address at
2628 which the data should be written. The address
2629 must be an implemented physical address on the
2630 processor model with bit 63 set to 0.
2632 @param Data Unsigned 64-bit integer value to write into
2633 the specified part of the cache.
2636 @return Status 0 - Call completed without error
2638 @return Status -2 - Invalid argument
2640 @return Status -3 - Call completed with error.
2643 @return Status -7 - The operation requested is not supported
2644 for this cache_type and level.
2647 #define PAL_CACHE_WRITE 260
2651 PAL Procedure - PAL_TEST_INFO.
2653 Returns alignment and size requirements needed for the memory
2654 buffer passed to the PAL_TEST_PROC procedure as well as
2655 information on self-test control words for the processor self
2656 tests. It is required by IPF. The PAL procedure supports the
2657 Static Registers calling convention. It could be called at
2660 @param Index Index of PAL_TEST_INFO within the list of PAL
2663 @param TestPhase Unsigned integer that specifies which phase
2664 of the processor self-test information is
2665 being requested on. A value of 0 indicates
2666 the phase two of the processor self-test and
2667 a value of 1 indicates phase one of the
2668 processor self-test. All other values are
2671 @return R9 Unsigned 64-bit integer denoting the number of
2672 bytes of main memory needed to perform the second
2673 phase of processor self-test.
2675 @return R10 Unsigned 64-bit integer denoting the alignment
2676 required for the memory buffer.
2678 @return R11 48-bit wide bit-field indicating if control of
2679 the processor self-tests is supported and which
2680 bits of the test_control field are defined for
2684 @return Status 0 - Call completed without error
2686 @return Status -2 - Invalid argument
2688 @return Status -3 - Call completed with error.
2692 #define PAL_TEST_INFO 37
2696 @param BufferSize Indicates the size in bytes of the memory
2697 buffer that is passed to this procedure.
2698 BufferSize must be greater than or equal in
2699 size to the bytes_needed return value from
2700 PAL_TEST_INFO, otherwise this procedure will
2701 return with an invalid argument return
2704 @param TestPhase Defines which phase of the processor
2705 self-tests are requested to be run. A value
2706 of zero indicates to run phase two of the
2707 processor self-tests. Phase two of the
2708 processor self-tests are ones that require
2709 external memory to execute correctly. A
2710 value of one indicates to run phase one of
2711 the processor self-tests. Phase one of the
2712 processor self-tests are tests run during
2713 PALE_RESET and do not depend on external
2714 memory to run correctly. When the caller
2715 requests to have phase one of the processor
2716 self-test run via this procedure call, a
2717 memory buffer may be needed to save and
2718 restore state as required by the PAL calling
2719 conventions. The procedure PAL_TEST_INFO
2720 informs the caller about the requirements of
2725 UINT64 BufferSize
:56;
2727 } PAL_TEST_INFO_INFO
;
2731 @param TestControl This is an ordered implementation-specific
2732 control word that allows the user control
2733 over the length and runtime of the
2734 processor self-tests. This control word is
2735 ordered from the longest running tests up
2736 to the shortest running tests with bit 0
2737 controlling the longest running test. PAL
2738 may not implement all 47-bits of the
2739 test_control word. PAL communicates if a
2740 bit provides control by placing a zero in
2741 that bit. If a bit provides no control,
2742 PAL will place a one in it. PAL will have
2743 two sets of test_control bits for the two
2744 phases of the processor self-test. PAL
2745 provides information about implemented
2746 test_control bits at the hand-off from PAL
2747 to SAL for the firmware recovery check.
2748 These test_control bits provide control
2749 for phase one of processor self-test. It
2750 also provides this information via the PAL
2751 procedure call PAL_TEST_INFO for both the
2752 phase one and phase two processor tests
2753 depending on which information the caller
2754 is requesting. PAL interprets these bits
2755 as input parameters on two occasions. The
2756 first time is when SAL passes control back
2757 to PAL after the firmware recovery check.
2758 The second time is when a call to
2759 PAL_TEST_PROC is made. When PAL interprets
2760 these bits it will only interpret
2761 implemented test_control bits and will
2762 ignore the values located in the
2763 unimplemented test_control bits. PAL
2764 interprets the implemented bits such that
2765 if a bit contains a zero, this indicates
2766 to run the test. If a bit contains a one,
2767 this indicates to PAL to skip the test. If
2768 the cs bit indicates that control is not
2769 available, the test_control bits will be
2770 ignored or generate an illegal argument in
2771 procedure calls if the caller sets these
2774 @param ControlSupport This bit defines if an implementation
2775 supports control of the PAL self-tests
2776 via the self-test control word. If
2777 this bit is 0, the implementation does
2778 not support control of the processor
2779 self-tests via the self-test control
2780 word. If this bit is 1, the
2781 implementation does support control of
2782 the processor self-tests via the
2783 self-test control word. If control is
2784 not supported, GR37 will be ignored at
2785 the hand-off between SAL and PAL after
2786 the firmware recovery check and the
2787 PAL procedures related to the
2788 processor self-tests may return
2789 illegal arguments if a user tries to
2790 use the self-test control features.
2794 UINT64 TestControl
:47;
2795 UINT64 ControlSupport
:1;
2797 } PAL_SELF_TEST_CONTROL
;
2801 @param Attributes Specifies the memory attributes that are
2802 allowed to be used with the memory buffer
2803 passed to this procedure. The attributes
2804 parameter is a vector where each bit
2805 represents one of the virtual memory
2806 attributes defined by the architecture.See
2807 MEMORY_AATRIBUTES. The caller is required
2808 to support the cacheable attribute for the
2809 memory buffer, otherwise an invalid
2810 argument will be returned.
2813 @param TestControl Is the self-test control word
2814 corresponding to the test_phase passed.
2815 This test_control directs the coverage and
2816 runtime of the processor self-tests
2817 specified by the test_phase input
2818 argument. Information on if this
2819 feature is implemented and the number of
2820 bits supported can be obtained by the
2821 PAL_TEST_INFO procedure call. If this
2822 feature is implemented by the processor,
2823 the caller can selectively skip parts of
2824 the processor self-test by setting
2825 test_control bits to a one. If a bit has a
2826 zero, this test will be run. The values in
2827 the unimplemented bits are ignored. If
2828 PAL_TEST_INFO indicated that the self-test
2829 control word is not implemented, this
2830 procedure will return with an invalid
2831 argument status if the caller sets any of
2832 the test_control bits. See
2833 PAL_SELF_TEST_CONTROL.
2836 UINT64 Attributes
:8;
2838 UINT64 TestControl
:48;
2843 PAL Procedure - PAL_TEST_PROC.
2845 Perform late processor self test. It is required by IPF. The
2846 PAL procedure supports the Static Registers calling
2847 convention. It could be called at physical mode.
2849 @param Index Index of PAL_TEST_PROC within the list of PAL
2852 @param TestAddress 64-bit physical address of main memory
2853 area to be used by processor self-test.
2854 The memory region passed must be
2855 cacheable, bit 63 must be zero.
2857 @param TestInfo Input argument specifying the size of the
2858 memory buffer passed and the phase of the
2859 processor self-test that should be run. See
2862 @param TestParam Input argument specifying the self-test
2863 control word and the allowable memory
2864 attributes that can be used with the memory
2865 buffer. See PAL_TEST_CONTROL.
2867 @return R9 Formatted 8-byte value denoting the state of the
2868 processor after self-test
2872 @return Status 1 - Call completed without error, but hardware
2873 failures occurred during self-test.
2875 @return Status 0 - Call completed without error
2877 @return Status -2 - Invalid argument
2879 @return Status -3 - Call completed with error.
2883 #define PAL_TEST_PROC 258
2887 @param NumberOfInterruptControllers Number of interrupt
2888 controllers currently
2889 enabled on the system.
2891 @param NumberOfProcessors Number of processors currently
2892 enabled on the system.
2896 UINT32 NumberOfInterruptControllers
;
2897 UINT32 NumberOfProcessors
;
2898 } PAL_PLATFORM_INFO
;
2902 PAL Procedure - PAL_COPY_INFO.
2904 Return information needed to relocate PAL procedures and PAL
2905 PMI code to memory. It is required by IPF. The PAL procedure
2906 supports the Static Registers calling convention. It could be
2907 called at physical mode.
2909 @param Index Index of PAL_COPY_INFO within the list of PAL
2912 @param CopyType Unsigned integer denoting type of procedures
2913 for which copy information is requested.
2915 @param PlatformInfo 8-byte formatted value describing the
2916 number of processors and the number of
2917 interrupt controllers currently enabled
2918 on the system. See PAL_PLATFORM_INFO.
2921 @param McaProcStateInfo Unsigned integer denoting the number
2922 of bytes that SAL needs for the
2923 min-state save area for each
2928 @return R9 Unsigned integer denoting the number of bytes of
2929 PAL information that must be copied to main
2932 @return R10 Unsigned integer denoting the starting alignment
2933 of the data to be copied.
2935 @return Status 0 - Call completed without error
2937 @return Status -2 - Invalid argument
2939 @return Status -3 - Call completed with error.
2943 #define PAL_COPY_INFO 30
2947 PAL Procedure - PAL_COPY_PAL.
2949 Relocate PAL procedures and PAL PMI code to memory. It is
2950 required by IPF. The PAL procedure supports the Stacked
2951 Registers calling convention. It could be called at physical
2954 @param Index Index of PAL_COPY_PAL within the list of PAL
2957 @param TargetAddress Physical address of a memory buffer to
2958 copy relocatable PAL procedures and PAL
2961 @param AllocSize Unsigned integer denoting the size of the
2962 buffer passed by SAL for the copy operation.
2965 @param CopyOption Unsigned integer indicating whether
2966 relocatable PAL code and PAL PMI code
2967 should be copied from firmware address
2968 space to main memory.
2971 @return R9 Unsigned integer denoting the offset of PAL_PROC
2972 in the relocatable segment copied.
2974 @return Status 0 - Call completed without error
2976 @return Status -2 - Invalid argument
2978 @return Status -3 - Call completed with error.
2982 #define PAL_COPY_PAL 256
2986 PAL Procedure - PAL_ENTER_IA_32_ENV.
2988 Enter IA-32 System environment. It is optional. The PAL
2989 procedure supports the Static Registers calling convention.
2990 It could be called at physical mode.
2992 Note: Since this is a special call, it does not follow the PAL
2993 static register calling convention. GR28 contains the index of
2994 PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other
2995 input arguments including GR29-GR31 are setup by SAL to values
2996 as required by the IA-32 operating system defined in Table
2997 11-67. The registers that are designated as preserved, scratch,
2998 input arguments and procedure return values by the static
2999 procedure calling convention are not followed by this call. For
3000 instance, GR5 and GR6 need not be preserved since these are
3001 regarded as scratch by the IA-32 operating system. Note: In an
3002 MP system, this call must be COMPLETED on the first CPU to enter
3003 the IA-32 System Environment (may or may not be the BSP) prior
3004 to being called on the remaining processors in the MP system.
3006 @param Index GR28 contains the index of the
3007 PAL_ENTER_IA_32_ENV call within the list of PAL
3011 @return Status The status is returned in GR4.
3012 -1 - Un-implemented procedure 0 JMPE detected
3015 0 - 1 SAL allocated buffer for IA-32 System
3016 Environment operation is too small
3018 2 - IA-32 Firmware Checksum Error
3020 3 - SAL allocated buffer for IA-32 System
3021 Environment operation is not properly aligned
3023 4 - Error in SAL MP Info Table
3025 5 - Error in SAL Memory Descriptor Table
3027 6 - Error in SAL System Table
3029 7 - Inconsistent IA-32 state
3031 8 - IA-32 Firmware Internal Error
3033 9 - IA-32 Soft Reset (Note: remaining register
3034 state is undefined for this termination
3037 10 - Machine Check Error
3039 11 - Error in SAL I/O Intercept Table
3041 12 - Processor exit due to other processor in
3042 MP system terminating the IA32 system
3043 environment. (Note: remaining register state
3044 is undefined for this termination reason.)
3046 13 - Itanium architecture-based state
3047 corruption by either SAL PMI handler or I/O
3048 Intercept callback function.
3052 #define PAL_ENTER_IA_32_ENV 33
3056 PAL Procedure - PAL_PMI_ENTRYPOINT.
3058 Register PMI memory entrypoints with processor. It is required
3059 by IPF. The PAL procedure supports the Stacked Registers
3060 calling convention. It could be called at physical mode.
3062 @param Index Index of PAL_PMI_ENTRYPOINT within the list of
3065 @param SalPmiEntry 256-byte aligned physical address of SAL
3066 PMI entrypoint in memory.
3069 @return Status 0 - Call completed without error
3071 @return Status -2 - Invalid argument
3073 @return Status -3 - Call completed with error.
3077 #define PAL_PMI_ENTRYPOINT 32
3082 The ASCII brand identification string will be copied to the
3083 address specified in the address input argument. The processor
3084 brand identification string is defined to be a maximum of 128
3085 characters long; 127 bytes will contain characters and the 128th
3086 byte is defined to be NULL (0). A processor may return less than
3087 the 127 ASCII characters as long as the string is null
3088 terminated. The string length will be placed in the brand_info
3092 #define PAL_BRAND_INFO_ID_REQUEST 0
3096 PAL Procedure - PAL_BRAND_INFO.
3098 Provides processor branding information. It is optional by
3099 IPF. The PAL procedure supports the Stacked Registers calling
3100 convention. It could be called at physical and Virtual mode.
3103 @param Index Index of PAL_BRAND_INFO within the list of PAL
3106 @param InfoRequest Unsigned 64-bit integer specifying the
3107 information that is being requested. (See
3108 PAL_BRAND_INFO_ID_REQUEST)
3110 @param Address Unsigned 64-bit integer specifying the
3111 address of the 128-byte block to which the
3112 processor brand string shall be written.
3115 @reture R9 Brand information returned. The format of this
3116 value is dependent on the input values passed.
3119 @return Status 0 - Call completed without error
3121 @return Status -1 - Unimplemented procedure
3123 @return Status -2 - Invalid argument
3125 @return Status -3 - Call completed with error.
3127 @return Status -6 - Input argument is not implemented.
3130 #define PAL_BRAND_INFO 274
3134 PAL Procedure - PAL_GET_HW_POLICY.
3136 Returns the current hardware resource sharing policy of the
3137 processor. It is optional by IPF. The PAL procedure supports
3138 the Static Registers calling convention. It could be called at
3139 physical and Virtual mode.
3142 @param Index Index of PAL_GET_HW_POLICY within the list of PAL
3145 @param ProcessorNumber Unsigned 64-bit integer that specifies
3146 for which logical processor
3147 information is being requested. This
3148 input argument must be zero for the
3149 first call to this procedure and can
3150 be a maximum value of one less than
3151 the number of logical processors
3152 impacted by the hardware resource
3153 sharing policy, which is returned by
3154 the R10 return value.
3157 @reture R9 Unsigned 64-bit integer representing the current
3158 hardware resource sharing policy.
3160 @return R10 Unsigned 64-bit integer that returns the number
3161 of logical processors impacted by the policy
3164 @return R11 Unsigned 64-bit integer containing the logical
3165 address of one of the logical processors
3166 impacted by policy modification.
3169 @return Status 0 - Call completed without error
3171 @return Status -1 - Unimplemented procedure
3173 @return Status -2 - Invalid argument
3175 @return Status -3 - Call completed with error.
3177 @return Status -9 - Call requires PAL memory buffer.
3180 #define PAL_GET_HW_POLICY 48
3184 // Value of PAL_SET_HW_POLICY.Policy
3186 #define PAL_SET_HW_POLICY_PERFORMANCE 0
3187 #define PAL_SET_HW_POLICY_FAIRNESS 1
3188 #define PAL_SET_HW_POLICY_HIGH_PRIORITY 2
3189 #define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3
3193 PAL Procedure - PAL_SET_HW_POLICY.
3195 Sets the current hardware resource sharing policy of the
3196 processor. It is optional by IPF. The PAL procedure supports
3197 the Static Registers calling convention. It could be called at
3198 physical and Virtual mode.
3201 @param Index Index of PAL_SET_HW_POLICY within the list of PAL
3204 @param Policy Unsigned 64-bit integer specifying the hardware
3205 resource sharing policy the caller is setting.
3206 See Value of PAL_SET_HW_POLICY.Policy above.
3209 @return Status 1 - Call completed successfully but could not
3210 change the hardware policy since a
3211 competing logical processor is set in
3212 exclusive high priority.
3214 @return Status 0 - Call completed without error
3216 @return Status -1 - Unimplemented procedure
3218 @return Status -2 - Invalid argument
3220 @return Status -3 - Call completed with error.
3222 @return Status -9 - Call requires PAL memory buffer.
3225 #define PAL_SET_HW_POLICY 49
3230 @param Mode Bit2:0, Indicates the mode of operation for this
3231 procedure: 0 - Query mode 1 ¨C Error inject mode
3232 (err_inj should also be specified) 2 - Cancel
3233 outstanding trigger. All other fields in
3234 PAL_MC_ERROR_TYPE_INFO,
3235 PAL_MC_ERROR_STRUCTURE_INFO and
3236 PAL_MC_ERROR_DATA_BUFFER are ignored. All other
3237 values are reserved.
3239 @param ErrorInjection Bit5:3, indicates the mode of error
3240 injection: 0 - Error inject only (no
3241 error consumption) 1 - Error inject
3242 and consume All other values are
3246 @param ErrorSeverity Bit7:6, indicates the severity desired
3247 for error injection/query. Definitions
3248 of the different error severity types
3249 0 - Corrected error 1 - Recoverable
3250 error 2 - Fatal error 3 - Reserved
3253 @param ErrorStructure Bit12:8, Indicates the structure
3254 identification for error
3255 injection/query: 0 - Any structure
3256 (cannot be used during query mode).
3257 When selected, the structure type used
3258 for error injection is determined by
3259 PAL. 1 - Cache 2 - TLB 3 - Register
3260 file 4 - Bus/System interconnect 5-15
3261 - Reserved 16-31 - Processor
3262 specific error injection
3263 capabilities.ErrorDataBuffer is used
3264 to specify error types. Please refer
3265 to the processor specific
3266 documentation for additional details.
3268 @param StructureHierarchy Bit15:13, Indicates the structure
3270 injection/query: 0 - Any level of
3271 hierarchy (cannot be used during
3272 query mode). When selected, the
3273 structure hierarchy used for error
3274 injection is determined by PAL. 1
3275 - Error structure hierarchy
3276 level-1 2 - Error structure
3277 hierarchy level-2 3 - Error
3278 structure hierarchy level-3 4 -
3279 Error structure hierarchy level-4
3280 All other values are reserved.
3281 Reserved 63:16 Reserved
3286 UINT64 ErrorInjection
:3;
3287 UINT64 ErrorSeverity
:2;
3288 UINT64 ErrorStructure
:5;
3289 UINT64 StructureHierarchy
:3;
3291 } PAL_MC_ERROR_TYPE_INFO
;
3295 @param StructInfoIsValid Bit0 When 1, indicates that the
3296 structure information fields
3297 (c_t,cl_p,cl_id) are valid and
3298 should be used for error injection.
3299 When 0, the structure information
3300 fields are ignored, and the values
3301 of these fields used for error
3303 implementation-specific.
3305 @param CacheType Bit2:1 Indicates which cache should be used
3306 for error injection: 0 - Reserved 1 -
3307 Instruction cache 2 - Data or unified cache
3311 @param PortionOfCacheLine Bit5:3 Indicates the portion of the
3312 cache line where the error should
3313 be injected: 0 - Reserved 1 - Tag
3314 2 - Data 3 - mesi All other
3315 values are reserved.
3317 @param Mechanism Bit8:6 Indicates which mechanism is used to
3318 identify the cache line to be used for error
3319 injection: 0 - Reserved 1 - Virtual address
3320 provided in the inj_addr field of the buffer
3321 pointed to by err_data_buffer should be used
3322 to identify the cache line for error
3323 injection. 2 - Physical address provided in
3324 the inj_addr field of the buffer pointed to
3325 by err_data_buffershould be used to identify
3326 the cache line for error injection. 3 - way
3327 and index fields provided in err_data_buffer
3328 should be used to identify the cache line
3329 for error injection. All other values are
3332 @param DataPoisonOfCacheLine Bit9 When 1, indicates that a
3333 multiple bit, non-correctable
3334 error should be injected in the
3335 cache line specified by cl_id.
3336 If this injected error is not
3337 consumed, it may eventually
3338 cause a data-poisoning event
3339 resulting in a corrected error
3340 signal, when the associated
3341 cache line is cast out (implicit
3342 or explicit write-back of the
3343 cache line). The error severity
3344 specified by err_sev in
3345 err_type_info must be set to 0
3346 (corrected error) when this bit
3350 @param TrigerInfoIsValid Bit32 When 1, indicates that the
3351 trigger information fields (trigger,
3352 trigger_pl) are valid and should be
3353 used for error injection. When 0,
3354 the trigger information fields are
3355 ignored and error injection is
3356 performed immediately.
3358 @param Triger Bit36:33 Indicates the operation type to be
3359 used as the error trigger condition. The
3360 address corresponding to the trigger is
3361 specified in the trigger_addr field of the
3362 buffer pointed to by err_data_buffer: 0 -
3363 Instruction memory access. The trigger match
3364 conditions for this operation type are similar
3365 to the IBR address breakpoint match conditions
3366 1 - Data memory access. The trigger match
3367 conditions for this operation type are similar
3368 to the DBR address breakpoint match conditions
3369 All other values are reserved.
3371 @param PrivilegeOfTriger Bit39:37 Indicates the privilege
3372 level of the context during which
3373 the error should be injected: 0 -
3374 privilege level 0 1 - privilege
3375 level 1 2 - privilege level 2 3 -
3376 privilege level 3 All other values
3377 are reserved. If the implementation
3378 does not support privilege level
3379 qualifier for triggers (i.e. if
3380 trigger_pl is 0 in the capabilities
3381 vector), this field is ignored and
3382 triggers can be taken at any
3387 UINT64 StructInfoIsValid
:1;
3389 UINT64 PortionOfCacheLine
:3;
3391 UINT64 DataPoisonOfCacheLine
:1;
3392 UINT64 Reserved1
:22;
3393 UINT64 TrigerInfoIsValid
:1;
3395 UINT64 PrivilegeOfTriger
:3;
3396 UINT64 Reserved2
:24;
3397 } PAL_MC_ERROR_STRUCT_INFO
;
3401 Buffer Pointed to by err_data_buffer ¨C TLB
3405 UINT64 TrigerAddress
;
3406 UINT64 VirtualPageNumber
:52;
3409 UINT64 Reserved2
:40;
3410 } PAL_MC_ERROR_DATA_BUFFER_TLB
;
3414 PAL Procedure - PAL_MC_ERROR_INJECT.
3416 Injects the requested processor error or returns information
3417 on the supported injection capabilities for this particular
3418 processor implementation. It is optional by IPF. The PAL
3419 procedure supports the Stacked Registers calling convention.
3420 It could be called at physical and Virtual mode.
3423 @param Index Index of PAL_MC_ERROR_INJECT within the list of PAL
3426 @param ErrorTypeInfo Unsigned 64-bit integer specifying the
3427 first level error information which
3428 identifies the error structure and
3429 corresponding structure hierarchy, and
3432 @param ErrorStructInfo Unsigned 64-bit integer identifying
3433 the optional structure specific
3434 information that provides the second
3435 level details for the requested error.
3437 @param ErrorDataBuffer 64-bit physical address of a buffer
3438 providing additional parameters for
3439 the requested error. The address of
3440 this buffer must be 8-byte aligned.
3442 @return R9 64-bit vector specifying the supported error
3443 injection capabilities for the input argument
3444 combination of struct_hier, err_struct and
3445 err_sev fields in ErrorTypeInfo.
3447 @return R10 64-bit vector specifying the architectural
3448 resources that are used by the procedure.
3451 @return Status 0 - Call completed without error
3453 @return Status -1 - Unimplemented procedure
3455 @return Status -2 - Invalid argument
3457 @return Status -3 - Call completed with error.
3459 @return Status -4 - Call completed with error; the requested
3460 error could not be injected due to failure in
3461 locating the target location in the specified
3464 @return Status -5 - Argument was valid, but requested error
3465 injection capability is not supported.
3467 @return Status -9 - Call requires PAL memory buffer.
3470 #define PAL_MC_ERROR_INJECT 276
3474 // Types of PAL_GET_PSTATE.Type
3476 #define PAL_GET_PSTATE_RECENT 0
3477 #define PAL_GET_PSTATE_AVERAGE_NEW_START 1
3478 #define PAL_GET_PSTATE_AVERAGE 2
3479 #define PAL_GET_PSTATE_NOW 3
3483 PAL Procedure - PAL_GET_PSTATE.
3485 Returns the performance index of the processor. It is optional
3486 by IPF. The PAL procedure supports the Stacked Registers
3487 calling convention. It could be called at physical and Virtual
3491 @param Index Index of PAL_GET_PSTATE within the list of PAL
3494 @param Type Type of performance_index value to be returned
3495 by this procedure.See PAL_GET_PSTATE.Type above.
3498 @return R9 Unsigned integer denoting the processor
3499 performance for the time duration since the last
3500 PAL_GET_PSTATE procedure call was made. The
3501 value returned is between 0 and 100, and is
3502 relative to the performance index of the highest
3505 @return Status 1 - Call completed without error, but accuracy
3506 of performance index has been impacted by a
3507 thermal throttling event, or a
3508 hardware-initiated event.
3510 @return Status 0 - Call completed without error
3512 @return Status -1 - Unimplemented procedure
3514 @return Status -2 - Invalid argument
3516 @return Status -3 - Call completed with error.
3518 @return Status -9 - Call requires PAL memory buffer.
3521 #define PAL_GET_PSTATE 262
3525 Layout of PAL_PSTATE_INFO.PStateBuffer
3529 UINT32 PerformanceIndex
:7;
3531 UINT32 TypicalPowerDissipation
:20;
3532 UINT32 TransitionLatency1
;
3533 UINT32 TransitionLatency2
;
3535 } PAL_PSTATE_INFO_BUFFER
;
3540 PAL Procedure - PAL_PSTATE_INFO.
3542 Returns information about the P-states supported by the
3543 processor. It is optional by IPF. The PAL procedure supports
3544 the Static Registers calling convention. It could be called
3545 at physical and Virtual mode.
3548 @param Index Index of PAL_PSTATE_INFO within the list of PAL
3551 @param PStateBuffer 64-bit pointer to a 256-byte buffer
3552 aligned on an 8-byte boundary. See
3553 PAL_PSTATE_INFO_BUFFER above.
3556 @return R9 Unsigned integer denoting the number of P-states
3557 supported. The maximum value of this field is 16.
3559 @return R10 Dependency domain information
3562 @return Status 0 - Call completed without error
3564 @return Status -1 - Unimplemented procedure
3566 @return Status -2 - Invalid argument
3568 @return Status -3 - Call completed with error.
3571 #define PAL_PSTATE_INFO 44
3576 PAL Procedure - PAL_SET_PSTATE.
3578 To request a processor transition to a given P-state. It is
3579 optional by IPF. The PAL procedure supports the Stacked
3580 Registers calling convention. It could be called at physical
3584 @param Index Index of PAL_SET_PSTATE within the list of PAL
3587 @param PState Unsigned integer denoting the processor
3588 P-state being requested.
3590 @param ForcePState Unsigned integer denoting whether the
3591 P-state change should be forced for the
3598 @return Status 1 - Call completed without error, but
3599 transition request was not accepted
3601 @return Status 0 - Call completed without error
3603 @return Status -1 - Unimplemented procedure
3605 @return Status -2 - Invalid argument
3607 @return Status -3 - Call completed with error.
3609 @return Status -9 - Call requires PAL memory buffer.
3612 #define PAL_SET_PSTATE 263
3616 PAL Procedure - PAL_SHUTDOWN.
3618 Put the logical processor into a low power state which can be
3619 exited only by a reset event. It is optional by IPF. The PAL
3620 procedure supports the Static Registers calling convention. It
3621 could be called at physical mode.
3624 @param Index Index of PAL_SHUTDOWN within the list of PAL
3627 @param NotifyPlatform 8-byte aligned physical address
3628 pointer providing details on how to
3629 optionally notify the platform that
3630 the processor is entering a shutdown
3633 @return Status -1 - Unimplemented procedure
3635 @return Status -2 - Invalid argument
3637 @return Status -3 - Call completed with error.
3639 @return Status -9 - Call requires PAL memory buffer.
3642 #define PAL_SHUTDOWN 45
3646 Layout of PAL_MEMORY_BUFFER.ControlWord
3650 UINT64 Registration
:1;
3651 UINT64 ProbeInterrupt
:1;
3653 } PAL_MEMORY_CONTROL_WORD
;
3657 PAL Procedure - PAL_MEMORY_BUFFER.
3659 Provides cacheable memory to PAL for exclusive use during
3660 runtime. It is optional by IPF. The PAL procedure supports the
3661 Static Registers calling convention. It could be called at
3665 @param Index Index of PAL_MEMORY_BUFFER within the list of PAL
3668 @param BaseAddress Physical address of the memory buffer
3669 allocated for PAL use.
3671 @param AllocSize Unsigned integer denoting the size of the
3674 @param ControlWord Formatted bit vector that provides control
3675 options for this procedure. See
3676 PAL_MEMORY_CONTROL_WORD above.
3678 @return R9 Returns the minimum size of the memory buffer
3679 required if the alloc_size input argument was
3682 @return Status 1 - Call has not completed a buffer relocation
3683 due to a pending interrupt
3685 @return Status 0 - Call completed without error
3687 @return Status -1 - Unimplemented procedure
3689 @return Status -2 - Invalid argument
3691 @return Status -3 - Call completed with error.
3693 @return Status -9 - Call requires PAL memory buffer.
3696 #define PAL_MEMORY_BUFFER 277
3701 PAL Procedure - PAL_VP_CREATE.
3703 Initializes a new vpd for the operation of a new virtual
3704 processor in the virtual environment. It is optional by IPF.
3705 The PAL procedure supports the Stacked Registers calling
3706 convention. It could be called at Virtual mode.
3709 @param Index Index of PAL_VP_CREATE within the list of PAL
3712 @param Vpd 64-bit host virtual pointer to the Virtual
3713 Processor Descriptor (VPD).
3715 @param HostIva 64-bit host virtual pointer to the host IVT
3716 for the virtual processor
3718 @param OptionalHandler 64-bit non-zero host-virtual pointer
3719 to an optional handler for
3720 virtualization intercepts.
3723 @return Status 0 - Call completed without error
3725 @return Status -1 - Unimplemented procedure
3727 @return Status -2 - Invalid argument
3729 @return Status -3 - Call completed with error.
3731 @return Status -9 - Call requires PAL memory buffer.
3734 #define PAL_VP_CREATE 265
3738 Virtual Environment Information Parameter
3745 } PAL_VP_ENV_INFO_RETURN
;
3749 PAL Procedure - PAL_VP_ENV_INFO.
3751 Returns the parameters needed to enter a virtual environment.
3752 It is optional by IPF. The PAL procedure supports the Stacked
3753 Registers calling convention. It could be called at Virtual
3757 @param Index Index of PAL_VP_ENV_INFO within the list of PAL
3760 @param Vpd 64-bit host virtual pointer to the Virtual
3761 Processor Descriptor (VPD).
3763 @param HostIva 64-bit host virtual pointer to the host IVT
3764 for the virtual processor
3766 @param OptionalHandler 64-bit non-zero host-virtual pointer
3767 to an optional handler for
3768 virtualization intercepts.
3769 @return R9 Unsigned integer denoting the number of bytes
3770 required by the PAL virtual environment buffer
3771 during PAL_VP_INIT_ENV
3773 @return R10 64-bit vector of virtual environment
3774 information. See PAL_VP_ENV_INFO_RETURN.
3777 @return Status 0 - Call completed without error
3779 @return Status -1 - Unimplemented procedure
3781 @return Status -2 - Invalid argument
3783 @return Status -3 - Call completed with error.
3785 @return Status -9 - Call requires PAL memory buffer.
3788 #define PAL_VP_ENV_INFO 266
3792 PAL Procedure - PAL_VP_EXIT_ENV.
3794 Allows a logical processor to exit a virtual environment.
3795 It is optional by IPF. The PAL procedure supports the Stacked
3796 Registers calling convention. It could be called at Virtual
3800 @param Index Index of PAL_VP_EXIT_ENV within the list of PAL
3803 @param Iva Optional 64-bit host virtual pointer to the IVT
3804 when this procedure is done
3806 @return Status 0 - Call completed without error
3808 @return Status -1 - Unimplemented procedure
3810 @return Status -2 - Invalid argument
3812 @return Status -3 - Call completed with error.
3814 @return Status -9 - Call requires PAL memory buffer.
3817 #define PAL_VP_EXIT_ENV 267
3823 PAL Procedure - PAL_VP_INIT_ENV.
3825 Allows a logical processor to enter a virtual environment. It
3826 is optional by IPF. The PAL procedure supports the Stacked
3827 Registers calling convention. It could be called at Virtual
3831 @param Index Index of PAL_VP_INIT_ENV within the list of PAL
3834 @param ConfigOptions 64-bit vector of global configuration
3837 @param PhysicalBase Host physical base address of a block of
3838 contiguous physical memory for the PAL
3839 virtual environment buffer 1) This
3840 memory area must be allocated by the VMM
3841 and be 4K aligned. The first logical
3842 processor to enter the environment will
3843 initialize the physical block for
3844 virtualization operations.
3846 @param VirtualBase Host virtual base address of the
3847 corresponding physical memory block for
3848 the PAL virtual environment buffer : The
3849 VMM must maintain the host virtual to host
3850 physical data and instruction translations
3851 in TRs for addresses within the allocated
3852 address space. Logical processors in this
3853 virtual environment will use this address
3854 when transitioning to virtual mode
3857 @return R9 Virtualization Service Address ¨C VSA specifies
3858 the virtual base address of the PAL
3859 virtualization services in this virtual
3863 @return Status 0 - Call completed without error
3865 @return Status -1 - Unimplemented procedure
3867 @return Status -2 - Invalid argument
3869 @return Status -3 - Call completed with error.
3871 @return Status -9 - Call requires PAL memory buffer.
3874 #define PAL_VP_INIT_ENV 268
3879 PAL Procedure - PAL_VP_REGISTER.
3881 Register a different host IVT and/or a different optional
3882 virtualization intercept handler for the virtual processor
3883 specified by vpd. It is optional by IPF. The PAL procedure
3884 supports the Stacked Registers calling convention. It could be
3885 called at Virtual mode.
3888 @param Index Index of PAL_VP_REGISTER within the list of PAL
3891 @param Vpd 64-bit host virtual pointer to the Virtual
3892 Processor Descriptor (VPD) host_iva 64-bit host
3893 virtual pointer to the host IVT for the virtual
3896 @param OptionalHandler 64-bit non-zero host-virtual pointer
3897 to an optional handler for
3898 virtualization intercepts.
3901 @return Status 0 - Call completed without error
3903 @return Status -1 - Unimplemented procedure
3905 @return Status -2 - Invalid argument
3907 @return Status -3 - Call completed with error.
3909 @return Status -9 - Call requires PAL memory buffer.
3912 #define PAL_VP_REGISTER 269
3917 PAL Procedure - PAL_VP_RESTORE.
3919 Restores virtual processor state for the specified vpd on the
3920 logical processor. It is optional by IPF. The PAL procedure
3921 supports the Stacked Registers calling convention. It could be
3922 called at Virtual mode.
3925 @param Index Index of PAL_VP_RESTORE within the list of PAL
3928 @param Vpd 64-bit host virtual pointer to the Virtual
3929 Processor Descriptor (VPD) host_iva 64-bit host
3930 virtual pointer to the host IVT for the virtual
3933 @param PalVector Vector specifies PAL procedure
3934 implementation-specific state to be
3938 @return Status 0 - Call completed without error
3940 @return Status -1 - Unimplemented procedure
3942 @return Status -2 - Invalid argument
3944 @return Status -3 - Call completed with error.
3946 @return Status -9 - Call requires PAL memory buffer.
3949 #define PAL_VP_RESTORE 270
3953 PAL Procedure - PAL_VP_SAVE.
3955 Saves virtual processor state for the specified vpd on the
3956 logical processor. It is optional by IPF. The PAL procedure
3957 supports the Stacked Registers calling convention. It could be
3958 called at Virtual mode.
3961 @param Index Index of PAL_VP_SAVE within the list of PAL
3964 @param Vpd 64-bit host virtual pointer to the Virtual
3965 Processor Descriptor (VPD) host_iva 64-bit host
3966 virtual pointer to the host IVT for the virtual
3969 @param PalVector Vector specifies PAL procedure
3970 implementation-specific state to be
3974 @return Status 0 - Call completed without error
3976 @return Status -1 - Unimplemented procedure
3978 @return Status -2 - Invalid argument
3980 @return Status -3 - Call completed with error.
3982 @return Status -9 - Call requires PAL memory buffer.
3985 #define PAL_VP_SAVE 271
3990 PAL Procedure - PAL_VP_TERMINATE.
3992 Terminates operation for the specified virtual processor. It
3993 is optional by IPF. The PAL procedure supports the Stacked
3994 Registers calling convention. It could be called at Virtual
3998 @param Index Index of PAL_VP_TERMINATE within the list of PAL
4001 @param Vpd 64-bit host virtual pointer to the Virtual
4002 Processor Descriptor (VPD)
4004 @param Iva Optional 64-bit host virtual pointer to the IVT
4005 when this procedure is done.
4007 @return Status 0 - Call completed without error
4009 @return Status -1 - Unimplemented procedure
4011 @return Status -2 - Invalid argument
4013 @return Status -3 - Call completed with error.
4015 @return Status -9 - Call requires PAL memory buffer.
4018 #define PAL_VP_TERMINATE 272
4021 Makes a PAL procedure call.
4023 This is a wrapper function to make a PAL procedure call. Based on the Index value,
4024 this API will make static or stacked PAL call. Architected procedures may be designated
4025 as required or optional. If a PAL procedure is specified as optional, a unique return
4026 code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CALL_RETURN structure.
4027 This indicates that the procedure is not present in this PAL implementation. It is the
4028 caller¡¯s responsibility to check for this return code after calling any optional PAL
4029 procedure. No parameter checking is performed on the 4 input parameters, but there are
4030 some common rules that the caller should follow when making a PAL call. Any address
4031 passed to PAL as buffers for return parameters must be 8-byte aligned. Unaligned addresses
4032 may cause undefined results. For those parameters defined as reserved or some fields
4033 defined as reserved must be zero filled or the invalid argument return value may be
4034 returned or undefined result may occur during the execution of the procedure.
4035 This function is only available on IPF.
4037 @param Index - The PAL procedure Index number.
4038 @param Arg2 - The 2nd parameter for PAL procedure calls.
4039 @param Arg3 - The 3rd parameter for PAL procedure calls.
4040 @param Arg4 - The 4th parameter for PAL procedure calls.
4042 @return structure returned from the PAL Call procedure, including the status and return value.