MdePkg/Include/Library/PciCf8Lib.h

   1 /** @file
   2   PCI CF8 Library Services for PCI Segment #0
   3
   4   Copyright (c) 2006, Intel Corporation
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13   Module Name:  PciCf8Lib.h
  14
  15 **/
  16
  17 #ifndef __PCI_CF8_LIB_H__
  18 #define __PCI_CF8_LIB_H__
  19
  20
  21 /**
  22   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  23   address that can be passed to the PCI Library functions.
  24
  25   Computes an address that is compatible with the PCI Library functions. The
  26   unused upper bits of Bus, Device, Function and Register are stripped prior to
  27   the generation of the address.
  28
  29   @param  Bus       PCI Bus number. Range 0..255.
  30   @param  Device    PCI Device number. Range 0..31.
  31   @param  Function  PCI Function number. Range 0..7.
  32   @param  Register  PCI Register number. Range 0..255.
  33
  34   @return The encode PCI address.
  35
  36 **/
  37 #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \
  38   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  39
  40 /**
  41   Reads an 8-bit PCI configuration register.
  42
  43   Reads and returns the 8-bit PCI configuration register specified by Address.
  44   This function must guarantee that all PCI read and write operations are
  45   serialized.
  46
  47   If Address > 0x0FFFFFFF, then ASSERT().
  48   If the register specified by Address >= 0x100, then ASSERT().
  49
  50   @param  Address Address that encodes the PCI Bus, Device, Function and
  51                   Register.
  52
  53   @return The read value from the PCI configuration register.
  54
  55 **/
  56 UINT8
  57 EFIAPI
  58 PciCf8Read8 (
  59   IN      UINTN                     Address
  60   );
  61
  62 /**
  63   Writes an 8-bit PCI configuration register.
  64
  65   Writes the 8-bit PCI configuration register specified by Address with the
  66   value specified by Value. Value is returned. This function must guarantee
  67   that all PCI read and write operations are serialized.
  68
  69   If Address > 0x0FFFFFFF, then ASSERT().
  70   If the register specified by Address >= 0x100, then ASSERT().
  71
  72   @param  Address Address that encodes the PCI Bus, Device, Function and
  73                   Register.
  74   @param  Value   The value to write.
  75
  76   @return The value written to the PCI configuration register.
  77
  78 **/
  79 UINT8
  80 EFIAPI
  81 PciCf8Write8 (
  82   IN      UINTN                     Address,
  83   IN      UINT8                     Data
  84   );
  85
  86 /**
  87   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
  88   an 8-bit value.
  89
  90   Reads the 8-bit PCI configuration register specified by Address, performs a
  91   bitwise inclusive OR between the read result and the value specified by
  92   OrData, and writes the result to the 8-bit PCI configuration register
  93   specified by Address. The value written to the PCI configuration register is
  94   returned. This function must guarantee that all PCI read and write operations
  95   are serialized.
  96
  97   If Address > 0x0FFFFFFF, then ASSERT().
  98   If the register specified by Address >= 0x100, then ASSERT().
  99
 100   @param  Address Address that encodes the PCI Bus, Device, Function and
 101                   Register.
 102   @param  OrData  The value to OR with the PCI configuration register.
 103
 104   @return The value written back to the PCI configuration register.
 105
 106 **/
 107 UINT8
 108 EFIAPI
 109 PciCf8Or8 (
 110   IN      UINTN                     Address,
 111   IN      UINT8                     OrData
 112   );
 113
 114 /**
 115   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 116   value.
 117
 118   Reads the 8-bit PCI configuration register specified by Address, performs a
 119   bitwise AND between the read result and the value specified by AndData, and
 120   writes the result to the 8-bit PCI configuration register specified by
 121   Address. The value written to the PCI configuration register is returned.
 122   This function must guarantee that all PCI read and write operations are
 123   serialized.
 124
 125   If Address > 0x0FFFFFFF, then ASSERT().
 126   If the register specified by Address >= 0x100, then ASSERT().
 127
 128   @param  Address Address that encodes the PCI Bus, Device, Function and
 129                   Register.
 130   @param  AndData The value to AND with the PCI configuration register.
 131
 132   @return The value written back to the PCI configuration register.
 133
 134 **/
 135 UINT8
 136 EFIAPI
 137 PciCf8And8 (
 138   IN      UINTN                     Address,
 139   IN      UINT8                     AndData
 140   );
 141
 142 /**
 143   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 144   value, followed a  bitwise inclusive OR with another 8-bit value.
 145
 146   Reads the 8-bit PCI configuration register specified by Address, performs a
 147   bitwise AND between the read result and the value specified by AndData,
 148   performs a bitwise inclusive OR between the result of the AND operation and
 149   the value specified by OrData, and writes the result to the 8-bit PCI
 150   configuration register specified by Address. The value written to the PCI
 151   configuration register is returned. This function must guarantee that all PCI
 152   read and write operations are serialized.
 153
 154   If Address > 0x0FFFFFFF, then ASSERT().
 155   If the register specified by Address >= 0x100, then ASSERT().
 156
 157   @param  Address Address that encodes the PCI Bus, Device, Function and
 158                   Register.
 159   @param  AndData The value to AND with the PCI configuration register.
 160   @param  OrData  The value to OR with the result of the AND operation.
 161
 162   @return The value written back to the PCI configuration register.
 163
 164 **/
 165 UINT8
 166 EFIAPI
 167 PciCf8AndThenOr8 (
 168   IN      UINTN                     Address,
 169   IN      UINT8                     AndData,
 170   IN      UINT8                     OrData
 171   );
 172
 173 /**
 174   Reads a bit field of a PCI configuration register.
 175
 176   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 177   specified by the StartBit and the EndBit. The value of the bit field is
 178   returned.
 179
 180   If Address > 0x0FFFFFFF, then ASSERT().
 181   If the register specified by Address >= 0x100, then ASSERT().
 182   If StartBit is greater than 7, then ASSERT().
 183   If EndBit is greater than 7, then ASSERT().
 184   If EndBit is less than StartBit, then ASSERT().
 185
 186   @param  Address   PCI configuration register to read.
 187   @param  StartBit  The ordinal of the least significant bit in the bit field.
 188                     Range 0..7.
 189   @param  EndBit    The ordinal of the most significant bit in the bit field.
 190                     Range 0..7.
 191
 192   @return The value of the bit field read from the PCI configuration register.
 193
 194 **/
 195 UINT8
 196 EFIAPI
 197 PciCf8BitFieldRead8 (
 198   IN      UINTN                     Address,
 199   IN      UINTN                     StartBit,
 200   IN      UINTN                     EndBit
 201   );
 202
 203 /**
 204   Writes a bit field to a PCI configuration register.
 205
 206   Writes Value to the bit field of the PCI configuration register. The bit
 207   field is specified by the StartBit and the EndBit. All other bits in the
 208   destination PCI configuration register are preserved. The new value of the
 209   8-bit register is returned.
 210
 211   If Address > 0x0FFFFFFF, then ASSERT().
 212   If the register specified by Address >= 0x100, then ASSERT().
 213   If StartBit is greater than 7, then ASSERT().
 214   If EndBit is greater than 7, then ASSERT().
 215   If EndBit is less than StartBit, then ASSERT().
 216
 217   @param  Address   PCI configuration register to write.
 218   @param  StartBit  The ordinal of the least significant bit in the bit field.
 219                     Range 0..7.
 220   @param  EndBit    The ordinal of the most significant bit in the bit field.
 221                     Range 0..7.
 222   @param  Value     New value of the bit field.
 223
 224   @return The value written back to the PCI configuration register.
 225
 226 **/
 227 UINT8
 228 EFIAPI
 229 PciCf8BitFieldWrite8 (
 230   IN      UINTN                     Address,
 231   IN      UINTN                     StartBit,
 232   IN      UINTN                     EndBit,
 233   IN      UINT8                     Value
 234   );
 235
 236 /**
 237   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 238   writes the result back to the bit field in the 8-bit port.
 239
 240   Reads the 8-bit PCI configuration register specified by Address, performs a
 241   bitwise inclusive OR between the read result and the value specified by
 242   OrData, and writes the result to the 8-bit PCI configuration register
 243   specified by Address. The value written to the PCI configuration register is
 244   returned. This function must guarantee that all PCI read and write operations
 245   are serialized. Extra left bits in OrData are stripped.
 246
 247   If Address > 0x0FFFFFFF, then ASSERT().
 248   If the register specified by Address >= 0x100, then ASSERT().
 249   If StartBit is greater than 7, then ASSERT().
 250   If EndBit is greater than 7, then ASSERT().
 251   If EndBit is less than StartBit, then ASSERT().
 252
 253   @param  Address   PCI configuration register to write.
 254   @param  StartBit  The ordinal of the least significant bit in the bit field.
 255                     Range 0..7.
 256   @param  EndBit    The ordinal of the most significant bit in the bit field.
 257                     Range 0..7.
 258   @param  OrData    The value to OR with the PCI configuration register.
 259
 260   @return The value written back to the PCI configuration register.
 261
 262 **/
 263 UINT8
 264 EFIAPI
 265 PciCf8BitFieldOr8 (
 266   IN      UINTN                     Address,
 267   IN      UINTN                     StartBit,
 268   IN      UINTN                     EndBit,
 269   IN      UINT8                     OrData
 270   );
 271
 272 /**
 273   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 274   AND, and writes the result back to the bit field in the 8-bit register.
 275
 276   Reads the 8-bit PCI configuration register specified by Address, performs a
 277   bitwise AND between the read result and the value specified by AndData, and
 278   writes the result to the 8-bit PCI configuration register specified by
 279   Address. The value written to the PCI configuration register is returned.
 280   This function must guarantee that all PCI read and write operations are
 281   serialized. Extra left bits in AndData are stripped.
 282
 283   If Address > 0x0FFFFFFF, then ASSERT().
 284   If the register specified by Address >= 0x100, then ASSERT().
 285   If StartBit is greater than 7, then ASSERT().
 286   If EndBit is greater than 7, then ASSERT().
 287   If EndBit is less than StartBit, then ASSERT().
 288
 289   @param  Address   PCI configuration register to write.
 290   @param  StartBit  The ordinal of the least significant bit in the bit field.
 291                     Range 0..7.
 292   @param  EndBit    The ordinal of the most significant bit in the bit field.
 293                     Range 0..7.
 294   @param  AndData   The value to AND with the PCI configuration register.
 295
 296   @return The value written back to the PCI configuration register.
 297
 298 **/
 299 UINT8
 300 EFIAPI
 301 PciCf8BitFieldAnd8 (
 302   IN      UINTN                     Address,
 303   IN      UINTN                     StartBit,
 304   IN      UINTN                     EndBit,
 305   IN      UINT8                     AndData
 306   );
 307
 308 /**
 309   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 310   bitwise inclusive OR, and writes the result back to the bit field in the
 311   8-bit port.
 312
 313   Reads the 8-bit PCI configuration register specified by Address, performs a
 314   bitwise AND followed by a bitwise inclusive OR between the read result and
 315   the value specified by AndData, and writes the result to the 8-bit PCI
 316   configuration register specified by Address. The value written to the PCI
 317   configuration register is returned. This function must guarantee that all PCI
 318   read and write operations are serialized. Extra left bits in both AndData and
 319   OrData are stripped.
 320
 321   If Address > 0x0FFFFFFF, then ASSERT().
 322   If the register specified by Address >= 0x100, then ASSERT().
 323   If StartBit is greater than 7, then ASSERT().
 324   If EndBit is greater than 7, then ASSERT().
 325   If EndBit is less than StartBit, then ASSERT().
 326
 327   @param  Address   PCI configuration register to write.
 328   @param  StartBit  The ordinal of the least significant bit in the bit field.
 329                     Range 0..7.
 330   @param  EndBit    The ordinal of the most significant bit in the bit field.
 331                     Range 0..7.
 332   @param  AndData   The value to AND with the PCI configuration register.
 333   @param  OrData    The value to OR with the result of the AND operation.
 334
 335   @return The value written back to the PCI configuration register.
 336
 337 **/
 338 UINT8
 339 EFIAPI
 340 PciCf8BitFieldAndThenOr8 (
 341   IN      UINTN                     Address,
 342   IN      UINTN                     StartBit,
 343   IN      UINTN                     EndBit,
 344   IN      UINT8                     AndData,
 345   IN      UINT8                     OrData
 346   );
 347
 348 /**
 349   Reads a 16-bit PCI configuration register.
 350
 351   Reads and returns the 16-bit PCI configuration register specified by Address.
 352   This function must guarantee that all PCI read and write operations are
 353   serialized.
 354
 355   If Address > 0x0FFFFFFF, then ASSERT().
 356   If Address is not aligned on a 16-bit boundary, then ASSERT().
 357   If the register specified by Address >= 0x100, then ASSERT().
 358
 359   @param  Address Address that encodes the PCI Bus, Device, Function and
 360                   Register.
 361
 362   @return The read value from the PCI configuration register.
 363
 364 **/
 365 UINT16
 366 EFIAPI
 367 PciCf8Read16 (
 368   IN      UINTN                     Address
 369   );
 370
 371 /**
 372   Writes a 16-bit PCI configuration register.
 373
 374   Writes the 16-bit PCI configuration register specified by Address with the
 375   value specified by Value. Value is returned. This function must guarantee
 376   that all PCI read and write operations are serialized.
 377
 378   If Address > 0x0FFFFFFF, then ASSERT().
 379   If Address is not aligned on a 16-bit boundary, then ASSERT().
 380   If the register specified by Address >= 0x100, then ASSERT().
 381
 382   @param  Address Address that encodes the PCI Bus, Device, Function and
 383                   Register.
 384   @param  Value   The value to write.
 385
 386   @return The value written to the PCI configuration register.
 387
 388 **/
 389 UINT16
 390 EFIAPI
 391 PciCf8Write16 (
 392   IN      UINTN                     Address,
 393   IN      UINT16                    Data
 394   );
 395
 396 /**
 397   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 398   a 16-bit value.
 399
 400   Reads the 16-bit PCI configuration register specified by Address, performs a
 401   bitwise inclusive OR between the read result and the value specified by
 402   OrData, and writes the result to the 16-bit PCI configuration register
 403   specified by Address. The value written to the PCI configuration register is
 404   returned. This function must guarantee that all PCI read and write operations
 405   are serialized.
 406
 407   If Address > 0x0FFFFFFF, then ASSERT().
 408   If Address is not aligned on a 16-bit boundary, then ASSERT().
 409   If the register specified by Address >= 0x100, then ASSERT().
 410
 411   @param  Address Address that encodes the PCI Bus, Device, Function and
 412                   Register.
 413   @param  OrData  The value to OR with the PCI configuration register.
 414
 415   @return The value written back to the PCI configuration register.
 416
 417 **/
 418 UINT16
 419 EFIAPI
 420 PciCf8Or16 (
 421   IN      UINTN                     Address,
 422   IN      UINT16                    OrData
 423   );
 424
 425 /**
 426   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 427   value.
 428
 429   Reads the 16-bit PCI configuration register specified by Address, performs a
 430   bitwise AND between the read result and the value specified by AndData, and
 431   writes the result to the 16-bit PCI configuration register specified by
 432   Address. The value written to the PCI configuration register is returned.
 433   This function must guarantee that all PCI read and write operations are
 434   serialized.
 435
 436   If Address > 0x0FFFFFFF, then ASSERT().
 437   If Address is not aligned on a 16-bit boundary, then ASSERT().
 438   If the register specified by Address >= 0x100, then ASSERT().
 439
 440   @param  Address Address that encodes the PCI Bus, Device, Function and
 441                   Register.
 442   @param  AndData The value to AND with the PCI configuration register.
 443
 444   @return The value written back to the PCI configuration register.
 445
 446 **/
 447 UINT16
 448 EFIAPI
 449 PciCf8And16 (
 450   IN      UINTN                     Address,
 451   IN      UINT16                    AndData
 452   );
 453
 454 /**
 455   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 456   value, followed a  bitwise inclusive OR with another 16-bit value.
 457
 458   Reads the 16-bit PCI configuration register specified by Address, performs a
 459   bitwise AND between the read result and the value specified by AndData,
 460   performs a bitwise inclusive OR between the result of the AND operation and
 461   the value specified by OrData, and writes the result to the 16-bit PCI
 462   configuration register specified by Address. The value written to the PCI
 463   configuration register is returned. This function must guarantee that all PCI
 464   read and write operations are serialized.
 465
 466   If Address > 0x0FFFFFFF, then ASSERT().
 467   If Address is not aligned on a 16-bit boundary, then ASSERT().
 468   If the register specified by Address >= 0x100, then ASSERT().
 469
 470   @param  Address Address that encodes the PCI Bus, Device, Function and
 471                   Register.
 472   @param  AndData The value to AND with the PCI configuration register.
 473   @param  OrData  The value to OR with the result of the AND operation.
 474
 475   @return The value written back to the PCI configuration register.
 476
 477 **/
 478 UINT16
 479 EFIAPI
 480 PciCf8AndThenOr16 (
 481   IN      UINTN                     Address,
 482   IN      UINT16                    AndData,
 483   IN      UINT16                    OrData
 484   );
 485
 486 /**
 487   Reads a bit field of a PCI configuration register.
 488
 489   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 490   specified by the StartBit and the EndBit. The value of the bit field is
 491   returned.
 492
 493   If Address > 0x0FFFFFFF, then ASSERT().
 494   If Address is not aligned on a 16-bit boundary, then ASSERT().
 495   If the register specified by Address >= 0x100, then ASSERT().
 496   If StartBit is greater than 15, then ASSERT().
 497   If EndBit is greater than 15, then ASSERT().
 498   If EndBit is less than StartBit, then ASSERT().
 499
 500   @param  Address   PCI configuration register to read.
 501   @param  StartBit  The ordinal of the least significant bit in the bit field.
 502                     Range 0..15.
 503   @param  EndBit    The ordinal of the most significant bit in the bit field.
 504                     Range 0..15.
 505
 506   @return The value of the bit field read from the PCI configuration register.
 507
 508 **/
 509 UINT16
 510 EFIAPI
 511 PciCf8BitFieldRead16 (
 512   IN      UINTN                     Address,
 513   IN      UINTN                     StartBit,
 514   IN      UINTN                     EndBit
 515   );
 516
 517 /**
 518   Writes a bit field to a PCI configuration register.
 519
 520   Writes Value to the bit field of the PCI configuration register. The bit
 521   field is specified by the StartBit and the EndBit. All other bits in the
 522   destination PCI configuration register are preserved. The new value of the
 523   16-bit register is returned.
 524
 525   If Address > 0x0FFFFFFF, then ASSERT().
 526   If Address is not aligned on a 16-bit boundary, then ASSERT().
 527   If the register specified by Address >= 0x100, then ASSERT().
 528   If StartBit is greater than 15, then ASSERT().
 529   If EndBit is greater than 15, then ASSERT().
 530   If EndBit is less than StartBit, then ASSERT().
 531
 532   @param  Address   PCI configuration register to write.
 533   @param  StartBit  The ordinal of the least significant bit in the bit field.
 534                     Range 0..15.
 535   @param  EndBit    The ordinal of the most significant bit in the bit field.
 536                     Range 0..15.
 537   @param  Value     New value of the bit field.
 538
 539   @return The value written back to the PCI configuration register.
 540
 541 **/
 542 UINT16
 543 EFIAPI
 544 PciCf8BitFieldWrite16 (
 545   IN      UINTN                     Address,
 546   IN      UINTN                     StartBit,
 547   IN      UINTN                     EndBit,
 548   IN      UINT16                    Value
 549   );
 550
 551 /**
 552   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 553   writes the result back to the bit field in the 16-bit port.
 554
 555   Reads the 16-bit PCI configuration register specified by Address, performs a
 556   bitwise inclusive OR between the read result and the value specified by
 557   OrData, and writes the result to the 16-bit PCI configuration register
 558   specified by Address. The value written to the PCI configuration register is
 559   returned. This function must guarantee that all PCI read and write operations
 560   are serialized. Extra left bits in OrData are stripped.
 561
 562   If Address > 0x0FFFFFFF, then ASSERT().
 563   If Address is not aligned on a 16-bit boundary, then ASSERT().
 564   If the register specified by Address >= 0x100, then ASSERT().
 565   If StartBit is greater than 15, then ASSERT().
 566   If EndBit is greater than 15, then ASSERT().
 567   If EndBit is less than StartBit, then ASSERT().
 568
 569   @param  Address   PCI configuration register to write.
 570   @param  StartBit  The ordinal of the least significant bit in the bit field.
 571                     Range 0..15.
 572   @param  EndBit    The ordinal of the most significant bit in the bit field.
 573                     Range 0..15.
 574   @param  OrData    The value to OR with the PCI configuration register.
 575
 576   @return The value written back to the PCI configuration register.
 577
 578 **/
 579 UINT16
 580 EFIAPI
 581 PciCf8BitFieldOr16 (
 582   IN      UINTN                     Address,
 583   IN      UINTN                     StartBit,
 584   IN      UINTN                     EndBit,
 585   IN      UINT16                    OrData
 586   );
 587
 588 /**
 589   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 590   AND, and writes the result back to the bit field in the 16-bit register.
 591
 592   Reads the 16-bit PCI configuration register specified by Address, performs a
 593   bitwise AND between the read result and the value specified by AndData, and
 594   writes the result to the 16-bit PCI configuration register specified by
 595   Address. The value written to the PCI configuration register is returned.
 596   This function must guarantee that all PCI read and write operations are
 597   serialized. Extra left bits in AndData are stripped.
 598
 599   If Address > 0x0FFFFFFF, then ASSERT().
 600   If Address is not aligned on a 16-bit boundary, then ASSERT().
 601   If the register specified by Address >= 0x100, then ASSERT().
 602   If StartBit is greater than 15, then ASSERT().
 603   If EndBit is greater than 15, then ASSERT().
 604   If EndBit is less than StartBit, then ASSERT().
 605
 606   @param  Address   PCI configuration register to write.
 607   @param  StartBit  The ordinal of the least significant bit in the bit field.
 608                     Range 0..15.
 609   @param  EndBit    The ordinal of the most significant bit in the bit field.
 610                     Range 0..15.
 611   @param  AndData   The value to AND with the PCI configuration register.
 612
 613   @return The value written back to the PCI configuration register.
 614
 615 **/
 616 UINT16
 617 EFIAPI
 618 PciCf8BitFieldAnd16 (
 619   IN      UINTN                     Address,
 620   IN      UINTN                     StartBit,
 621   IN      UINTN                     EndBit,
 622   IN      UINT16                    AndData
 623   );
 624
 625 /**
 626   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 627   bitwise inclusive OR, and writes the result back to the bit field in the
 628   16-bit port.
 629
 630   Reads the 16-bit PCI configuration register specified by Address, performs a
 631   bitwise AND followed by a bitwise inclusive OR between the read result and
 632   the value specified by AndData, and writes the result to the 16-bit PCI
 633   configuration register specified by Address. The value written to the PCI
 634   configuration register is returned. This function must guarantee that all PCI
 635   read and write operations are serialized. Extra left bits in both AndData and
 636   OrData are stripped.
 637
 638   If Address > 0x0FFFFFFF, then ASSERT().
 639   If Address is not aligned on a 16-bit boundary, then ASSERT().
 640   If the register specified by Address >= 0x100, then ASSERT().
 641   If StartBit is greater than 15, then ASSERT().
 642   If EndBit is greater than 15, then ASSERT().
 643   If EndBit is less than StartBit, then ASSERT().
 644
 645   @param  Address   PCI configuration register to write.
 646   @param  StartBit  The ordinal of the least significant bit in the bit field.
 647                     Range 0..15.
 648   @param  EndBit    The ordinal of the most significant bit in the bit field.
 649                     Range 0..15.
 650   @param  AndData   The value to AND with the PCI configuration register.
 651   @param  OrData    The value to OR with the result of the AND operation.
 652
 653   @return The value written back to the PCI configuration register.
 654
 655 **/
 656 UINT16
 657 EFIAPI
 658 PciCf8BitFieldAndThenOr16 (
 659   IN      UINTN                     Address,
 660   IN      UINTN                     StartBit,
 661   IN      UINTN                     EndBit,
 662   IN      UINT16                    AndData,
 663   IN      UINT16                    OrData
 664   );
 665
 666 /**
 667   Reads a 32-bit PCI configuration register.
 668
 669   Reads and returns the 32-bit PCI configuration register specified by Address.
 670   This function must guarantee that all PCI read and write operations are
 671   serialized.
 672
 673   If Address > 0x0FFFFFFF, then ASSERT().
 674   If Address is not aligned on a 32-bit boundary, then ASSERT().
 675   If the register specified by Address >= 0x100, then ASSERT().
 676
 677   @param  Address Address that encodes the PCI Bus, Device, Function and
 678                   Register.
 679
 680   @return The read value from the PCI configuration register.
 681
 682 **/
 683 UINT32
 684 EFIAPI
 685 PciCf8Read32 (
 686   IN      UINTN                     Address
 687   );
 688
 689 /**
 690   Writes a 32-bit PCI configuration register.
 691
 692   Writes the 32-bit PCI configuration register specified by Address with the
 693   value specified by Value. Value is returned. This function must guarantee
 694   that all PCI read and write operations are serialized.
 695
 696   If Address > 0x0FFFFFFF, then ASSERT().
 697   If Address is not aligned on a 32-bit boundary, then ASSERT().
 698   If the register specified by Address >= 0x100, then ASSERT().
 699
 700   @param  Address Address that encodes the PCI Bus, Device, Function and
 701                   Register.
 702   @param  Value   The value to write.
 703
 704   @return The value written to the PCI configuration register.
 705
 706 **/
 707 UINT32
 708 EFIAPI
 709 PciCf8Write32 (
 710   IN      UINTN                     Address,
 711   IN      UINT32                    Data
 712   );
 713
 714 /**
 715   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 716   a 32-bit value.
 717
 718   Reads the 32-bit PCI configuration register specified by Address, performs a
 719   bitwise inclusive OR between the read result and the value specified by
 720   OrData, and writes the result to the 32-bit PCI configuration register
 721   specified by Address. The value written to the PCI configuration register is
 722   returned. This function must guarantee that all PCI read and write operations
 723   are serialized.
 724
 725   If Address > 0x0FFFFFFF, then ASSERT().
 726   If Address is not aligned on a 32-bit boundary, then ASSERT().
 727   If the register specified by Address >= 0x100, then ASSERT().
 728
 729   @param  Address Address that encodes the PCI Bus, Device, Function and
 730                   Register.
 731   @param  OrData  The value to OR with the PCI configuration register.
 732
 733   @return The value written back to the PCI configuration register.
 734
 735 **/
 736 UINT32
 737 EFIAPI
 738 PciCf8Or32 (
 739   IN      UINTN                     Address,
 740   IN      UINT32                    OrData
 741   );
 742
 743 /**
 744   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 745   value.
 746
 747   Reads the 32-bit PCI configuration register specified by Address, performs a
 748   bitwise AND between the read result and the value specified by AndData, and
 749   writes the result to the 32-bit PCI configuration register specified by
 750   Address. The value written to the PCI configuration register is returned.
 751   This function must guarantee that all PCI read and write operations are
 752   serialized.
 753
 754   If Address > 0x0FFFFFFF, then ASSERT().
 755   If Address is not aligned on a 32-bit boundary, then ASSERT().
 756   If the register specified by Address >= 0x100, then ASSERT().
 757
 758   @param  Address Address that encodes the PCI Bus, Device, Function and
 759                   Register.
 760   @param  AndData The value to AND with the PCI configuration register.
 761
 762   @return The value written back to the PCI configuration register.
 763
 764 **/
 765 UINT32
 766 EFIAPI
 767 PciCf8And32 (
 768   IN      UINTN                     Address,
 769   IN      UINT32                    AndData
 770   );
 771
 772 /**
 773   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 774   value, followed a  bitwise inclusive OR with another 32-bit value.
 775
 776   Reads the 32-bit PCI configuration register specified by Address, performs a
 777   bitwise AND between the read result and the value specified by AndData,
 778   performs a bitwise inclusive OR between the result of the AND operation and
 779   the value specified by OrData, and writes the result to the 32-bit PCI
 780   configuration register specified by Address. The value written to the PCI
 781   configuration register is returned. This function must guarantee that all PCI
 782   read and write operations are serialized.
 783
 784   If Address > 0x0FFFFFFF, then ASSERT().
 785   If Address is not aligned on a 32-bit boundary, then ASSERT().
 786   If the register specified by Address >= 0x100, then ASSERT().
 787
 788   @param  Address Address that encodes the PCI Bus, Device, Function and
 789                   Register.
 790   @param  AndData The value to AND with the PCI configuration register.
 791   @param  OrData  The value to OR with the result of the AND operation.
 792
 793   @return The value written back to the PCI configuration register.
 794
 795 **/
 796 UINT32
 797 EFIAPI
 798 PciCf8AndThenOr32 (
 799   IN      UINTN                     Address,
 800   IN      UINT32                    AndData,
 801   IN      UINT32                    OrData
 802   );
 803
 804 /**
 805   Reads a bit field of a PCI configuration register.
 806
 807   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 808   specified by the StartBit and the EndBit. The value of the bit field is
 809   returned.
 810
 811   If Address > 0x0FFFFFFF, then ASSERT().
 812   If Address is not aligned on a 32-bit boundary, then ASSERT().
 813   If the register specified by Address >= 0x100, then ASSERT().
 814   If StartBit is greater than 31, then ASSERT().
 815   If EndBit is greater than 31, then ASSERT().
 816   If EndBit is less than StartBit, then ASSERT().
 817
 818   @param  Address   PCI configuration register to read.
 819   @param  StartBit  The ordinal of the least significant bit in the bit field.
 820                     Range 0..31.
 821   @param  EndBit    The ordinal of the most significant bit in the bit field.
 822                     Range 0..31.
 823
 824   @return The value of the bit field read from the PCI configuration register.
 825
 826 **/
 827 UINT32
 828 EFIAPI
 829 PciCf8BitFieldRead32 (
 830   IN      UINTN                     Address,
 831   IN      UINTN                     StartBit,
 832   IN      UINTN                     EndBit
 833   );
 834
 835 /**
 836   Writes a bit field to a PCI configuration register.
 837
 838   Writes Value to the bit field of the PCI configuration register. The bit
 839   field is specified by the StartBit and the EndBit. All other bits in the
 840   destination PCI configuration register are preserved. The new value of the
 841   32-bit register is returned.
 842
 843   If Address > 0x0FFFFFFF, then ASSERT().
 844   If Address is not aligned on a 32-bit boundary, then ASSERT().
 845   If the register specified by Address >= 0x100, then ASSERT().
 846   If StartBit is greater than 31, then ASSERT().
 847   If EndBit is greater than 31, then ASSERT().
 848   If EndBit is less than StartBit, then ASSERT().
 849
 850   @param  Address   PCI configuration register to write.
 851   @param  StartBit  The ordinal of the least significant bit in the bit field.
 852                     Range 0..31.
 853   @param  EndBit    The ordinal of the most significant bit in the bit field.
 854                     Range 0..31.
 855   @param  Value     New value of the bit field.
 856
 857   @return The value written back to the PCI configuration register.
 858
 859 **/
 860 UINT32
 861 EFIAPI
 862 PciCf8BitFieldWrite32 (
 863   IN      UINTN                     Address,
 864   IN      UINTN                     StartBit,
 865   IN      UINTN                     EndBit,
 866   IN      UINT32                    Value
 867   );
 868
 869 /**
 870   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 871   writes the result back to the bit field in the 32-bit port.
 872
 873   Reads the 32-bit PCI configuration register specified by Address, performs a
 874   bitwise inclusive OR between the read result and the value specified by
 875   OrData, and writes the result to the 32-bit PCI configuration register
 876   specified by Address. The value written to the PCI configuration register is
 877   returned. This function must guarantee that all PCI read and write operations
 878   are serialized. Extra left bits in OrData are stripped.
 879
 880   If Address > 0x0FFFFFFF, then ASSERT().
 881   If Address is not aligned on a 32-bit boundary, then ASSERT().
 882   If the register specified by Address >= 0x100, then ASSERT().
 883   If StartBit is greater than 31, then ASSERT().
 884   If EndBit is greater than 31, then ASSERT().
 885   If EndBit is less than StartBit, then ASSERT().
 886
 887   @param  Address   PCI configuration register to write.
 888   @param  StartBit  The ordinal of the least significant bit in the bit field.
 889                     Range 0..31.
 890   @param  EndBit    The ordinal of the most significant bit in the bit field.
 891                     Range 0..31.
 892   @param  OrData    The value to OR with the PCI configuration register.
 893
 894   @return The value written back to the PCI configuration register.
 895
 896 **/
 897 UINT32
 898 EFIAPI
 899 PciCf8BitFieldOr32 (
 900   IN      UINTN                     Address,
 901   IN      UINTN                     StartBit,
 902   IN      UINTN                     EndBit,
 903   IN      UINT32                    OrData
 904   );
 905
 906 /**
 907   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 908   AND, and writes the result back to the bit field in the 32-bit register.
 909
 910   Reads the 32-bit PCI configuration register specified by Address, performs a
 911   bitwise AND between the read result and the value specified by AndData, and
 912   writes the result to the 32-bit PCI configuration register specified by
 913   Address. The value written to the PCI configuration register is returned.
 914   This function must guarantee that all PCI read and write operations are
 915   serialized. Extra left bits in AndData are stripped.
 916
 917   If Address > 0x0FFFFFFF, then ASSERT().
 918   If Address is not aligned on a 32-bit boundary, then ASSERT().
 919   If the register specified by Address >= 0x100, then ASSERT().
 920   If StartBit is greater than 31, then ASSERT().
 921   If EndBit is greater than 31, then ASSERT().
 922   If EndBit is less than StartBit, then ASSERT().
 923
 924   @param  Address   PCI configuration register to write.
 925   @param  StartBit  The ordinal of the least significant bit in the bit field.
 926                     Range 0..31.
 927   @param  EndBit    The ordinal of the most significant bit in the bit field.
 928                     Range 0..31.
 929   @param  AndData   The value to AND with the PCI configuration register.
 930
 931   @return The value written back to the PCI configuration register.
 932
 933 **/
 934 UINT32
 935 EFIAPI
 936 PciCf8BitFieldAnd32 (
 937   IN      UINTN                     Address,
 938   IN      UINTN                     StartBit,
 939   IN      UINTN                     EndBit,
 940   IN      UINT32                    AndData
 941   );
 942
 943 /**
 944   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 945   bitwise inclusive OR, and writes the result back to the bit field in the
 946   32-bit port.
 947
 948   Reads the 32-bit PCI configuration register specified by Address, performs a
 949   bitwise AND followed by a bitwise inclusive OR between the read result and
 950   the value specified by AndData, and writes the result to the 32-bit PCI
 951   configuration register specified by Address. The value written to the PCI
 952   configuration register is returned. This function must guarantee that all PCI
 953   read and write operations are serialized. Extra left bits in both AndData and
 954   OrData are stripped.
 955
 956   If Address > 0x0FFFFFFF, then ASSERT().
 957   If Address is not aligned on a 32-bit boundary, then ASSERT().
 958   If the register specified by Address >= 0x100, then ASSERT().
 959   If StartBit is greater than 31, then ASSERT().
 960   If EndBit is greater than 31, then ASSERT().
 961   If EndBit is less than StartBit, then ASSERT().
 962
 963   @param  Address   PCI configuration register to write.
 964   @param  StartBit  The ordinal of the least significant bit in the bit field.
 965                     Range 0..31.
 966   @param  EndBit    The ordinal of the most significant bit in the bit field.
 967                     Range 0..31.
 968   @param  AndData   The value to AND with the PCI configuration register.
 969   @param  OrData    The value to OR with the result of the AND operation.
 970
 971   @return The value written back to the PCI configuration register.
 972
 973 **/
 974 UINT32
 975 EFIAPI
 976 PciCf8BitFieldAndThenOr32 (
 977   IN      UINTN                     Address,
 978   IN      UINTN                     StartBit,
 979   IN      UINTN                     EndBit,
 980   IN      UINT32                    AndData,
 981   IN      UINT32                    OrData
 982   );
 983
 984 /**
 985   Reads a range of PCI configuration registers into a caller supplied buffer.
 986
 987   Reads the range of PCI configuration registers specified by StartAddress and
 988   Size into the buffer specified by Buffer. This function only allows the PCI
 989   configuration registers from a single PCI function to be read. Size is
 990   returned. When possible 32-bit PCI configuration read cycles are used to read
 991   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
 992   and 16-bit PCI configuration read cycles may be used at the beginning and the
 993   end of the range.
 994
 995   If StartAddress > 0x0FFFFFFF, then ASSERT().
 996   If the register specified by StartAddress >= 0x100, then ASSERT().
 997   If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
 998   If Size > 0 and Buffer is NULL, then ASSERT().
 999
1000   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1001                         Function and Register.
1002   @param  Size          Size in bytes of the transfer.
1003   @param  Buffer        Pointer to a buffer receiving the data read.
1004
1005   @return Size
1006
1007 **/
1008 UINTN
1009 EFIAPI
1010 PciCf8ReadBuffer (
1011   IN      UINTN                     StartAddress,
1012   IN      UINTN                     Size,
1013   OUT     VOID                      *Buffer
1014   );
1015
1016 /**
1017   Copies the data in a caller supplied buffer to a specified range of PCI
1018   configuration space.
1019
1020   Writes the range of PCI configuration registers specified by StartAddress and
1021   Size from the buffer specified by Buffer. This function only allows the PCI
1022   configuration registers from a single PCI function to be written. Size is
1023   returned. When possible 32-bit PCI configuration write cycles are used to
1024   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1025   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1026   and the end of the range.
1027
1028   If StartAddress > 0x0FFFFFFF, then ASSERT().
1029   If the register specified by StartAddress >= 0x100, then ASSERT().
1030   If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1031   If Size > 0 and Buffer is NULL, then ASSERT().
1032
1033   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1034                         Function and Register.
1035   @param  Size          Size in bytes of the transfer.
1036   @param  Buffer        Pointer to a buffer containing the data to write.
1037
1038   @return Size
1039
1040 **/
1041 UINTN
1042 EFIAPI
1043 PciCf8WriteBuffer (
1044   IN      UINTN                     StartAddress,
1045   IN      UINTN                     Size,
1046   IN      VOID                      *Buffer
1047   );
1048
1049 #endif