MdePkg/Include/Library/PciCf8Lib.h

   1 /** @file
   2   PCI CF8 Library Services for PCI Segment #0
   3
   4   Copyright (c) 2006 - 2008, Intel Corporation
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef __PCI_CF8_LIB_H__
  16 #define __PCI_CF8_LIB_H__
  17
  18
  19 /**
  20   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  21   address that can be passed to the PCI Library functions.
  22
  23   Computes an address that is compatible with the PCI Library functions. The
  24   unused upper bits of Bus, Device, Function and Register are stripped prior to
  25   the generation of the address.
  26
  27   @param  Bus       PCI Bus number. Range 0..255.
  28   @param  Device    PCI Device number. Range 0..31.
  29   @param  Function  PCI Function number. Range 0..7.
  30   @param  Register  PCI Register number. Range 0..255.
  31
  32   @return The encode PCI address.
  33
  34 **/
  35 #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \
  36   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  37
  38 /**
  39   Reads an 8-bit PCI configuration register.
  40
  41   Reads and returns the 8-bit PCI configuration register specified by Address.
  42   This function must guarantee that all PCI read and write operations are
  43   serialized.
  44
  45   If Address > 0x0FFFFFFF, then ASSERT().
  46   If the register specified by Address >= 0x100, then ASSERT().
  47
  48   @param  Address Address that encodes the PCI Bus, Device, Function and
  49                   Register.
  50
  51   @return The read value from the PCI configuration register.
  52
  53 **/
  54 UINT8
  55 EFIAPI
  56 PciCf8Read8 (
  57   IN      UINTN                     Address
  58   );
  59
  60 /**
  61   Writes an 8-bit PCI configuration register.
  62
  63   Writes the 8-bit PCI configuration register specified by Address with the
  64   value specified by Value. Value is returned. This function must guarantee
  65   that all PCI read and write operations are serialized.
  66
  67   If Address > 0x0FFFFFFF, then ASSERT().
  68   If the register specified by Address >= 0x100, then ASSERT().
  69
  70   @param  Address Address that encodes the PCI Bus, Device, Function and
  71                   Register.
  72   @param  Value   The value to write.
  73
  74   @return The value written to the PCI configuration register.
  75
  76 **/
  77 UINT8
  78 EFIAPI
  79 PciCf8Write8 (
  80   IN      UINTN                     Address,
  81   IN      UINT8                     Value
  82   );
  83
  84 /**
  85   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
  86   an 8-bit value.
  87
  88   Reads the 8-bit PCI configuration register specified by Address, performs a
  89   bitwise inclusive OR between the read result and the value specified by
  90   OrData, and writes the result to the 8-bit PCI configuration register
  91   specified by Address. The value written to the PCI configuration register is
  92   returned. This function must guarantee that all PCI read and write operations
  93   are serialized.
  94
  95   If Address > 0x0FFFFFFF, then ASSERT().
  96   If the register specified by Address >= 0x100, then ASSERT().
  97
  98   @param  Address Address that encodes the PCI Bus, Device, Function and
  99                   Register.
 100   @param  OrData  The value to OR with the PCI configuration register.
 101
 102   @return The value written back to the PCI configuration register.
 103
 104 **/
 105 UINT8
 106 EFIAPI
 107 PciCf8Or8 (
 108   IN      UINTN                     Address,
 109   IN      UINT8                     OrData
 110   );
 111
 112 /**
 113   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 114   value.
 115
 116   Reads the 8-bit PCI configuration register specified by Address, performs a
 117   bitwise AND between the read result and the value specified by AndData, and
 118   writes the result to the 8-bit PCI configuration register specified by
 119   Address. The value written to the PCI configuration register is returned.
 120   This function must guarantee that all PCI read and write operations are
 121   serialized.
 122
 123   If Address > 0x0FFFFFFF, then ASSERT().
 124   If the register specified by Address >= 0x100, then ASSERT().
 125
 126   @param  Address Address that encodes the PCI Bus, Device, Function and
 127                   Register.
 128   @param  AndData The value to AND with the PCI configuration register.
 129
 130   @return The value written back to the PCI configuration register.
 131
 132 **/
 133 UINT8
 134 EFIAPI
 135 PciCf8And8 (
 136   IN      UINTN                     Address,
 137   IN      UINT8                     AndData
 138   );
 139
 140 /**
 141   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 142   value, followed a  bitwise inclusive OR with another 8-bit value.
 143
 144   Reads the 8-bit PCI configuration register specified by Address, performs a
 145   bitwise AND between the read result and the value specified by AndData,
 146   performs a bitwise inclusive OR between the result of the AND operation and
 147   the value specified by OrData, and writes the result to the 8-bit PCI
 148   configuration register specified by Address. The value written to the PCI
 149   configuration register is returned. This function must guarantee that all PCI
 150   read and write operations are serialized.
 151
 152   If Address > 0x0FFFFFFF, then ASSERT().
 153   If the register specified by Address >= 0x100, then ASSERT().
 154
 155   @param  Address Address that encodes the PCI Bus, Device, Function and
 156                   Register.
 157   @param  AndData The value to AND with the PCI configuration register.
 158   @param  OrData  The value to OR with the result of the AND operation.
 159
 160   @return The value written back to the PCI configuration register.
 161
 162 **/
 163 UINT8
 164 EFIAPI
 165 PciCf8AndThenOr8 (
 166   IN      UINTN                     Address,
 167   IN      UINT8                     AndData,
 168   IN      UINT8                     OrData
 169   );
 170
 171 /**
 172   Reads a bit field of a PCI configuration register.
 173
 174   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 175   specified by the StartBit and the EndBit. The value of the bit field is
 176   returned.
 177
 178   If Address > 0x0FFFFFFF, then ASSERT().
 179   If the register specified by Address >= 0x100, then ASSERT().
 180   If StartBit is greater than 7, then ASSERT().
 181   If EndBit is greater than 7, then ASSERT().
 182   If EndBit is less than StartBit, then ASSERT().
 183
 184   @param  Address   PCI configuration register to read.
 185   @param  StartBit  The ordinal of the least significant bit in the bit field.
 186                     Range 0..7.
 187   @param  EndBit    The ordinal of the most significant bit in the bit field.
 188                     Range 0..7.
 189
 190   @return The value of the bit field read from the PCI configuration register.
 191
 192 **/
 193 UINT8
 194 EFIAPI
 195 PciCf8BitFieldRead8 (
 196   IN      UINTN                     Address,
 197   IN      UINTN                     StartBit,
 198   IN      UINTN                     EndBit
 199   );
 200
 201 /**
 202   Writes a bit field to a PCI configuration register.
 203
 204   Writes Value to the bit field of the PCI configuration register. The bit
 205   field is specified by the StartBit and the EndBit. All other bits in the
 206   destination PCI configuration register are preserved. The new value of the
 207   8-bit register is returned.
 208
 209   If Address > 0x0FFFFFFF, then ASSERT().
 210   If the register specified by Address >= 0x100, then ASSERT().
 211   If StartBit is greater than 7, then ASSERT().
 212   If EndBit is greater than 7, then ASSERT().
 213   If EndBit is less than StartBit, then ASSERT().
 214
 215   @param  Address   PCI configuration register to write.
 216   @param  StartBit  The ordinal of the least significant bit in the bit field.
 217                     Range 0..7.
 218   @param  EndBit    The ordinal of the most significant bit in the bit field.
 219                     Range 0..7.
 220   @param  Value     New value of the bit field.
 221
 222   @return The value written back to the PCI configuration register.
 223
 224 **/
 225 UINT8
 226 EFIAPI
 227 PciCf8BitFieldWrite8 (
 228   IN      UINTN                     Address,
 229   IN      UINTN                     StartBit,
 230   IN      UINTN                     EndBit,
 231   IN      UINT8                     Value
 232   );
 233
 234 /**
 235   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 236   writes the result back to the bit field in the 8-bit port.
 237
 238   Reads the 8-bit PCI configuration register specified by Address, performs a
 239   bitwise inclusive OR between the read result and the value specified by
 240   OrData, and writes the result to the 8-bit PCI configuration register
 241   specified by Address. The value written to the PCI configuration register is
 242   returned. This function must guarantee that all PCI read and write operations
 243   are serialized. Extra left bits in OrData are stripped.
 244
 245   If Address > 0x0FFFFFFF, then ASSERT().
 246   If the register specified by Address >= 0x100, then ASSERT().
 247   If StartBit is greater than 7, then ASSERT().
 248   If EndBit is greater than 7, then ASSERT().
 249   If EndBit is less than StartBit, then ASSERT().
 250
 251   @param  Address   PCI configuration register to write.
 252   @param  StartBit  The ordinal of the least significant bit in the bit field.
 253                     Range 0..7.
 254   @param  EndBit    The ordinal of the most significant bit in the bit field.
 255                     Range 0..7.
 256   @param  OrData    The value to OR with the PCI configuration register.
 257
 258   @return The value written back to the PCI configuration register.
 259
 260 **/
 261 UINT8
 262 EFIAPI
 263 PciCf8BitFieldOr8 (
 264   IN      UINTN                     Address,
 265   IN      UINTN                     StartBit,
 266   IN      UINTN                     EndBit,
 267   IN      UINT8                     OrData
 268   );
 269
 270 /**
 271   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 272   AND, and writes the result back to the bit field in the 8-bit register.
 273
 274   Reads the 8-bit PCI configuration register specified by Address, performs a
 275   bitwise AND between the read result and the value specified by AndData, and
 276   writes the result to the 8-bit PCI configuration register specified by
 277   Address. The value written to the PCI configuration register is returned.
 278   This function must guarantee that all PCI read and write operations are
 279   serialized. Extra left bits in AndData are stripped.
 280
 281   If Address > 0x0FFFFFFF, then ASSERT().
 282   If the register specified by Address >= 0x100, then ASSERT().
 283   If StartBit is greater than 7, then ASSERT().
 284   If EndBit is greater than 7, then ASSERT().
 285   If EndBit is less than StartBit, then ASSERT().
 286
 287   @param  Address   PCI configuration register to write.
 288   @param  StartBit  The ordinal of the least significant bit in the bit field.
 289                     Range 0..7.
 290   @param  EndBit    The ordinal of the most significant bit in the bit field.
 291                     Range 0..7.
 292   @param  AndData   The value to AND with the PCI configuration register.
 293
 294   @return The value written back to the PCI configuration register.
 295
 296 **/
 297 UINT8
 298 EFIAPI
 299 PciCf8BitFieldAnd8 (
 300   IN      UINTN                     Address,
 301   IN      UINTN                     StartBit,
 302   IN      UINTN                     EndBit,
 303   IN      UINT8                     AndData
 304   );
 305
 306 /**
 307   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 308   bitwise inclusive OR, and writes the result back to the bit field in the
 309   8-bit port.
 310
 311   Reads the 8-bit PCI configuration register specified by Address, performs a
 312   bitwise AND followed by a bitwise inclusive OR between the read result and
 313   the value specified by AndData, and writes the result to the 8-bit PCI
 314   configuration register specified by Address. The value written to the PCI
 315   configuration register is returned. This function must guarantee that all PCI
 316   read and write operations are serialized. Extra left bits in both AndData and
 317   OrData are stripped.
 318
 319   If Address > 0x0FFFFFFF, then ASSERT().
 320   If the register specified by Address >= 0x100, then ASSERT().
 321   If StartBit is greater than 7, then ASSERT().
 322   If EndBit is greater than 7, then ASSERT().
 323   If EndBit is less than StartBit, then ASSERT().
 324
 325   @param  Address   PCI configuration register to write.
 326   @param  StartBit  The ordinal of the least significant bit in the bit field.
 327                     Range 0..7.
 328   @param  EndBit    The ordinal of the most significant bit in the bit field.
 329                     Range 0..7.
 330   @param  AndData   The value to AND with the PCI configuration register.
 331   @param  OrData    The value to OR with the result of the AND operation.
 332
 333   @return The value written back to the PCI configuration register.
 334
 335 **/
 336 UINT8
 337 EFIAPI
 338 PciCf8BitFieldAndThenOr8 (
 339   IN      UINTN                     Address,
 340   IN      UINTN                     StartBit,
 341   IN      UINTN                     EndBit,
 342   IN      UINT8                     AndData,
 343   IN      UINT8                     OrData
 344   );
 345
 346 /**
 347   Reads a 16-bit PCI configuration register.
 348
 349   Reads and returns the 16-bit PCI configuration register specified by Address.
 350   This function must guarantee that all PCI read and write operations are
 351   serialized.
 352
 353   If Address > 0x0FFFFFFF, then ASSERT().
 354   If Address is not aligned on a 16-bit boundary, then ASSERT().
 355   If the register specified by Address >= 0x100, then ASSERT().
 356
 357   @param  Address Address that encodes the PCI Bus, Device, Function and
 358                   Register.
 359
 360   @return The read value from the PCI configuration register.
 361
 362 **/
 363 UINT16
 364 EFIAPI
 365 PciCf8Read16 (
 366   IN      UINTN                     Address
 367   );
 368
 369 /**
 370   Writes a 16-bit PCI configuration register.
 371
 372   Writes the 16-bit PCI configuration register specified by Address with the
 373   value specified by Value. Value is returned. This function must guarantee
 374   that all PCI read and write operations are serialized.
 375
 376   If Address > 0x0FFFFFFF, then ASSERT().
 377   If Address is not aligned on a 16-bit boundary, then ASSERT().
 378   If the register specified by Address >= 0x100, then ASSERT().
 379
 380   @param  Address Address that encodes the PCI Bus, Device, Function and
 381                   Register.
 382   @param  Value   The value to write.
 383
 384   @return The value written to the PCI configuration register.
 385
 386 **/
 387 UINT16
 388 EFIAPI
 389 PciCf8Write16 (
 390   IN      UINTN                     Address,
 391   IN      UINT16                    Value
 392   );
 393
 394 /**
 395   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 396   a 16-bit value.
 397
 398   Reads the 16-bit PCI configuration register specified by Address, performs a
 399   bitwise inclusive OR between the read result and the value specified by
 400   OrData, and writes the result to the 16-bit PCI configuration register
 401   specified by Address. The value written to the PCI configuration register is
 402   returned. This function must guarantee that all PCI read and write operations
 403   are serialized.
 404
 405   If Address > 0x0FFFFFFF, then ASSERT().
 406   If Address is not aligned on a 16-bit boundary, then ASSERT().
 407   If the register specified by Address >= 0x100, then ASSERT().
 408
 409   @param  Address Address that encodes the PCI Bus, Device, Function and
 410                   Register.
 411   @param  OrData  The value to OR with the PCI configuration register.
 412
 413   @return The value written back to the PCI configuration register.
 414
 415 **/
 416 UINT16
 417 EFIAPI
 418 PciCf8Or16 (
 419   IN      UINTN                     Address,
 420   IN      UINT16                    OrData
 421   );
 422
 423 /**
 424   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 425   value.
 426
 427   Reads the 16-bit PCI configuration register specified by Address, performs a
 428   bitwise AND between the read result and the value specified by AndData, and
 429   writes the result to the 16-bit PCI configuration register specified by
 430   Address. The value written to the PCI configuration register is returned.
 431   This function must guarantee that all PCI read and write operations are
 432   serialized.
 433
 434   If Address > 0x0FFFFFFF, then ASSERT().
 435   If Address is not aligned on a 16-bit boundary, then ASSERT().
 436   If the register specified by Address >= 0x100, then ASSERT().
 437
 438   @param  Address Address that encodes the PCI Bus, Device, Function and
 439                   Register.
 440   @param  AndData The value to AND with the PCI configuration register.
 441
 442   @return The value written back to the PCI configuration register.
 443
 444 **/
 445 UINT16
 446 EFIAPI
 447 PciCf8And16 (
 448   IN      UINTN                     Address,
 449   IN      UINT16                    AndData
 450   );
 451
 452 /**
 453   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 454   value, followed a  bitwise inclusive OR with another 16-bit value.
 455
 456   Reads the 16-bit PCI configuration register specified by Address, performs a
 457   bitwise AND between the read result and the value specified by AndData,
 458   performs a bitwise inclusive OR between the result of the AND operation and
 459   the value specified by OrData, and writes the result to the 16-bit PCI
 460   configuration register specified by Address. The value written to the PCI
 461   configuration register is returned. This function must guarantee that all PCI
 462   read and write operations are serialized.
 463
 464   If Address > 0x0FFFFFFF, then ASSERT().
 465   If Address is not aligned on a 16-bit boundary, then ASSERT().
 466   If the register specified by Address >= 0x100, then ASSERT().
 467
 468   @param  Address Address that encodes the PCI Bus, Device, Function and
 469                   Register.
 470   @param  AndData The value to AND with the PCI configuration register.
 471   @param  OrData  The value to OR with the result of the AND operation.
 472
 473   @return The value written back to the PCI configuration register.
 474
 475 **/
 476 UINT16
 477 EFIAPI
 478 PciCf8AndThenOr16 (
 479   IN      UINTN                     Address,
 480   IN      UINT16                    AndData,
 481   IN      UINT16                    OrData
 482   );
 483
 484 /**
 485   Reads a bit field of a PCI configuration register.
 486
 487   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 488   specified by the StartBit and the EndBit. The value of the bit field is
 489   returned.
 490
 491   If Address > 0x0FFFFFFF, then ASSERT().
 492   If Address is not aligned on a 16-bit boundary, then ASSERT().
 493   If the register specified by Address >= 0x100, then ASSERT().
 494   If StartBit is greater than 15, then ASSERT().
 495   If EndBit is greater than 15, then ASSERT().
 496   If EndBit is less than StartBit, then ASSERT().
 497
 498   @param  Address   PCI configuration register to read.
 499   @param  StartBit  The ordinal of the least significant bit in the bit field.
 500                     Range 0..15.
 501   @param  EndBit    The ordinal of the most significant bit in the bit field.
 502                     Range 0..15.
 503
 504   @return The value of the bit field read from the PCI configuration register.
 505
 506 **/
 507 UINT16
 508 EFIAPI
 509 PciCf8BitFieldRead16 (
 510   IN      UINTN                     Address,
 511   IN      UINTN                     StartBit,
 512   IN      UINTN                     EndBit
 513   );
 514
 515 /**
 516   Writes a bit field to a PCI configuration register.
 517
 518   Writes Value to the bit field of the PCI configuration register. The bit
 519   field is specified by the StartBit and the EndBit. All other bits in the
 520   destination PCI configuration register are preserved. The new value of the
 521   16-bit register is returned.
 522
 523   If Address > 0x0FFFFFFF, then ASSERT().
 524   If Address is not aligned on a 16-bit boundary, then ASSERT().
 525   If the register specified by Address >= 0x100, then ASSERT().
 526   If StartBit is greater than 15, then ASSERT().
 527   If EndBit is greater than 15, then ASSERT().
 528   If EndBit is less than StartBit, then ASSERT().
 529
 530   @param  Address   PCI configuration register to write.
 531   @param  StartBit  The ordinal of the least significant bit in the bit field.
 532                     Range 0..15.
 533   @param  EndBit    The ordinal of the most significant bit in the bit field.
 534                     Range 0..15.
 535   @param  Value     New value of the bit field.
 536
 537   @return The value written back to the PCI configuration register.
 538
 539 **/
 540 UINT16
 541 EFIAPI
 542 PciCf8BitFieldWrite16 (
 543   IN      UINTN                     Address,
 544   IN      UINTN                     StartBit,
 545   IN      UINTN                     EndBit,
 546   IN      UINT16                    Value
 547   );
 548
 549 /**
 550   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 551   writes the result back to the bit field in the 16-bit port.
 552
 553   Reads the 16-bit PCI configuration register specified by Address, performs a
 554   bitwise inclusive OR between the read result and the value specified by
 555   OrData, and writes the result to the 16-bit PCI configuration register
 556   specified by Address. The value written to the PCI configuration register is
 557   returned. This function must guarantee that all PCI read and write operations
 558   are serialized. Extra left bits in OrData are stripped.
 559
 560   If Address > 0x0FFFFFFF, then ASSERT().
 561   If Address is not aligned on a 16-bit boundary, then ASSERT().
 562   If the register specified by Address >= 0x100, then ASSERT().
 563   If StartBit is greater than 15, then ASSERT().
 564   If EndBit is greater than 15, then ASSERT().
 565   If EndBit is less than StartBit, then ASSERT().
 566
 567   @param  Address   PCI configuration register to write.
 568   @param  StartBit  The ordinal of the least significant bit in the bit field.
 569                     Range 0..15.
 570   @param  EndBit    The ordinal of the most significant bit in the bit field.
 571                     Range 0..15.
 572   @param  OrData    The value to OR with the PCI configuration register.
 573
 574   @return The value written back to the PCI configuration register.
 575
 576 **/
 577 UINT16
 578 EFIAPI
 579 PciCf8BitFieldOr16 (
 580   IN      UINTN                     Address,
 581   IN      UINTN                     StartBit,
 582   IN      UINTN                     EndBit,
 583   IN      UINT16                    OrData
 584   );
 585
 586 /**
 587   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 588   AND, and writes the result back to the bit field in the 16-bit register.
 589
 590   Reads the 16-bit PCI configuration register specified by Address, performs a
 591   bitwise AND between the read result and the value specified by AndData, and
 592   writes the result to the 16-bit PCI configuration register specified by
 593   Address. The value written to the PCI configuration register is returned.
 594   This function must guarantee that all PCI read and write operations are
 595   serialized. Extra left bits in AndData are stripped.
 596
 597   If Address > 0x0FFFFFFF, then ASSERT().
 598   If Address is not aligned on a 16-bit boundary, then ASSERT().
 599   If the register specified by Address >= 0x100, then ASSERT().
 600   If StartBit is greater than 15, then ASSERT().
 601   If EndBit is greater than 15, then ASSERT().
 602   If EndBit is less than StartBit, then ASSERT().
 603
 604   @param  Address   PCI configuration register to write.
 605   @param  StartBit  The ordinal of the least significant bit in the bit field.
 606                     Range 0..15.
 607   @param  EndBit    The ordinal of the most significant bit in the bit field.
 608                     Range 0..15.
 609   @param  AndData   The value to AND with the PCI configuration register.
 610
 611   @return The value written back to the PCI configuration register.
 612
 613 **/
 614 UINT16
 615 EFIAPI
 616 PciCf8BitFieldAnd16 (
 617   IN      UINTN                     Address,
 618   IN      UINTN                     StartBit,
 619   IN      UINTN                     EndBit,
 620   IN      UINT16                    AndData
 621   );
 622
 623 /**
 624   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 625   bitwise inclusive OR, and writes the result back to the bit field in the
 626   16-bit port.
 627
 628   Reads the 16-bit PCI configuration register specified by Address, performs a
 629   bitwise AND followed by a bitwise inclusive OR between the read result and
 630   the value specified by AndData, and writes the result to the 16-bit PCI
 631   configuration register specified by Address. The value written to the PCI
 632   configuration register is returned. This function must guarantee that all PCI
 633   read and write operations are serialized. Extra left bits in both AndData and
 634   OrData are stripped.
 635
 636   If Address > 0x0FFFFFFF, then ASSERT().
 637   If Address is not aligned on a 16-bit boundary, then ASSERT().
 638   If the register specified by Address >= 0x100, then ASSERT().
 639   If StartBit is greater than 15, then ASSERT().
 640   If EndBit is greater than 15, then ASSERT().
 641   If EndBit is less than StartBit, then ASSERT().
 642
 643   @param  Address   PCI configuration register to write.
 644   @param  StartBit  The ordinal of the least significant bit in the bit field.
 645                     Range 0..15.
 646   @param  EndBit    The ordinal of the most significant bit in the bit field.
 647                     Range 0..15.
 648   @param  AndData   The value to AND with the PCI configuration register.
 649   @param  OrData    The value to OR with the result of the AND operation.
 650
 651   @return The value written back to the PCI configuration register.
 652
 653 **/
 654 UINT16
 655 EFIAPI
 656 PciCf8BitFieldAndThenOr16 (
 657   IN      UINTN                     Address,
 658   IN      UINTN                     StartBit,
 659   IN      UINTN                     EndBit,
 660   IN      UINT16                    AndData,
 661   IN      UINT16                    OrData
 662   );
 663
 664 /**
 665   Reads a 32-bit PCI configuration register.
 666
 667   Reads and returns the 32-bit PCI configuration register specified by Address.
 668   This function must guarantee that all PCI read and write operations are
 669   serialized.
 670
 671   If Address > 0x0FFFFFFF, then ASSERT().
 672   If Address is not aligned on a 32-bit boundary, then ASSERT().
 673   If the register specified by Address >= 0x100, then ASSERT().
 674
 675   @param  Address Address that encodes the PCI Bus, Device, Function and
 676                   Register.
 677
 678   @return The read value from the PCI configuration register.
 679
 680 **/
 681 UINT32
 682 EFIAPI
 683 PciCf8Read32 (
 684   IN      UINTN                     Address
 685   );
 686
 687 /**
 688   Writes a 32-bit PCI configuration register.
 689
 690   Writes the 32-bit PCI configuration register specified by Address with the
 691   value specified by Value. Value is returned. This function must guarantee
 692   that all PCI read and write operations are serialized.
 693
 694   If Address > 0x0FFFFFFF, then ASSERT().
 695   If Address is not aligned on a 32-bit boundary, then ASSERT().
 696   If the register specified by Address >= 0x100, then ASSERT().
 697
 698   @param  Address Address that encodes the PCI Bus, Device, Function and
 699                   Register.
 700   @param  Value   The value to write.
 701
 702   @return The value written to the PCI configuration register.
 703
 704 **/
 705 UINT32
 706 EFIAPI
 707 PciCf8Write32 (
 708   IN      UINTN                     Address,
 709   IN      UINT32                    Value
 710   );
 711
 712 /**
 713   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 714   a 32-bit value.
 715
 716   Reads the 32-bit PCI configuration register specified by Address, performs a
 717   bitwise inclusive OR between the read result and the value specified by
 718   OrData, and writes the result to the 32-bit PCI configuration register
 719   specified by Address. The value written to the PCI configuration register is
 720   returned. This function must guarantee that all PCI read and write operations
 721   are serialized.
 722
 723   If Address > 0x0FFFFFFF, then ASSERT().
 724   If Address is not aligned on a 32-bit boundary, then ASSERT().
 725   If the register specified by Address >= 0x100, then ASSERT().
 726
 727   @param  Address Address that encodes the PCI Bus, Device, Function and
 728                   Register.
 729   @param  OrData  The value to OR with the PCI configuration register.
 730
 731   @return The value written back to the PCI configuration register.
 732
 733 **/
 734 UINT32
 735 EFIAPI
 736 PciCf8Or32 (
 737   IN      UINTN                     Address,
 738   IN      UINT32                    OrData
 739   );
 740
 741 /**
 742   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 743   value.
 744
 745   Reads the 32-bit PCI configuration register specified by Address, performs a
 746   bitwise AND between the read result and the value specified by AndData, and
 747   writes the result to the 32-bit PCI configuration register specified by
 748   Address. The value written to the PCI configuration register is returned.
 749   This function must guarantee that all PCI read and write operations are
 750   serialized.
 751
 752   If Address > 0x0FFFFFFF, then ASSERT().
 753   If Address is not aligned on a 32-bit boundary, then ASSERT().
 754   If the register specified by Address >= 0x100, then ASSERT().
 755
 756   @param  Address Address that encodes the PCI Bus, Device, Function and
 757                   Register.
 758   @param  AndData The value to AND with the PCI configuration register.
 759
 760   @return The value written back to the PCI configuration register.
 761
 762 **/
 763 UINT32
 764 EFIAPI
 765 PciCf8And32 (
 766   IN      UINTN                     Address,
 767   IN      UINT32                    AndData
 768   );
 769
 770 /**
 771   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 772   value, followed a  bitwise inclusive OR with another 32-bit value.
 773
 774   Reads the 32-bit PCI configuration register specified by Address, performs a
 775   bitwise AND between the read result and the value specified by AndData,
 776   performs a bitwise inclusive OR between the result of the AND operation and
 777   the value specified by OrData, and writes the result to the 32-bit PCI
 778   configuration register specified by Address. The value written to the PCI
 779   configuration register is returned. This function must guarantee that all PCI
 780   read and write operations are serialized.
 781
 782   If Address > 0x0FFFFFFF, then ASSERT().
 783   If Address is not aligned on a 32-bit boundary, then ASSERT().
 784   If the register specified by Address >= 0x100, then ASSERT().
 785
 786   @param  Address Address that encodes the PCI Bus, Device, Function and
 787                   Register.
 788   @param  AndData The value to AND with the PCI configuration register.
 789   @param  OrData  The value to OR with the result of the AND operation.
 790
 791   @return The value written back to the PCI configuration register.
 792
 793 **/
 794 UINT32
 795 EFIAPI
 796 PciCf8AndThenOr32 (
 797   IN      UINTN                     Address,
 798   IN      UINT32                    AndData,
 799   IN      UINT32                    OrData
 800   );
 801
 802 /**
 803   Reads a bit field of a PCI configuration register.
 804
 805   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 806   specified by the StartBit and the EndBit. The value of the bit field is
 807   returned.
 808
 809   If Address > 0x0FFFFFFF, then ASSERT().
 810   If Address is not aligned on a 32-bit boundary, then ASSERT().
 811   If the register specified by Address >= 0x100, then ASSERT().
 812   If StartBit is greater than 31, then ASSERT().
 813   If EndBit is greater than 31, then ASSERT().
 814   If EndBit is less than StartBit, then ASSERT().
 815
 816   @param  Address   PCI configuration register to read.
 817   @param  StartBit  The ordinal of the least significant bit in the bit field.
 818                     Range 0..31.
 819   @param  EndBit    The ordinal of the most significant bit in the bit field.
 820                     Range 0..31.
 821
 822   @return The value of the bit field read from the PCI configuration register.
 823
 824 **/
 825 UINT32
 826 EFIAPI
 827 PciCf8BitFieldRead32 (
 828   IN      UINTN                     Address,
 829   IN      UINTN                     StartBit,
 830   IN      UINTN                     EndBit
 831   );
 832
 833 /**
 834   Writes a bit field to a PCI configuration register.
 835
 836   Writes Value to the bit field of the PCI configuration register. The bit
 837   field is specified by the StartBit and the EndBit. All other bits in the
 838   destination PCI configuration register are preserved. The new value of the
 839   32-bit register is returned.
 840
 841   If Address > 0x0FFFFFFF, then ASSERT().
 842   If Address is not aligned on a 32-bit boundary, then ASSERT().
 843   If the register specified by Address >= 0x100, then ASSERT().
 844   If StartBit is greater than 31, then ASSERT().
 845   If EndBit is greater than 31, then ASSERT().
 846   If EndBit is less than StartBit, then ASSERT().
 847
 848   @param  Address   PCI configuration register to write.
 849   @param  StartBit  The ordinal of the least significant bit in the bit field.
 850                     Range 0..31.
 851   @param  EndBit    The ordinal of the most significant bit in the bit field.
 852                     Range 0..31.
 853   @param  Value     New value of the bit field.
 854
 855   @return The value written back to the PCI configuration register.
 856
 857 **/
 858 UINT32
 859 EFIAPI
 860 PciCf8BitFieldWrite32 (
 861   IN      UINTN                     Address,
 862   IN      UINTN                     StartBit,
 863   IN      UINTN                     EndBit,
 864   IN      UINT32                    Value
 865   );
 866
 867 /**
 868   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 869   writes the result back to the bit field in the 32-bit port.
 870
 871   Reads the 32-bit PCI configuration register specified by Address, performs a
 872   bitwise inclusive OR between the read result and the value specified by
 873   OrData, and writes the result to the 32-bit PCI configuration register
 874   specified by Address. The value written to the PCI configuration register is
 875   returned. This function must guarantee that all PCI read and write operations
 876   are serialized. Extra left bits in OrData are stripped.
 877
 878   If Address > 0x0FFFFFFF, then ASSERT().
 879   If Address is not aligned on a 32-bit boundary, then ASSERT().
 880   If the register specified by Address >= 0x100, then ASSERT().
 881   If StartBit is greater than 31, then ASSERT().
 882   If EndBit is greater than 31, then ASSERT().
 883   If EndBit is less than StartBit, then ASSERT().
 884
 885   @param  Address   PCI configuration register to write.
 886   @param  StartBit  The ordinal of the least significant bit in the bit field.
 887                     Range 0..31.
 888   @param  EndBit    The ordinal of the most significant bit in the bit field.
 889                     Range 0..31.
 890   @param  OrData    The value to OR with the PCI configuration register.
 891
 892   @return The value written back to the PCI configuration register.
 893
 894 **/
 895 UINT32
 896 EFIAPI
 897 PciCf8BitFieldOr32 (
 898   IN      UINTN                     Address,
 899   IN      UINTN                     StartBit,
 900   IN      UINTN                     EndBit,
 901   IN      UINT32                    OrData
 902   );
 903
 904 /**
 905   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 906   AND, and writes the result back to the bit field in the 32-bit register.
 907
 908   Reads the 32-bit PCI configuration register specified by Address, performs a
 909   bitwise AND between the read result and the value specified by AndData, and
 910   writes the result to the 32-bit PCI configuration register specified by
 911   Address. The value written to the PCI configuration register is returned.
 912   This function must guarantee that all PCI read and write operations are
 913   serialized. Extra left bits in AndData are stripped.
 914
 915   If Address > 0x0FFFFFFF, then ASSERT().
 916   If Address is not aligned on a 32-bit boundary, then ASSERT().
 917   If the register specified by Address >= 0x100, then ASSERT().
 918   If StartBit is greater than 31, then ASSERT().
 919   If EndBit is greater than 31, then ASSERT().
 920   If EndBit is less than StartBit, then ASSERT().
 921
 922   @param  Address   PCI configuration register to write.
 923   @param  StartBit  The ordinal of the least significant bit in the bit field.
 924                     Range 0..31.
 925   @param  EndBit    The ordinal of the most significant bit in the bit field.
 926                     Range 0..31.
 927   @param  AndData   The value to AND with the PCI configuration register.
 928
 929   @return The value written back to the PCI configuration register.
 930
 931 **/
 932 UINT32
 933 EFIAPI
 934 PciCf8BitFieldAnd32 (
 935   IN      UINTN                     Address,
 936   IN      UINTN                     StartBit,
 937   IN      UINTN                     EndBit,
 938   IN      UINT32                    AndData
 939   );
 940
 941 /**
 942   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 943   bitwise inclusive OR, and writes the result back to the bit field in the
 944   32-bit port.
 945
 946   Reads the 32-bit PCI configuration register specified by Address, performs a
 947   bitwise AND followed by a bitwise inclusive OR between the read result and
 948   the value specified by AndData, and writes the result to the 32-bit PCI
 949   configuration register specified by Address. The value written to the PCI
 950   configuration register is returned. This function must guarantee that all PCI
 951   read and write operations are serialized. Extra left bits in both AndData and
 952   OrData are stripped.
 953
 954   If Address > 0x0FFFFFFF, then ASSERT().
 955   If Address is not aligned on a 32-bit boundary, then ASSERT().
 956   If the register specified by Address >= 0x100, then ASSERT().
 957   If StartBit is greater than 31, then ASSERT().
 958   If EndBit is greater than 31, then ASSERT().
 959   If EndBit is less than StartBit, then ASSERT().
 960
 961   @param  Address   PCI configuration register to write.
 962   @param  StartBit  The ordinal of the least significant bit in the bit field.
 963                     Range 0..31.
 964   @param  EndBit    The ordinal of the most significant bit in the bit field.
 965                     Range 0..31.
 966   @param  AndData   The value to AND with the PCI configuration register.
 967   @param  OrData    The value to OR with the result of the AND operation.
 968
 969   @return The value written back to the PCI configuration register.
 970
 971 **/
 972 UINT32
 973 EFIAPI
 974 PciCf8BitFieldAndThenOr32 (
 975   IN      UINTN                     Address,
 976   IN      UINTN                     StartBit,
 977   IN      UINTN                     EndBit,
 978   IN      UINT32                    AndData,
 979   IN      UINT32                    OrData
 980   );
 981
 982 /**
 983   Reads a range of PCI configuration registers into a caller supplied buffer.
 984
 985   Reads the range of PCI configuration registers specified by StartAddress and
 986   Size into the buffer specified by Buffer. This function only allows the PCI
 987   configuration registers from a single PCI function to be read. Size is
 988   returned. When possible 32-bit PCI configuration read cycles are used to read
 989   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
 990   and 16-bit PCI configuration read cycles may be used at the beginning and the
 991   end of the range.
 992
 993   If StartAddress > 0x0FFFFFFF, then ASSERT().
 994   If the register specified by StartAddress >= 0x100, then ASSERT().
 995   If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
 996   If Size > 0 and Buffer is NULL, then ASSERT().
 997
 998   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
 999                         Function and Register.
1000   @param  Size          Size in bytes of the transfer.
1001   @param  Buffer        Pointer to a buffer receiving the data read.
1002
1003   @return Size read from StartAddress.
1004
1005 **/
1006 UINTN
1007 EFIAPI
1008 PciCf8ReadBuffer (
1009   IN      UINTN                     StartAddress,
1010   IN      UINTN                     Size,
1011   OUT     VOID                      *Buffer
1012   );
1013
1014 /**
1015   Copies the data in a caller supplied buffer to a specified range of PCI
1016   configuration space.
1017
1018   Writes the range of PCI configuration registers specified by StartAddress and
1019   Size from the buffer specified by Buffer. This function only allows the PCI
1020   configuration registers from a single PCI function to be written. Size is
1021   returned. When possible 32-bit PCI configuration write cycles are used to
1022   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1023   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1024   and the end of the range.
1025
1026   If StartAddress > 0x0FFFFFFF, then ASSERT().
1027   If the register specified by StartAddress >= 0x100, then ASSERT().
1028   If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1029   If Size > 0 and Buffer is NULL, then ASSERT().
1030
1031   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1032                         Function and Register.
1033   @param  Size          Size in bytes of the transfer.
1034   @param  Buffer        Pointer to a buffer containing the data to write.
1035
1036   @return Size written to StartAddress.
1037
1038 **/
1039 UINTN
1040 EFIAPI
1041 PciCf8WriteBuffer (
1042   IN      UINTN                     StartAddress,
1043   IN      UINTN                     Size,
1044   IN      VOID                      *Buffer
1045   );
1046
1047 #endif