MdePkg/Include/Library/PciCf8Lib.h

   1 /** @file
   2         PCI CF8 Library Services for PCI Segment #0
   3
   4         Copyright (c) 2006, Intel Corporation
   5         All rights reserved. This program and the accompanying materials
   6         are licensed and made available under the terms and conditions of the BSD License
   7         which accompanies this distribution.  The full text of the license may be found at
   8         http://opensource.org/licenses/bsd-license.php
   9
  10         THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11         WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13         Module Name:    PciCf8Lib.h
  14
  15 **/
  16
  17 #ifndef __PCI_CF8_LIB_H__
  18 #define __PCI_CF8_LIB_H__
  19
  20 #include <Library/PciLib.h>
  21
  22 /**
  23   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  24   address that can be passed to the PCI Library functions.
  25
  26   Computes an address that is compatible with the PCI Library functions. The
  27   unused upper bits of Bus, Device, Function and Register are stripped prior to
  28   the generation of the address.
  29
  30   @param  Bus       PCI Bus number. Range 0..255.
  31   @param  Device    PCI Device number. Range 0..31.
  32   @param  Function  PCI Function number. Range 0..7.
  33   @param  Register  PCI Register number. Range 0..255.
  34
  35   @return The encode PCI address.
  36
  37 **/
  38 #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \
  39   PCI_LIB_ADDRESS (Bus, Device, Function, Offset)
  40
  41 /**
  42   Reads an 8-bit PCI configuration register.
  43
  44   Reads and returns the 8-bit PCI configuration register specified by Address.
  45   This function must guarantee that all PCI read and write operations are
  46   serialized.
  47
  48   If Address > 0x0FFFFFFF, then ASSERT().
  49   If the register specified by Address >= 0x100, then ASSERT().
  50
  51   @param  Address Address that encodes the PCI Bus, Device, Function and
  52                   Register.
  53
  54   @return The read value from the PCI configuration register.
  55
  56 **/
  57 UINT8
  58 EFIAPI
  59 PciCf8Read8 (
  60   IN      UINTN                     Address
  61   );
  62
  63 /**
  64   Writes an 8-bit PCI configuration register.
  65
  66   Writes the 8-bit PCI configuration register specified by Address with the
  67   value specified by Value. Value is returned. This function must guarantee
  68   that all PCI read and write operations are serialized.
  69
  70   If Address > 0x0FFFFFFF, then ASSERT().
  71   If the register specified by Address >= 0x100, then ASSERT().
  72
  73   @param  Address Address that encodes the PCI Bus, Device, Function and
  74                   Register.
  75   @param  Value   The value to write.
  76
  77   @return The value written to the PCI configuration register.
  78
  79 **/
  80 UINT8
  81 EFIAPI
  82 PciCf8Write8 (
  83   IN      UINTN                     Address,
  84   IN      UINT8                     Data
  85   );
  86
  87 /**
  88   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
  89   an 8-bit value.
  90
  91   Reads the 8-bit PCI configuration register specified by Address, performs a
  92   bitwise inclusive OR between the read result and the value specified by
  93   OrData, and writes the result to the 8-bit PCI configuration register
  94   specified by Address. The value written to the PCI configuration register is
  95   returned. This function must guarantee that all PCI read and write operations
  96   are serialized.
  97
  98   If Address > 0x0FFFFFFF, then ASSERT().
  99   If the register specified by Address >= 0x100, then ASSERT().
 100
 101   @param  Address Address that encodes the PCI Bus, Device, Function and
 102                   Register.
 103   @param  OrData  The value to OR with the PCI configuration register.
 104
 105   @return The value written back to the PCI configuration register.
 106
 107 **/
 108 UINT8
 109 EFIAPI
 110 PciCf8Or8 (
 111   IN      UINTN                     Address,
 112   IN      UINT8                     OrData
 113   );
 114
 115 /**
 116   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 117   value.
 118
 119   Reads the 8-bit PCI configuration register specified by Address, performs a
 120   bitwise AND between the read result and the value specified by AndData, and
 121   writes the result to the 8-bit PCI configuration register specified by
 122   Address. The value written to the PCI configuration register is returned.
 123   This function must guarantee that all PCI read and write operations are
 124   serialized.
 125
 126   If Address > 0x0FFFFFFF, then ASSERT().
 127   If the register specified by Address >= 0x100, then ASSERT().
 128
 129   @param  Address Address that encodes the PCI Bus, Device, Function and
 130                   Register.
 131   @param  AndData The value to AND with the PCI configuration register.
 132
 133   @return The value written back to the PCI configuration register.
 134
 135 **/
 136 UINT8
 137 EFIAPI
 138 PciCf8And8 (
 139   IN      UINTN                     Address,
 140   IN      UINT8                     AndData
 141   );
 142
 143 /**
 144   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 145   value, followed a  bitwise inclusive OR with another 8-bit value.
 146
 147   Reads the 8-bit PCI configuration register specified by Address, performs a
 148   bitwise AND between the read result and the value specified by AndData,
 149   performs a bitwise inclusive OR between the result of the AND operation and
 150   the value specified by OrData, and writes the result to the 8-bit PCI
 151   configuration register specified by Address. The value written to the PCI
 152   configuration register is returned. This function must guarantee that all PCI
 153   read and write operations are serialized.
 154
 155   If Address > 0x0FFFFFFF, then ASSERT().
 156   If the register specified by Address >= 0x100, then ASSERT().
 157
 158   @param  Address Address that encodes the PCI Bus, Device, Function and
 159                   Register.
 160   @param  AndData The value to AND with the PCI configuration register.
 161   @param  OrData  The value to OR with the result of the AND operation.
 162
 163   @return The value written back to the PCI configuration register.
 164
 165 **/
 166 UINT8
 167 EFIAPI
 168 PciCf8AndThenOr8 (
 169   IN      UINTN                     Address,
 170   IN      UINT8                     AndData,
 171   IN      UINT8                     OrData
 172   );
 173
 174 /**
 175   Reads a bit field of a PCI configuration register.
 176
 177   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 178   specified by the StartBit and the EndBit. The value of the bit field is
 179   returned.
 180
 181   If Address > 0x0FFFFFFF, then ASSERT().
 182   If the register specified by Address >= 0x100, then ASSERT().
 183   If StartBit is greater than 7, then ASSERT().
 184   If EndBit is greater than 7, then ASSERT().
 185   If EndBit is less than or equal to StartBit, then ASSERT().
 186
 187   @param  Address   PCI configuration register to read.
 188   @param  StartBit  The ordinal of the least significant bit in the bit field.
 189                     Range 0..7.
 190   @param  EndBit    The ordinal of the most significant bit in the bit field.
 191                     Range 0..7.
 192
 193   @return The value of the bit field read from the PCI configuration register.
 194
 195 **/
 196 UINT8
 197 EFIAPI
 198 PciCf8BitFieldRead8 (
 199   IN      UINTN                     Address,
 200   IN      UINTN                     StartBit,
 201   IN      UINTN                     EndBit
 202   );
 203
 204 /**
 205   Writes a bit field to a PCI configuration register.
 206
 207   Writes Value to the bit field of the PCI configuration register. The bit
 208   field is specified by the StartBit and the EndBit. All other bits in the
 209   destination PCI configuration register are preserved. The new value of the
 210   8-bit register is returned.
 211
 212   If Address > 0x0FFFFFFF, then ASSERT().
 213   If the register specified by Address >= 0x100, then ASSERT().
 214   If StartBit is greater than 7, then ASSERT().
 215   If EndBit is greater than 7, then ASSERT().
 216   If EndBit is less than or equal to StartBit, then ASSERT().
 217
 218   @param  Address   PCI configuration register to write.
 219   @param  StartBit  The ordinal of the least significant bit in the bit field.
 220                     Range 0..7.
 221   @param  EndBit    The ordinal of the most significant bit in the bit field.
 222                     Range 0..7.
 223   @param  Value     New value of the bit field.
 224
 225   @return The value written back to the PCI configuration register.
 226
 227 **/
 228 UINT8
 229 EFIAPI
 230 PciCf8BitFieldWrite8 (
 231   IN      UINTN                     Address,
 232   IN      UINTN                     StartBit,
 233   IN      UINTN                     EndBit,
 234   IN      UINT8                     Value
 235   );
 236
 237 /**
 238   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 239   writes the result back to the bit field in the 8-bit port.
 240
 241   Reads the 8-bit PCI configuration register specified by Address, performs a
 242   bitwise inclusive OR between the read result and the value specified by
 243   OrData, and writes the result to the 8-bit PCI configuration register
 244   specified by Address. The value written to the PCI configuration register is
 245   returned. This function must guarantee that all PCI read and write operations
 246   are serialized. Extra left bits in OrData are stripped.
 247
 248   If Address > 0x0FFFFFFF, then ASSERT().
 249   If the register specified by Address >= 0x100, then ASSERT().
 250   If StartBit is greater than 7, then ASSERT().
 251   If EndBit is greater than 7, then ASSERT().
 252   If EndBit is less than or equal to StartBit, then ASSERT().
 253
 254   @param  Address   PCI configuration register to write.
 255   @param  StartBit  The ordinal of the least significant bit in the bit field.
 256                     Range 0..7.
 257   @param  EndBit    The ordinal of the most significant bit in the bit field.
 258                     Range 0..7.
 259   @param  OrData    The value to OR with the PCI configuration register.
 260
 261   @return The value written back to the PCI configuration register.
 262
 263 **/
 264 UINT8
 265 EFIAPI
 266 PciCf8BitFieldOr8 (
 267   IN      UINTN                     Address,
 268   IN      UINTN                     StartBit,
 269   IN      UINTN                     EndBit,
 270   IN      UINT8                     OrData
 271   );
 272
 273 /**
 274   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 275   AND, and writes the result back to the bit field in the 8-bit register.
 276
 277   Reads the 8-bit PCI configuration register specified by Address, performs a
 278   bitwise AND between the read result and the value specified by AndData, and
 279   writes the result to the 8-bit PCI configuration register specified by
 280   Address. The value written to the PCI configuration register is returned.
 281   This function must guarantee that all PCI read and write operations are
 282   serialized. Extra left bits in AndData are stripped.
 283
 284   If Address > 0x0FFFFFFF, then ASSERT().
 285   If the register specified by Address >= 0x100, then ASSERT().
 286   If StartBit is greater than 7, then ASSERT().
 287   If EndBit is greater than 7, then ASSERT().
 288   If EndBit is less than or equal to StartBit, then ASSERT().
 289
 290   @param  Address   PCI configuration register to write.
 291   @param  StartBit  The ordinal of the least significant bit in the bit field.
 292                     Range 0..7.
 293   @param  EndBit    The ordinal of the most significant bit in the bit field.
 294                     Range 0..7.
 295   @param  AndData   The value to AND with the PCI configuration register.
 296
 297   @return The value written back to the PCI configuration register.
 298
 299 **/
 300 UINT8
 301 EFIAPI
 302 PciCf8BitFieldAnd8 (
 303   IN      UINTN                     Address,
 304   IN      UINTN                     StartBit,
 305   IN      UINTN                     EndBit,
 306   IN      UINT8                     AndData
 307   );
 308
 309 /**
 310   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 311   bitwise inclusive OR, and writes the result back to the bit field in the
 312   8-bit port.
 313
 314   Reads the 8-bit PCI configuration register specified by Address, performs a
 315   bitwise AND followed by a bitwise inclusive OR between the read result and
 316   the value specified by AndData, and writes the result to the 8-bit PCI
 317   configuration register specified by Address. The value written to the PCI
 318   configuration register is returned. This function must guarantee that all PCI
 319   read and write operations are serialized. Extra left bits in both AndData and
 320   OrData are stripped.
 321
 322   If Address > 0x0FFFFFFF, then ASSERT().
 323   If the register specified by Address >= 0x100, then ASSERT().
 324   If StartBit is greater than 7, then ASSERT().
 325   If EndBit is greater than 7, then ASSERT().
 326   If EndBit is less than or equal to StartBit, then ASSERT().
 327
 328   @param  Address   PCI configuration register to write.
 329   @param  StartBit  The ordinal of the least significant bit in the bit field.
 330                     Range 0..7.
 331   @param  EndBit    The ordinal of the most significant bit in the bit field.
 332                     Range 0..7.
 333   @param  AndData   The value to AND with the PCI configuration register.
 334   @param  OrData    The value to OR with the result of the AND operation.
 335
 336   @return The value written back to the PCI configuration register.
 337
 338 **/
 339 UINT8
 340 EFIAPI
 341 PciCf8BitFieldAndThenOr8 (
 342   IN      UINTN                     Address,
 343   IN      UINTN                     StartBit,
 344   IN      UINTN                     EndBit,
 345   IN      UINT8                     AndData,
 346   IN      UINT8                     OrData
 347   );
 348
 349 /**
 350   Reads a 16-bit PCI configuration register.
 351
 352   Reads and returns the 16-bit PCI configuration register specified by Address.
 353   This function must guarantee that all PCI read and write operations are
 354   serialized.
 355
 356   If Address > 0x0FFFFFFF, then ASSERT().
 357   If Address is not aligned on a 16-bit boundary, then ASSERT().
 358   If the register specified by Address >= 0x100, then ASSERT().
 359
 360   @param  Address Address that encodes the PCI Bus, Device, Function and
 361                   Register.
 362
 363   @return The read value from the PCI configuration register.
 364
 365 **/
 366 UINT16
 367 EFIAPI
 368 PciCf8Read16 (
 369   IN      UINTN                     Address
 370   );
 371
 372 /**
 373   Writes a 16-bit PCI configuration register.
 374
 375   Writes the 16-bit PCI configuration register specified by Address with the
 376   value specified by Value. Value is returned. This function must guarantee
 377   that all PCI read and write operations are serialized.
 378
 379   If Address > 0x0FFFFFFF, then ASSERT().
 380   If Address is not aligned on a 16-bit boundary, then ASSERT().
 381   If the register specified by Address >= 0x100, then ASSERT().
 382
 383   @param  Address Address that encodes the PCI Bus, Device, Function and
 384                   Register.
 385   @param  Value   The value to write.
 386
 387   @return The value written to the PCI configuration register.
 388
 389 **/
 390 UINT16
 391 EFIAPI
 392 PciCf8Write16 (
 393   IN      UINTN                     Address,
 394   IN      UINT16                    Data
 395   );
 396
 397 /**
 398   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 399   a 16-bit value.
 400
 401   Reads the 16-bit PCI configuration register specified by Address, performs a
 402   bitwise inclusive OR between the read result and the value specified by
 403   OrData, and writes the result to the 16-bit PCI configuration register
 404   specified by Address. The value written to the PCI configuration register is
 405   returned. This function must guarantee that all PCI read and write operations
 406   are serialized.
 407
 408   If Address > 0x0FFFFFFF, then ASSERT().
 409   If Address is not aligned on a 16-bit boundary, then ASSERT().
 410   If the register specified by Address >= 0x100, then ASSERT().
 411
 412   @param  Address Address that encodes the PCI Bus, Device, Function and
 413                   Register.
 414   @param  OrData  The value to OR with the PCI configuration register.
 415
 416   @return The value written back to the PCI configuration register.
 417
 418 **/
 419 UINT16
 420 EFIAPI
 421 PciCf8Or16 (
 422   IN      UINTN                     Address,
 423   IN      UINT16                    OrData
 424   );
 425
 426 /**
 427   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 428   value.
 429
 430   Reads the 16-bit PCI configuration register specified by Address, performs a
 431   bitwise AND between the read result and the value specified by AndData, and
 432   writes the result to the 16-bit PCI configuration register specified by
 433   Address. The value written to the PCI configuration register is returned.
 434   This function must guarantee that all PCI read and write operations are
 435   serialized.
 436
 437   If Address > 0x0FFFFFFF, then ASSERT().
 438   If Address is not aligned on a 16-bit boundary, then ASSERT().
 439   If the register specified by Address >= 0x100, then ASSERT().
 440
 441   @param  Address Address that encodes the PCI Bus, Device, Function and
 442                   Register.
 443   @param  AndData The value to AND with the PCI configuration register.
 444
 445   @return The value written back to the PCI configuration register.
 446
 447 **/
 448 UINT16
 449 EFIAPI
 450 PciCf8And16 (
 451   IN      UINTN                     Address,
 452   IN      UINT16                    AndData
 453   );
 454
 455 /**
 456   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 457   value, followed a  bitwise inclusive OR with another 16-bit value.
 458
 459   Reads the 16-bit PCI configuration register specified by Address, performs a
 460   bitwise AND between the read result and the value specified by AndData,
 461   performs a bitwise inclusive OR between the result of the AND operation and
 462   the value specified by OrData, and writes the result to the 16-bit PCI
 463   configuration register specified by Address. The value written to the PCI
 464   configuration register is returned. This function must guarantee that all PCI
 465   read and write operations are serialized.
 466
 467   If Address > 0x0FFFFFFF, then ASSERT().
 468   If Address is not aligned on a 16-bit boundary, then ASSERT().
 469   If the register specified by Address >= 0x100, then ASSERT().
 470
 471   @param  Address Address that encodes the PCI Bus, Device, Function and
 472                   Register.
 473   @param  AndData The value to AND with the PCI configuration register.
 474   @param  OrData  The value to OR with the result of the AND operation.
 475
 476   @return The value written back to the PCI configuration register.
 477
 478 **/
 479 UINT16
 480 EFIAPI
 481 PciCf8AndThenOr16 (
 482   IN      UINTN                     Address,
 483   IN      UINT16                    AndData,
 484   IN      UINT16                    OrData
 485   );
 486
 487 /**
 488   Reads a bit field of a PCI configuration register.
 489
 490   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 491   specified by the StartBit and the EndBit. The value of the bit field is
 492   returned.
 493
 494   If Address > 0x0FFFFFFF, then ASSERT().
 495   If Address is not aligned on a 16-bit boundary, then ASSERT().
 496   If the register specified by Address >= 0x100, then ASSERT().
 497   If StartBit is greater than 15, then ASSERT().
 498   If EndBit is greater than 15, then ASSERT().
 499   If EndBit is less than or equal to StartBit, then ASSERT().
 500
 501   @param  Address   PCI configuration register to read.
 502   @param  StartBit  The ordinal of the least significant bit in the bit field.
 503                     Range 0..15.
 504   @param  EndBit    The ordinal of the most significant bit in the bit field.
 505                     Range 0..15.
 506
 507   @return The value of the bit field read from the PCI configuration register.
 508
 509 **/
 510 UINT16
 511 EFIAPI
 512 PciCf8BitFieldRead16 (
 513   IN      UINTN                     Address,
 514   IN      UINTN                     StartBit,
 515   IN      UINTN                     EndBit
 516   );
 517
 518 /**
 519   Writes a bit field to a PCI configuration register.
 520
 521   Writes Value to the bit field of the PCI configuration register. The bit
 522   field is specified by the StartBit and the EndBit. All other bits in the
 523   destination PCI configuration register are preserved. The new value of the
 524   16-bit register is returned.
 525
 526   If Address > 0x0FFFFFFF, then ASSERT().
 527   If Address is not aligned on a 16-bit boundary, then ASSERT().
 528   If the register specified by Address >= 0x100, then ASSERT().
 529   If StartBit is greater than 15, then ASSERT().
 530   If EndBit is greater than 15, then ASSERT().
 531   If EndBit is less than or equal to StartBit, then ASSERT().
 532
 533   @param  Address   PCI configuration register to write.
 534   @param  StartBit  The ordinal of the least significant bit in the bit field.
 535                     Range 0..15.
 536   @param  EndBit    The ordinal of the most significant bit in the bit field.
 537                     Range 0..15.
 538   @param  Value     New value of the bit field.
 539
 540   @return The value written back to the PCI configuration register.
 541
 542 **/
 543 UINT16
 544 EFIAPI
 545 PciCf8BitFieldWrite16 (
 546   IN      UINTN                     Address,
 547   IN      UINTN                     StartBit,
 548   IN      UINTN                     EndBit,
 549   IN      UINT16                    Value
 550   );
 551
 552 /**
 553   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 554   writes the result back to the bit field in the 16-bit port.
 555
 556   Reads the 16-bit PCI configuration register specified by Address, performs a
 557   bitwise inclusive OR between the read result and the value specified by
 558   OrData, and writes the result to the 16-bit PCI configuration register
 559   specified by Address. The value written to the PCI configuration register is
 560   returned. This function must guarantee that all PCI read and write operations
 561   are serialized. Extra left bits in OrData are stripped.
 562
 563   If Address > 0x0FFFFFFF, then ASSERT().
 564   If Address is not aligned on a 16-bit boundary, then ASSERT().
 565   If the register specified by Address >= 0x100, then ASSERT().
 566   If StartBit is greater than 15, then ASSERT().
 567   If EndBit is greater than 15, then ASSERT().
 568   If EndBit is less than or equal to StartBit, then ASSERT().
 569
 570   @param  Address   PCI configuration register to write.
 571   @param  StartBit  The ordinal of the least significant bit in the bit field.
 572                     Range 0..15.
 573   @param  EndBit    The ordinal of the most significant bit in the bit field.
 574                     Range 0..15.
 575   @param  OrData    The value to OR with the PCI configuration register.
 576
 577   @return The value written back to the PCI configuration register.
 578
 579 **/
 580 UINT16
 581 EFIAPI
 582 PciCf8BitFieldOr16 (
 583   IN      UINTN                     Address,
 584   IN      UINTN                     StartBit,
 585   IN      UINTN                     EndBit,
 586   IN      UINT16                    OrData
 587   );
 588
 589 /**
 590   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 591   AND, and writes the result back to the bit field in the 16-bit register.
 592
 593   Reads the 16-bit PCI configuration register specified by Address, performs a
 594   bitwise AND between the read result and the value specified by AndData, and
 595   writes the result to the 16-bit PCI configuration register specified by
 596   Address. The value written to the PCI configuration register is returned.
 597   This function must guarantee that all PCI read and write operations are
 598   serialized. Extra left bits in AndData are stripped.
 599
 600   If Address > 0x0FFFFFFF, then ASSERT().
 601   If Address is not aligned on a 16-bit boundary, then ASSERT().
 602   If the register specified by Address >= 0x100, then ASSERT().
 603   If StartBit is greater than 15, then ASSERT().
 604   If EndBit is greater than 15, then ASSERT().
 605   If EndBit is less than or equal to StartBit, then ASSERT().
 606
 607   @param  Address   PCI configuration register to write.
 608   @param  StartBit  The ordinal of the least significant bit in the bit field.
 609                     Range 0..15.
 610   @param  EndBit    The ordinal of the most significant bit in the bit field.
 611                     Range 0..15.
 612   @param  AndData   The value to AND with the PCI configuration register.
 613
 614   @return The value written back to the PCI configuration register.
 615
 616 **/
 617 UINT16
 618 EFIAPI
 619 PciCf8BitFieldAnd16 (
 620   IN      UINTN                     Address,
 621   IN      UINTN                     StartBit,
 622   IN      UINTN                     EndBit,
 623   IN      UINT16                    AndData
 624   );
 625
 626 /**
 627   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 628   bitwise inclusive OR, and writes the result back to the bit field in the
 629   16-bit port.
 630
 631   Reads the 16-bit PCI configuration register specified by Address, performs a
 632   bitwise AND followed by a bitwise inclusive OR between the read result and
 633   the value specified by AndData, and writes the result to the 16-bit PCI
 634   configuration register specified by Address. The value written to the PCI
 635   configuration register is returned. This function must guarantee that all PCI
 636   read and write operations are serialized. Extra left bits in both AndData and
 637   OrData are stripped.
 638
 639   If Address > 0x0FFFFFFF, then ASSERT().
 640   If Address is not aligned on a 16-bit boundary, then ASSERT().
 641   If the register specified by Address >= 0x100, then ASSERT().
 642   If StartBit is greater than 15, then ASSERT().
 643   If EndBit is greater than 15, then ASSERT().
 644   If EndBit is less than or equal to StartBit, then ASSERT().
 645
 646   @param  Address   PCI configuration register to write.
 647   @param  StartBit  The ordinal of the least significant bit in the bit field.
 648                     Range 0..15.
 649   @param  EndBit    The ordinal of the most significant bit in the bit field.
 650                     Range 0..15.
 651   @param  AndData   The value to AND with the PCI configuration register.
 652   @param  OrData    The value to OR with the result of the AND operation.
 653
 654   @return The value written back to the PCI configuration register.
 655
 656 **/
 657 UINT16
 658 EFIAPI
 659 PciCf8BitFieldAndThenOr16 (
 660   IN      UINTN                     Address,
 661   IN      UINTN                     StartBit,
 662   IN      UINTN                     EndBit,
 663   IN      UINT16                    AndData,
 664   IN      UINT16                    OrData
 665   );
 666
 667 /**
 668   Reads a 32-bit PCI configuration register.
 669
 670   Reads and returns the 32-bit PCI configuration register specified by Address.
 671   This function must guarantee that all PCI read and write operations are
 672   serialized.
 673
 674   If Address > 0x0FFFFFFF, then ASSERT().
 675   If Address is not aligned on a 32-bit boundary, then ASSERT().
 676   If the register specified by Address >= 0x100, then ASSERT().
 677
 678   @param  Address Address that encodes the PCI Bus, Device, Function and
 679                   Register.
 680
 681   @return The read value from the PCI configuration register.
 682
 683 **/
 684 UINT32
 685 EFIAPI
 686 PciCf8Read32 (
 687   IN      UINTN                     Address
 688   );
 689
 690 /**
 691   Writes a 32-bit PCI configuration register.
 692
 693   Writes the 32-bit PCI configuration register specified by Address with the
 694   value specified by Value. Value is returned. This function must guarantee
 695   that all PCI read and write operations are serialized.
 696
 697   If Address > 0x0FFFFFFF, then ASSERT().
 698   If Address is not aligned on a 32-bit boundary, then ASSERT().
 699   If the register specified by Address >= 0x100, then ASSERT().
 700
 701   @param  Address Address that encodes the PCI Bus, Device, Function and
 702                   Register.
 703   @param  Value   The value to write.
 704
 705   @return The value written to the PCI configuration register.
 706
 707 **/
 708 UINT32
 709 EFIAPI
 710 PciCf8Write32 (
 711   IN      UINTN                     Address,
 712   IN      UINT32                    Data
 713   );
 714
 715 /**
 716   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 717   a 32-bit value.
 718
 719   Reads the 32-bit PCI configuration register specified by Address, performs a
 720   bitwise inclusive OR between the read result and the value specified by
 721   OrData, and writes the result to the 32-bit PCI configuration register
 722   specified by Address. The value written to the PCI configuration register is
 723   returned. This function must guarantee that all PCI read and write operations
 724   are serialized.
 725
 726   If Address > 0x0FFFFFFF, then ASSERT().
 727   If Address is not aligned on a 32-bit boundary, then ASSERT().
 728   If the register specified by Address >= 0x100, then ASSERT().
 729
 730   @param  Address Address that encodes the PCI Bus, Device, Function and
 731                   Register.
 732   @param  OrData  The value to OR with the PCI configuration register.
 733
 734   @return The value written back to the PCI configuration register.
 735
 736 **/
 737 UINT32
 738 EFIAPI
 739 PciCf8Or32 (
 740   IN      UINTN                     Address,
 741   IN      UINT32                    OrData
 742   );
 743
 744 /**
 745   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 746   value.
 747
 748   Reads the 32-bit PCI configuration register specified by Address, performs a
 749   bitwise AND between the read result and the value specified by AndData, and
 750   writes the result to the 32-bit PCI configuration register specified by
 751   Address. The value written to the PCI configuration register is returned.
 752   This function must guarantee that all PCI read and write operations are
 753   serialized.
 754
 755   If Address > 0x0FFFFFFF, then ASSERT().
 756   If Address is not aligned on a 32-bit boundary, then ASSERT().
 757   If the register specified by Address >= 0x100, then ASSERT().
 758
 759   @param  Address Address that encodes the PCI Bus, Device, Function and
 760                   Register.
 761   @param  AndData The value to AND with the PCI configuration register.
 762
 763   @return The value written back to the PCI configuration register.
 764
 765 **/
 766 UINT32
 767 EFIAPI
 768 PciCf8And32 (
 769   IN      UINTN                     Address,
 770   IN      UINT32                    AndData
 771   );
 772
 773 /**
 774   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 775   value, followed a  bitwise inclusive OR with another 32-bit value.
 776
 777   Reads the 32-bit PCI configuration register specified by Address, performs a
 778   bitwise AND between the read result and the value specified by AndData,
 779   performs a bitwise inclusive OR between the result of the AND operation and
 780   the value specified by OrData, and writes the result to the 32-bit PCI
 781   configuration register specified by Address. The value written to the PCI
 782   configuration register is returned. This function must guarantee that all PCI
 783   read and write operations are serialized.
 784
 785   If Address > 0x0FFFFFFF, then ASSERT().
 786   If Address is not aligned on a 32-bit boundary, then ASSERT().
 787   If the register specified by Address >= 0x100, then ASSERT().
 788
 789   @param  Address Address that encodes the PCI Bus, Device, Function and
 790                   Register.
 791   @param  AndData The value to AND with the PCI configuration register.
 792   @param  OrData  The value to OR with the result of the AND operation.
 793
 794   @return The value written back to the PCI configuration register.
 795
 796 **/
 797 UINT32
 798 EFIAPI
 799 PciCf8AndThenOr32 (
 800   IN      UINTN                     Address,
 801   IN      UINT32                    AndData,
 802   IN      UINT32                    OrData
 803   );
 804
 805 /**
 806   Reads a bit field of a PCI configuration register.
 807
 808   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 809   specified by the StartBit and the EndBit. The value of the bit field is
 810   returned.
 811
 812   If Address > 0x0FFFFFFF, then ASSERT().
 813   If Address is not aligned on a 32-bit boundary, then ASSERT().
 814   If the register specified by Address >= 0x100, then ASSERT().
 815   If StartBit is greater than 31, then ASSERT().
 816   If EndBit is greater than 31, then ASSERT().
 817   If EndBit is less than or equal to StartBit, then ASSERT().
 818
 819   @param  Address   PCI configuration register to read.
 820   @param  StartBit  The ordinal of the least significant bit in the bit field.
 821                     Range 0..31.
 822   @param  EndBit    The ordinal of the most significant bit in the bit field.
 823                     Range 0..31.
 824
 825   @return The value of the bit field read from the PCI configuration register.
 826
 827 **/
 828 UINT32
 829 EFIAPI
 830 PciCf8BitFieldRead32 (
 831   IN      UINTN                     Address,
 832   IN      UINTN                     StartBit,
 833   IN      UINTN                     EndBit
 834   );
 835
 836 /**
 837   Writes a bit field to a PCI configuration register.
 838
 839   Writes Value to the bit field of the PCI configuration register. The bit
 840   field is specified by the StartBit and the EndBit. All other bits in the
 841   destination PCI configuration register are preserved. The new value of the
 842   32-bit register is returned.
 843
 844   If Address > 0x0FFFFFFF, then ASSERT().
 845   If Address is not aligned on a 32-bit boundary, then ASSERT().
 846   If the register specified by Address >= 0x100, then ASSERT().
 847   If StartBit is greater than 31, then ASSERT().
 848   If EndBit is greater than 31, then ASSERT().
 849   If EndBit is less than or equal to StartBit, then ASSERT().
 850
 851   @param  Address   PCI configuration register to write.
 852   @param  StartBit  The ordinal of the least significant bit in the bit field.
 853                     Range 0..31.
 854   @param  EndBit    The ordinal of the most significant bit in the bit field.
 855                     Range 0..31.
 856   @param  Value     New value of the bit field.
 857
 858   @return The value written back to the PCI configuration register.
 859
 860 **/
 861 UINT32
 862 EFIAPI
 863 PciCf8BitFieldWrite32 (
 864   IN      UINTN                     Address,
 865   IN      UINTN                     StartBit,
 866   IN      UINTN                     EndBit,
 867   IN      UINT32                    Value
 868   );
 869
 870 /**
 871   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 872   writes the result back to the bit field in the 32-bit port.
 873
 874   Reads the 32-bit PCI configuration register specified by Address, performs a
 875   bitwise inclusive OR between the read result and the value specified by
 876   OrData, and writes the result to the 32-bit PCI configuration register
 877   specified by Address. The value written to the PCI configuration register is
 878   returned. This function must guarantee that all PCI read and write operations
 879   are serialized. Extra left bits in OrData are stripped.
 880
 881   If Address > 0x0FFFFFFF, then ASSERT().
 882   If Address is not aligned on a 32-bit boundary, then ASSERT().
 883   If the register specified by Address >= 0x100, then ASSERT().
 884   If StartBit is greater than 31, then ASSERT().
 885   If EndBit is greater than 31, then ASSERT().
 886   If EndBit is less than or equal to StartBit, then ASSERT().
 887
 888   @param  Address   PCI configuration register to write.
 889   @param  StartBit  The ordinal of the least significant bit in the bit field.
 890                     Range 0..31.
 891   @param  EndBit    The ordinal of the most significant bit in the bit field.
 892                     Range 0..31.
 893   @param  OrData    The value to OR with the PCI configuration register.
 894
 895   @return The value written back to the PCI configuration register.
 896
 897 **/
 898 UINT32
 899 EFIAPI
 900 PciCf8BitFieldOr32 (
 901   IN      UINTN                     Address,
 902   IN      UINTN                     StartBit,
 903   IN      UINTN                     EndBit,
 904   IN      UINT32                    OrData
 905   );
 906
 907 /**
 908   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 909   AND, and writes the result back to the bit field in the 32-bit register.
 910
 911   Reads the 32-bit PCI configuration register specified by Address, performs a
 912   bitwise AND between the read result and the value specified by AndData, and
 913   writes the result to the 32-bit PCI configuration register specified by
 914   Address. The value written to the PCI configuration register is returned.
 915   This function must guarantee that all PCI read and write operations are
 916   serialized. Extra left bits in AndData are stripped.
 917
 918   If Address > 0x0FFFFFFF, then ASSERT().
 919   If Address is not aligned on a 32-bit boundary, then ASSERT().
 920   If the register specified by Address >= 0x100, then ASSERT().
 921   If StartBit is greater than 31, then ASSERT().
 922   If EndBit is greater than 31, then ASSERT().
 923   If EndBit is less than or equal to StartBit, then ASSERT().
 924
 925   @param  Address   PCI configuration register to write.
 926   @param  StartBit  The ordinal of the least significant bit in the bit field.
 927                     Range 0..31.
 928   @param  EndBit    The ordinal of the most significant bit in the bit field.
 929                     Range 0..31.
 930   @param  AndData   The value to AND with the PCI configuration register.
 931
 932   @return The value written back to the PCI configuration register.
 933
 934 **/
 935 UINT32
 936 EFIAPI
 937 PciCf8BitFieldAnd32 (
 938   IN      UINTN                     Address,
 939   IN      UINTN                     StartBit,
 940   IN      UINTN                     EndBit,
 941   IN      UINT32                    AndData
 942   );
 943
 944 /**
 945   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 946   bitwise inclusive OR, and writes the result back to the bit field in the
 947   32-bit port.
 948
 949   Reads the 32-bit PCI configuration register specified by Address, performs a
 950   bitwise AND followed by a bitwise inclusive OR between the read result and
 951   the value specified by AndData, and writes the result to the 32-bit PCI
 952   configuration register specified by Address. The value written to the PCI
 953   configuration register is returned. This function must guarantee that all PCI
 954   read and write operations are serialized. Extra left bits in both AndData and
 955   OrData are stripped.
 956
 957   If Address > 0x0FFFFFFF, then ASSERT().
 958   If Address is not aligned on a 32-bit boundary, then ASSERT().
 959   If the register specified by Address >= 0x100, then ASSERT().
 960   If StartBit is greater than 31, then ASSERT().
 961   If EndBit is greater than 31, then ASSERT().
 962   If EndBit is less than or equal to StartBit, then ASSERT().
 963
 964   @param  Address   PCI configuration register to write.
 965   @param  StartBit  The ordinal of the least significant bit in the bit field.
 966                     Range 0..31.
 967   @param  EndBit    The ordinal of the most significant bit in the bit field.
 968                     Range 0..31.
 969   @param  AndData   The value to AND with the PCI configuration register.
 970   @param  OrData    The value to OR with the result of the AND operation.
 971
 972   @return The value written back to the PCI configuration register.
 973
 974 **/
 975 UINT32
 976 EFIAPI
 977 PciCf8BitFieldAndThenOr32 (
 978   IN      UINTN                     Address,
 979   IN      UINTN                     StartBit,
 980   IN      UINTN                     EndBit,
 981   IN      UINT32                    AndData,
 982   IN      UINT32                    OrData
 983   );
 984
 985 /**
 986   Reads a range of PCI configuration registers into a caller supplied buffer.
 987
 988   Reads the range of PCI configuration registers specified by StartAddress and
 989   Size into the buffer specified by Buffer. This function only allows the PCI
 990   configuration registers from a single PCI function to be read. Size is
 991   returned. When possible 32-bit PCI configuration read cycles are used to read
 992   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
 993   and 16-bit PCI configuration read cycles may be used at the beginning and the
 994   end of the range.
 995
 996   If StartAddress > 0x0FFFFFFF, then ASSERT().
 997   If the register specified by StartAddress >= 0x100, then ASSERT().
 998   If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
 999   If (StartAddress + Size - 1)  > 0x0FFFFFFF, then ASSERT().
1000   If Buffer is NULL, then ASSERT().
1001
1002   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1003                         Function and Register.
1004   @param  Size          Size in bytes of the transfer.
1005   @param  Buffer        Pointer to a buffer receiving the data read.
1006
1007   @return Size
1008
1009 **/
1010 UINTN
1011 EFIAPI
1012 PciCf8ReadBuffer (
1013   IN      UINTN                     StartAddress,
1014   IN      UINTN                     Size,
1015   OUT     VOID                      *Buffer
1016   );
1017
1018 /**
1019   Copies the data in a caller supplied buffer to a specified range of PCI
1020   configuration space.
1021
1022   Writes the range of PCI configuration registers specified by StartAddress and
1023   Size from the buffer specified by Buffer. This function only allows the PCI
1024   configuration registers from a single PCI function to be written. Size is
1025   returned. When possible 32-bit PCI configuration write cycles are used to
1026   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1027   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1028   and the end of the range.
1029
1030   If StartAddress > 0x0FFFFFFF, then ASSERT().
1031   If the register specified by StartAddress >= 0x100, then ASSERT().
1032   If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1033   If (StartAddress + Size - 1)  > 0x0FFFFFFF, then ASSERT().
1034   If Buffer is NULL, then ASSERT().
1035
1036   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1037                         Function and Register.
1038   @param  Size          Size in bytes of the transfer.
1039   @param  Buffer        Pointer to a buffer containing the data to write.
1040
1041   @return Size
1042
1043 **/
1044 UINTN
1045 EFIAPI
1046 PciCf8WriteBuffer (
1047   IN      UINTN                     StartAddress,
1048   IN      UINTN                     Size,
1049   IN      VOID                      *Buffer
1050   );
1051
1052 #endif