MdePkg/Include/Library/PciExpressLib.h

   1 /** @file
   2   Pci Express Library Services for PCI Segment #0
   3
   4   Copyright (c) 2006, Intel Corporation
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef __PCI_EXPRESS_LIB_H__
  16 #define __PCI_EXPRESS_LIB_H__
  17
  18 #include <Library/PciLib.h>
  19
  20 /**
  21   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  22   address that can be passed to the PCI Library functions.
  23
  24   Computes an address that is compatible with the PCI Library functions. The
  25   unused upper bits of Bus, Device, Function and Register are stripped prior to
  26   the generation of the address.
  27
  28   @param  Bus       PCI Bus number. Range 0..255.
  29   @param  Device    PCI Device number. Range 0..31.
  30   @param  Function  PCI Function number. Range 0..7.
  31   @param  Register  PCI Register number. Range 0..4095.
  32
  33   @return The encode PCI address.
  34
  35 **/
  36 #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \
  37   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  38
  39 /**
  40   Reads an 8-bit PCI configuration register.
  41
  42   Reads and returns the 8-bit PCI configuration register specified by Address.
  43   This function must guarantee that all PCI read and write operations are
  44   serialized.
  45
  46   If Address > 0x0FFFFFFF, then ASSERT().
  47
  48   @param  Address Address that encodes the PCI Bus, Device, Function and
  49                   Register.
  50
  51   @return The read value from the PCI configuration register.
  52
  53 **/
  54 UINT8
  55 EFIAPI
  56 PciExpressRead8 (
  57   IN      UINTN                     Address
  58   );
  59
  60 /**
  61   Writes an 8-bit PCI configuration register.
  62
  63   Writes the 8-bit PCI configuration register specified by Address with the
  64   value specified by Value. Value is returned. This function must guarantee
  65   that all PCI read and write operations are serialized.
  66
  67   If Address > 0x0FFFFFFF, then ASSERT().
  68
  69   @param  Address Address that encodes the PCI Bus, Device, Function and
  70                   Register.
  71   @param  Value   The value to write.
  72
  73   @return The value written to the PCI configuration register.
  74
  75 **/
  76 UINT8
  77 EFIAPI
  78 PciExpressWrite8 (
  79   IN      UINTN                     Address,
  80   IN      UINT8                     Data
  81   );
  82
  83 /**
  84   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
  85   an 8-bit value.
  86
  87   Reads the 8-bit PCI configuration register specified by Address, performs a
  88   bitwise inclusive OR between the read result and the value specified by
  89   OrData, and writes the result to the 8-bit PCI configuration register
  90   specified by Address. The value written to the PCI configuration register is
  91   returned. This function must guarantee that all PCI read and write operations
  92   are serialized.
  93
  94   If Address > 0x0FFFFFFF, then ASSERT().
  95
  96   @param  Address Address that encodes the PCI Bus, Device, Function and
  97                   Register.
  98   @param  OrData  The value to OR with the PCI configuration register.
  99
 100   @return The value written back to the PCI configuration register.
 101
 102 **/
 103 UINT8
 104 EFIAPI
 105 PciExpressOr8 (
 106   IN      UINTN                     Address,
 107   IN      UINT8                     OrData
 108   );
 109
 110 /**
 111   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 112   value.
 113
 114   Reads the 8-bit PCI configuration register specified by Address, performs a
 115   bitwise AND between the read result and the value specified by AndData, and
 116   writes the result to the 8-bit PCI configuration register specified by
 117   Address. The value written to the PCI configuration register is returned.
 118   This function must guarantee that all PCI read and write operations are
 119   serialized.
 120
 121   If Address > 0x0FFFFFFF, then ASSERT().
 122
 123   @param  Address Address that encodes the PCI Bus, Device, Function and
 124                   Register.
 125   @param  AndData The value to AND with the PCI configuration register.
 126
 127   @return The value written back to the PCI configuration register.
 128
 129 **/
 130 UINT8
 131 EFIAPI
 132 PciExpressAnd8 (
 133   IN      UINTN                     Address,
 134   IN      UINT8                     AndData
 135   );
 136
 137 /**
 138   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 139   value, followed a  bitwise inclusive OR with another 8-bit value.
 140
 141   Reads the 8-bit PCI configuration register specified by Address, performs a
 142   bitwise AND between the read result and the value specified by AndData,
 143   performs a bitwise inclusive OR between the result of the AND operation and
 144   the value specified by OrData, and writes the result to the 8-bit PCI
 145   configuration register specified by Address. The value written to the PCI
 146   configuration register is returned. This function must guarantee that all PCI
 147   read and write operations are serialized.
 148
 149   If Address > 0x0FFFFFFF, then ASSERT().
 150
 151   @param  Address Address that encodes the PCI Bus, Device, Function and
 152                   Register.
 153   @param  AndData The value to AND with the PCI configuration register.
 154   @param  OrData  The value to OR with the result of the AND operation.
 155
 156   @return The value written back to the PCI configuration register.
 157
 158 **/
 159 UINT8
 160 EFIAPI
 161 PciExpressAndThenOr8 (
 162   IN      UINTN                     Address,
 163   IN      UINT8                     AndData,
 164   IN      UINT8                     OrData
 165   );
 166
 167 /**
 168   Reads a bit field of a PCI configuration register.
 169
 170   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 171   specified by the StartBit and the EndBit. The value of the bit field is
 172   returned.
 173
 174   If Address > 0x0FFFFFFF, then ASSERT().
 175   If StartBit is greater than 7, then ASSERT().
 176   If EndBit is greater than 7, then ASSERT().
 177   If EndBit is less than StartBit, then ASSERT().
 178
 179   @param  Address   PCI configuration register to read.
 180   @param  StartBit  The ordinal of the least significant bit in the bit field.
 181                     Range 0..7.
 182   @param  EndBit    The ordinal of the most significant bit in the bit field.
 183                     Range 0..7.
 184
 185   @return The value of the bit field read from the PCI configuration register.
 186
 187 **/
 188 UINT8
 189 EFIAPI
 190 PciExpressBitFieldRead8 (
 191   IN      UINTN                     Address,
 192   IN      UINTN                     StartBit,
 193   IN      UINTN                     EndBit
 194   );
 195
 196 /**
 197   Writes a bit field to a PCI configuration register.
 198
 199   Writes Value to the bit field of the PCI configuration register. The bit
 200   field is specified by the StartBit and the EndBit. All other bits in the
 201   destination PCI configuration register are preserved. The new value of the
 202   8-bit register is returned.
 203
 204   If Address > 0x0FFFFFFF, then ASSERT().
 205   If StartBit is greater than 7, then ASSERT().
 206   If EndBit is greater than 7, then ASSERT().
 207   If EndBit is less than StartBit, then ASSERT().
 208
 209   @param  Address   PCI configuration register to write.
 210   @param  StartBit  The ordinal of the least significant bit in the bit field.
 211                     Range 0..7.
 212   @param  EndBit    The ordinal of the most significant bit in the bit field.
 213                     Range 0..7.
 214   @param  Value     New value of the bit field.
 215
 216   @return The value written back to the PCI configuration register.
 217
 218 **/
 219 UINT8
 220 EFIAPI
 221 PciExpressBitFieldWrite8 (
 222   IN      UINTN                     Address,
 223   IN      UINTN                     StartBit,
 224   IN      UINTN                     EndBit,
 225   IN      UINT8                     Value
 226   );
 227
 228 /**
 229   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 230   writes the result back to the bit field in the 8-bit port.
 231
 232   Reads the 8-bit PCI configuration register specified by Address, performs a
 233   bitwise inclusive OR between the read result and the value specified by
 234   OrData, and writes the result to the 8-bit PCI configuration register
 235   specified by Address. The value written to the PCI configuration register is
 236   returned. This function must guarantee that all PCI read and write operations
 237   are serialized. Extra left bits in OrData are stripped.
 238
 239   If Address > 0x0FFFFFFF, then ASSERT().
 240   If StartBit is greater than 7, then ASSERT().
 241   If EndBit is greater than 7, then ASSERT().
 242   If EndBit is less than StartBit, then ASSERT().
 243
 244   @param  Address   PCI configuration register to write.
 245   @param  StartBit  The ordinal of the least significant bit in the bit field.
 246                     Range 0..7.
 247   @param  EndBit    The ordinal of the most significant bit in the bit field.
 248                     Range 0..7.
 249   @param  OrData    The value to OR with the PCI configuration register.
 250
 251   @return The value written back to the PCI configuration register.
 252
 253 **/
 254 UINT8
 255 EFIAPI
 256 PciExpressBitFieldOr8 (
 257   IN      UINTN                     Address,
 258   IN      UINTN                     StartBit,
 259   IN      UINTN                     EndBit,
 260   IN      UINT8                     OrData
 261   );
 262
 263 /**
 264   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 265   AND, and writes the result back to the bit field in the 8-bit register.
 266
 267   Reads the 8-bit PCI configuration register specified by Address, performs a
 268   bitwise AND between the read result and the value specified by AndData, and
 269   writes the result to the 8-bit PCI configuration register specified by
 270   Address. The value written to the PCI configuration register is returned.
 271   This function must guarantee that all PCI read and write operations are
 272   serialized. Extra left bits in AndData are stripped.
 273
 274   If Address > 0x0FFFFFFF, then ASSERT().
 275   If StartBit is greater than 7, then ASSERT().
 276   If EndBit is greater than 7, then ASSERT().
 277   If EndBit is less than StartBit, then ASSERT().
 278
 279   @param  Address   PCI configuration register to write.
 280   @param  StartBit  The ordinal of the least significant bit in the bit field.
 281                     Range 0..7.
 282   @param  EndBit    The ordinal of the most significant bit in the bit field.
 283                     Range 0..7.
 284   @param  AndData   The value to AND with the PCI configuration register.
 285
 286   @return The value written back to the PCI configuration register.
 287
 288 **/
 289 UINT8
 290 EFIAPI
 291 PciExpressBitFieldAnd8 (
 292   IN      UINTN                     Address,
 293   IN      UINTN                     StartBit,
 294   IN      UINTN                     EndBit,
 295   IN      UINT8                     AndData
 296   );
 297
 298 /**
 299   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 300   bitwise inclusive OR, and writes the result back to the bit field in the
 301   8-bit port.
 302
 303   Reads the 8-bit PCI configuration register specified by Address, performs a
 304   bitwise AND followed by a bitwise inclusive OR between the read result and
 305   the value specified by AndData, and writes the result to the 8-bit PCI
 306   configuration register specified by Address. The value written to the PCI
 307   configuration register is returned. This function must guarantee that all PCI
 308   read and write operations are serialized. Extra left bits in both AndData and
 309   OrData are stripped.
 310
 311   If Address > 0x0FFFFFFF, then ASSERT().
 312   If StartBit is greater than 7, then ASSERT().
 313   If EndBit is greater than 7, then ASSERT().
 314   If EndBit is less than StartBit, then ASSERT().
 315
 316   @param  Address   PCI configuration register to write.
 317   @param  StartBit  The ordinal of the least significant bit in the bit field.
 318                     Range 0..7.
 319   @param  EndBit    The ordinal of the most significant bit in the bit field.
 320                     Range 0..7.
 321   @param  AndData   The value to AND with the PCI configuration register.
 322   @param  OrData    The value to OR with the result of the AND operation.
 323
 324   @return The value written back to the PCI configuration register.
 325
 326 **/
 327 UINT8
 328 EFIAPI
 329 PciExpressBitFieldAndThenOr8 (
 330   IN      UINTN                     Address,
 331   IN      UINTN                     StartBit,
 332   IN      UINTN                     EndBit,
 333   IN      UINT8                     AndData,
 334   IN      UINT8                     OrData
 335   );
 336
 337 /**
 338   Reads a 16-bit PCI configuration register.
 339
 340   Reads and returns the 16-bit PCI configuration register specified by Address.
 341   This function must guarantee that all PCI read and write operations are
 342   serialized.
 343
 344   If Address > 0x0FFFFFFF, then ASSERT().
 345   If Address is not aligned on a 16-bit boundary, then ASSERT().
 346
 347   @param  Address Address that encodes the PCI Bus, Device, Function and
 348                   Register.
 349
 350   @return The read value from the PCI configuration register.
 351
 352 **/
 353 UINT16
 354 EFIAPI
 355 PciExpressRead16 (
 356   IN      UINTN                     Address
 357   );
 358
 359 /**
 360   Writes a 16-bit PCI configuration register.
 361
 362   Writes the 16-bit PCI configuration register specified by Address with the
 363   value specified by Value. Value is returned. This function must guarantee
 364   that all PCI read and write operations are serialized.
 365
 366   If Address > 0x0FFFFFFF, then ASSERT().
 367   If Address is not aligned on a 16-bit boundary, then ASSERT().
 368
 369   @param  Address Address that encodes the PCI Bus, Device, Function and
 370                   Register.
 371   @param  Value   The value to write.
 372
 373   @return The value written to the PCI configuration register.
 374
 375 **/
 376 UINT16
 377 EFIAPI
 378 PciExpressWrite16 (
 379   IN      UINTN                     Address,
 380   IN      UINT16                    Data
 381   );
 382
 383 /**
 384   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 385   a 16-bit value.
 386
 387   Reads the 16-bit PCI configuration register specified by Address, performs a
 388   bitwise inclusive OR between the read result and the value specified by
 389   OrData, and writes the result to the 16-bit PCI configuration register
 390   specified by Address. The value written to the PCI configuration register is
 391   returned. This function must guarantee that all PCI read and write operations
 392   are serialized.
 393
 394   If Address > 0x0FFFFFFF, then ASSERT().
 395   If Address is not aligned on a 16-bit boundary, then ASSERT().
 396
 397   @param  Address Address that encodes the PCI Bus, Device, Function and
 398                   Register.
 399   @param  OrData  The value to OR with the PCI configuration register.
 400
 401   @return The value written back to the PCI configuration register.
 402
 403 **/
 404 UINT16
 405 EFIAPI
 406 PciExpressOr16 (
 407   IN      UINTN                     Address,
 408   IN      UINT16                    OrData
 409   );
 410
 411 /**
 412   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 413   value.
 414
 415   Reads the 16-bit PCI configuration register specified by Address, performs a
 416   bitwise AND between the read result and the value specified by AndData, and
 417   writes the result to the 16-bit PCI configuration register specified by
 418   Address. The value written to the PCI configuration register is returned.
 419   This function must guarantee that all PCI read and write operations are
 420   serialized.
 421
 422   If Address > 0x0FFFFFFF, then ASSERT().
 423   If Address is not aligned on a 16-bit boundary, then ASSERT().
 424
 425   @param  Address Address that encodes the PCI Bus, Device, Function and
 426                   Register.
 427   @param  AndData The value to AND with the PCI configuration register.
 428
 429   @return The value written back to the PCI configuration register.
 430
 431 **/
 432 UINT16
 433 EFIAPI
 434 PciExpressAnd16 (
 435   IN      UINTN                     Address,
 436   IN      UINT16                    AndData
 437   );
 438
 439 /**
 440   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 441   value, followed a  bitwise inclusive OR with another 16-bit value.
 442
 443   Reads the 16-bit PCI configuration register specified by Address, performs a
 444   bitwise AND between the read result and the value specified by AndData,
 445   performs a bitwise inclusive OR between the result of the AND operation and
 446   the value specified by OrData, and writes the result to the 16-bit PCI
 447   configuration register specified by Address. The value written to the PCI
 448   configuration register is returned. This function must guarantee that all PCI
 449   read and write operations are serialized.
 450
 451   If Address > 0x0FFFFFFF, then ASSERT().
 452   If Address is not aligned on a 16-bit boundary, then ASSERT().
 453
 454   @param  Address Address that encodes the PCI Bus, Device, Function and
 455                   Register.
 456   @param  AndData The value to AND with the PCI configuration register.
 457   @param  OrData  The value to OR with the result of the AND operation.
 458
 459   @return The value written back to the PCI configuration register.
 460
 461 **/
 462 UINT16
 463 EFIAPI
 464 PciExpressAndThenOr16 (
 465   IN      UINTN                     Address,
 466   IN      UINT16                    AndData,
 467   IN      UINT16                    OrData
 468   );
 469
 470 /**
 471   Reads a bit field of a PCI configuration register.
 472
 473   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 474   specified by the StartBit and the EndBit. The value of the bit field is
 475   returned.
 476
 477   If Address > 0x0FFFFFFF, then ASSERT().
 478   If Address is not aligned on a 16-bit boundary, then ASSERT().
 479   If StartBit is greater than 15, then ASSERT().
 480   If EndBit is greater than 15, then ASSERT().
 481   If EndBit is less than StartBit, then ASSERT().
 482
 483   @param  Address   PCI configuration register to read.
 484   @param  StartBit  The ordinal of the least significant bit in the bit field.
 485                     Range 0..15.
 486   @param  EndBit    The ordinal of the most significant bit in the bit field.
 487                     Range 0..15.
 488
 489   @return The value of the bit field read from the PCI configuration register.
 490
 491 **/
 492 UINT16
 493 EFIAPI
 494 PciExpressBitFieldRead16 (
 495   IN      UINTN                     Address,
 496   IN      UINTN                     StartBit,
 497   IN      UINTN                     EndBit
 498   );
 499
 500 /**
 501   Writes a bit field to a PCI configuration register.
 502
 503   Writes Value to the bit field of the PCI configuration register. The bit
 504   field is specified by the StartBit and the EndBit. All other bits in the
 505   destination PCI configuration register are preserved. The new value of the
 506   16-bit register is returned.
 507
 508   If Address > 0x0FFFFFFF, then ASSERT().
 509   If Address is not aligned on a 16-bit boundary, then ASSERT().
 510   If StartBit is greater than 15, then ASSERT().
 511   If EndBit is greater than 15, then ASSERT().
 512   If EndBit is less than StartBit, then ASSERT().
 513
 514   @param  Address   PCI configuration register to write.
 515   @param  StartBit  The ordinal of the least significant bit in the bit field.
 516                     Range 0..15.
 517   @param  EndBit    The ordinal of the most significant bit in the bit field.
 518                     Range 0..15.
 519   @param  Value     New value of the bit field.
 520
 521   @return The value written back to the PCI configuration register.
 522
 523 **/
 524 UINT16
 525 EFIAPI
 526 PciExpressBitFieldWrite16 (
 527   IN      UINTN                     Address,
 528   IN      UINTN                     StartBit,
 529   IN      UINTN                     EndBit,
 530   IN      UINT16                    Value
 531   );
 532
 533 /**
 534   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 535   writes the result back to the bit field in the 16-bit port.
 536
 537   Reads the 16-bit PCI configuration register specified by Address, performs a
 538   bitwise inclusive OR between the read result and the value specified by
 539   OrData, and writes the result to the 16-bit PCI configuration register
 540   specified by Address. The value written to the PCI configuration register is
 541   returned. This function must guarantee that all PCI read and write operations
 542   are serialized. Extra left bits in OrData are stripped.
 543
 544   If Address > 0x0FFFFFFF, then ASSERT().
 545   If Address is not aligned on a 16-bit boundary, then ASSERT().
 546   If StartBit is greater than 15, then ASSERT().
 547   If EndBit is greater than 15, then ASSERT().
 548   If EndBit is less than StartBit, then ASSERT().
 549
 550   @param  Address   PCI configuration register to write.
 551   @param  StartBit  The ordinal of the least significant bit in the bit field.
 552                     Range 0..15.
 553   @param  EndBit    The ordinal of the most significant bit in the bit field.
 554                     Range 0..15.
 555   @param  OrData    The value to OR with the PCI configuration register.
 556
 557   @return The value written back to the PCI configuration register.
 558
 559 **/
 560 UINT16
 561 EFIAPI
 562 PciExpressBitFieldOr16 (
 563   IN      UINTN                     Address,
 564   IN      UINTN                     StartBit,
 565   IN      UINTN                     EndBit,
 566   IN      UINT16                    OrData
 567   );
 568
 569 /**
 570   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 571   AND, and writes the result back to the bit field in the 16-bit register.
 572
 573   Reads the 16-bit PCI configuration register specified by Address, performs a
 574   bitwise AND between the read result and the value specified by AndData, and
 575   writes the result to the 16-bit PCI configuration register specified by
 576   Address. The value written to the PCI configuration register is returned.
 577   This function must guarantee that all PCI read and write operations are
 578   serialized. Extra left bits in AndData are stripped.
 579
 580   If Address > 0x0FFFFFFF, then ASSERT().
 581   If Address is not aligned on a 16-bit boundary, then ASSERT().
 582   If StartBit is greater than 15, then ASSERT().
 583   If EndBit is greater than 15, then ASSERT().
 584   If EndBit is less than StartBit, then ASSERT().
 585
 586   @param  Address   PCI configuration register to write.
 587   @param  StartBit  The ordinal of the least significant bit in the bit field.
 588                     Range 0..15.
 589   @param  EndBit    The ordinal of the most significant bit in the bit field.
 590                     Range 0..15.
 591   @param  AndData   The value to AND with the PCI configuration register.
 592
 593   @return The value written back to the PCI configuration register.
 594
 595 **/
 596 UINT16
 597 EFIAPI
 598 PciExpressBitFieldAnd16 (
 599   IN      UINTN                     Address,
 600   IN      UINTN                     StartBit,
 601   IN      UINTN                     EndBit,
 602   IN      UINT16                    AndData
 603   );
 604
 605 /**
 606   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 607   bitwise inclusive OR, and writes the result back to the bit field in the
 608   16-bit port.
 609
 610   Reads the 16-bit PCI configuration register specified by Address, performs a
 611   bitwise AND followed by a bitwise inclusive OR between the read result and
 612   the value specified by AndData, and writes the result to the 16-bit PCI
 613   configuration register specified by Address. The value written to the PCI
 614   configuration register is returned. This function must guarantee that all PCI
 615   read and write operations are serialized. Extra left bits in both AndData and
 616   OrData are stripped.
 617
 618   If Address > 0x0FFFFFFF, then ASSERT().
 619   If Address is not aligned on a 16-bit boundary, then ASSERT().
 620   If StartBit is greater than 15, then ASSERT().
 621   If EndBit is greater than 15, then ASSERT().
 622   If EndBit is less than StartBit, then ASSERT().
 623
 624   @param  Address   PCI configuration register to write.
 625   @param  StartBit  The ordinal of the least significant bit in the bit field.
 626                     Range 0..15.
 627   @param  EndBit    The ordinal of the most significant bit in the bit field.
 628                     Range 0..15.
 629   @param  AndData   The value to AND with the PCI configuration register.
 630   @param  OrData    The value to OR with the result of the AND operation.
 631
 632   @return The value written back to the PCI configuration register.
 633
 634 **/
 635 UINT16
 636 EFIAPI
 637 PciExpressBitFieldAndThenOr16 (
 638   IN      UINTN                     Address,
 639   IN      UINTN                     StartBit,
 640   IN      UINTN                     EndBit,
 641   IN      UINT16                    AndData,
 642   IN      UINT16                    OrData
 643   );
 644
 645 /**
 646   Reads a 32-bit PCI configuration register.
 647
 648   Reads and returns the 32-bit PCI configuration register specified by Address.
 649   This function must guarantee that all PCI read and write operations are
 650   serialized.
 651
 652   If Address > 0x0FFFFFFF, then ASSERT().
 653   If Address is not aligned on a 32-bit boundary, then ASSERT().
 654
 655   @param  Address Address that encodes the PCI Bus, Device, Function and
 656                   Register.
 657
 658   @return The read value from the PCI configuration register.
 659
 660 **/
 661 UINT32
 662 EFIAPI
 663 PciExpressRead32 (
 664   IN      UINTN                     Address
 665   );
 666
 667 /**
 668   Writes a 32-bit PCI configuration register.
 669
 670   Writes the 32-bit PCI configuration register specified by Address with the
 671   value specified by Value. Value is returned. This function must guarantee
 672   that all PCI read and write operations are serialized.
 673
 674   If Address > 0x0FFFFFFF, then ASSERT().
 675   If Address is not aligned on a 32-bit boundary, then ASSERT().
 676
 677   @param  Address Address that encodes the PCI Bus, Device, Function and
 678                   Register.
 679   @param  Value   The value to write.
 680
 681   @return The value written to the PCI configuration register.
 682
 683 **/
 684 UINT32
 685 EFIAPI
 686 PciExpressWrite32 (
 687   IN      UINTN                     Address,
 688   IN      UINT32                    Data
 689   );
 690
 691 /**
 692   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 693   a 32-bit value.
 694
 695   Reads the 32-bit PCI configuration register specified by Address, performs a
 696   bitwise inclusive OR between the read result and the value specified by
 697   OrData, and writes the result to the 32-bit PCI configuration register
 698   specified by Address. The value written to the PCI configuration register is
 699   returned. This function must guarantee that all PCI read and write operations
 700   are serialized.
 701
 702   If Address > 0x0FFFFFFF, then ASSERT().
 703   If Address is not aligned on a 32-bit boundary, then ASSERT().
 704
 705   @param  Address Address that encodes the PCI Bus, Device, Function and
 706                   Register.
 707   @param  OrData  The value to OR with the PCI configuration register.
 708
 709   @return The value written back to the PCI configuration register.
 710
 711 **/
 712 UINT32
 713 EFIAPI
 714 PciExpressOr32 (
 715   IN      UINTN                     Address,
 716   IN      UINT32                    OrData
 717   );
 718
 719 /**
 720   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 721   value.
 722
 723   Reads the 32-bit PCI configuration register specified by Address, performs a
 724   bitwise AND between the read result and the value specified by AndData, and
 725   writes the result to the 32-bit PCI configuration register specified by
 726   Address. The value written to the PCI configuration register is returned.
 727   This function must guarantee that all PCI read and write operations are
 728   serialized.
 729
 730   If Address > 0x0FFFFFFF, then ASSERT().
 731   If Address is not aligned on a 32-bit boundary, then ASSERT().
 732
 733   @param  Address Address that encodes the PCI Bus, Device, Function and
 734                   Register.
 735   @param  AndData The value to AND with the PCI configuration register.
 736
 737   @return The value written back to the PCI configuration register.
 738
 739 **/
 740 UINT32
 741 EFIAPI
 742 PciExpressAnd32 (
 743   IN      UINTN                     Address,
 744   IN      UINT32                    AndData
 745   );
 746
 747 /**
 748   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 749   value, followed a  bitwise inclusive OR with another 32-bit value.
 750
 751   Reads the 32-bit PCI configuration register specified by Address, performs a
 752   bitwise AND between the read result and the value specified by AndData,
 753   performs a bitwise inclusive OR between the result of the AND operation and
 754   the value specified by OrData, and writes the result to the 32-bit PCI
 755   configuration register specified by Address. The value written to the PCI
 756   configuration register is returned. This function must guarantee that all PCI
 757   read and write operations are serialized.
 758
 759   If Address > 0x0FFFFFFF, then ASSERT().
 760   If Address is not aligned on a 32-bit boundary, then ASSERT().
 761
 762   @param  Address Address that encodes the PCI Bus, Device, Function and
 763                   Register.
 764   @param  AndData The value to AND with the PCI configuration register.
 765   @param  OrData  The value to OR with the result of the AND operation.
 766
 767   @return The value written back to the PCI configuration register.
 768
 769 **/
 770 UINT32
 771 EFIAPI
 772 PciExpressAndThenOr32 (
 773   IN      UINTN                     Address,
 774   IN      UINT32                    AndData,
 775   IN      UINT32                    OrData
 776   );
 777
 778 /**
 779   Reads a bit field of a PCI configuration register.
 780
 781   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 782   specified by the StartBit and the EndBit. The value of the bit field is
 783   returned.
 784
 785   If Address > 0x0FFFFFFF, then ASSERT().
 786   If Address is not aligned on a 32-bit boundary, then ASSERT().
 787   If StartBit is greater than 31, then ASSERT().
 788   If EndBit is greater than 31, then ASSERT().
 789   If EndBit is less than StartBit, then ASSERT().
 790
 791   @param  Address   PCI configuration register to read.
 792   @param  StartBit  The ordinal of the least significant bit in the bit field.
 793                     Range 0..31.
 794   @param  EndBit    The ordinal of the most significant bit in the bit field.
 795                     Range 0..31.
 796
 797   @return The value of the bit field read from the PCI configuration register.
 798
 799 **/
 800 UINT32
 801 EFIAPI
 802 PciExpressBitFieldRead32 (
 803   IN      UINTN                     Address,
 804   IN      UINTN                     StartBit,
 805   IN      UINTN                     EndBit
 806   );
 807
 808 /**
 809   Writes a bit field to a PCI configuration register.
 810
 811   Writes Value to the bit field of the PCI configuration register. The bit
 812   field is specified by the StartBit and the EndBit. All other bits in the
 813   destination PCI configuration register are preserved. The new value of the
 814   32-bit register is returned.
 815
 816   If Address > 0x0FFFFFFF, then ASSERT().
 817   If Address is not aligned on a 32-bit boundary, then ASSERT().
 818   If StartBit is greater than 31, then ASSERT().
 819   If EndBit is greater than 31, then ASSERT().
 820   If EndBit is less than StartBit, then ASSERT().
 821
 822   @param  Address   PCI configuration register to write.
 823   @param  StartBit  The ordinal of the least significant bit in the bit field.
 824                     Range 0..31.
 825   @param  EndBit    The ordinal of the most significant bit in the bit field.
 826                     Range 0..31.
 827   @param  Value     New value of the bit field.
 828
 829   @return The value written back to the PCI configuration register.
 830
 831 **/
 832 UINT32
 833 EFIAPI
 834 PciExpressBitFieldWrite32 (
 835   IN      UINTN                     Address,
 836   IN      UINTN                     StartBit,
 837   IN      UINTN                     EndBit,
 838   IN      UINT32                    Value
 839   );
 840
 841 /**
 842   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 843   writes the result back to the bit field in the 32-bit port.
 844
 845   Reads the 32-bit PCI configuration register specified by Address, performs a
 846   bitwise inclusive OR between the read result and the value specified by
 847   OrData, and writes the result to the 32-bit PCI configuration register
 848   specified by Address. The value written to the PCI configuration register is
 849   returned. This function must guarantee that all PCI read and write operations
 850   are serialized. Extra left bits in OrData are stripped.
 851
 852   If Address > 0x0FFFFFFF, then ASSERT().
 853   If Address is not aligned on a 32-bit boundary, then ASSERT().
 854   If StartBit is greater than 31, then ASSERT().
 855   If EndBit is greater than 31, then ASSERT().
 856   If EndBit is less than StartBit, then ASSERT().
 857
 858   @param  Address   PCI configuration register to write.
 859   @param  StartBit  The ordinal of the least significant bit in the bit field.
 860                     Range 0..31.
 861   @param  EndBit    The ordinal of the most significant bit in the bit field.
 862                     Range 0..31.
 863   @param  OrData    The value to OR with the PCI configuration register.
 864
 865   @return The value written back to the PCI configuration register.
 866
 867 **/
 868 UINT32
 869 EFIAPI
 870 PciExpressBitFieldOr32 (
 871   IN      UINTN                     Address,
 872   IN      UINTN                     StartBit,
 873   IN      UINTN                     EndBit,
 874   IN      UINT32                    OrData
 875   );
 876
 877 /**
 878   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 879   AND, and writes the result back to the bit field in the 32-bit register.
 880
 881   Reads the 32-bit PCI configuration register specified by Address, performs a
 882   bitwise AND between the read result and the value specified by AndData, and
 883   writes the result to the 32-bit PCI configuration register specified by
 884   Address. The value written to the PCI configuration register is returned.
 885   This function must guarantee that all PCI read and write operations are
 886   serialized. Extra left bits in AndData are stripped.
 887
 888   If Address > 0x0FFFFFFF, then ASSERT().
 889   If Address is not aligned on a 32-bit boundary, then ASSERT().
 890   If StartBit is greater than 31, then ASSERT().
 891   If EndBit is greater than 31, then ASSERT().
 892   If EndBit is less than StartBit, then ASSERT().
 893
 894   @param  Address   PCI configuration register to write.
 895   @param  StartBit  The ordinal of the least significant bit in the bit field.
 896                     Range 0..31.
 897   @param  EndBit    The ordinal of the most significant bit in the bit field.
 898                     Range 0..31.
 899   @param  AndData   The value to AND with the PCI configuration register.
 900
 901   @return The value written back to the PCI configuration register.
 902
 903 **/
 904 UINT32
 905 EFIAPI
 906 PciExpressBitFieldAnd32 (
 907   IN      UINTN                     Address,
 908   IN      UINTN                     StartBit,
 909   IN      UINTN                     EndBit,
 910   IN      UINT32                    AndData
 911   );
 912
 913 /**
 914   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 915   bitwise inclusive OR, and writes the result back to the bit field in the
 916   32-bit port.
 917
 918   Reads the 32-bit PCI configuration register specified by Address, performs a
 919   bitwise AND followed by a bitwise inclusive OR between the read result and
 920   the value specified by AndData, and writes the result to the 32-bit PCI
 921   configuration register specified by Address. The value written to the PCI
 922   configuration register is returned. This function must guarantee that all PCI
 923   read and write operations are serialized. Extra left bits in both AndData and
 924   OrData are stripped.
 925
 926   If Address > 0x0FFFFFFF, then ASSERT().
 927   If Address is not aligned on a 32-bit boundary, then ASSERT().
 928   If StartBit is greater than 31, then ASSERT().
 929   If EndBit is greater than 31, then ASSERT().
 930   If EndBit is less than StartBit, then ASSERT().
 931
 932   @param  Address   PCI configuration register to write.
 933   @param  StartBit  The ordinal of the least significant bit in the bit field.
 934                     Range 0..31.
 935   @param  EndBit    The ordinal of the most significant bit in the bit field.
 936                     Range 0..31.
 937   @param  AndData   The value to AND with the PCI configuration register.
 938   @param  OrData    The value to OR with the result of the AND operation.
 939
 940   @return The value written back to the PCI configuration register.
 941
 942 **/
 943 UINT32
 944 EFIAPI
 945 PciExpressBitFieldAndThenOr32 (
 946   IN      UINTN                     Address,
 947   IN      UINTN                     StartBit,
 948   IN      UINTN                     EndBit,
 949   IN      UINT32                    AndData,
 950   IN      UINT32                    OrData
 951   );
 952
 953 /**
 954   Reads a range of PCI configuration registers into a caller supplied buffer.
 955
 956   Reads the range of PCI configuration registers specified by StartAddress and
 957   Size into the buffer specified by Buffer. This function only allows the PCI
 958   configuration registers from a single PCI function to be read. Size is
 959   returned. When possible 32-bit PCI configuration read cycles are used to read
 960   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
 961   and 16-bit PCI configuration read cycles may be used at the beginning and the
 962   end of the range.
 963
 964   If StartAddress > 0x0FFFFFFF, then ASSERT().
 965   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 966   If Size > 0 and Buffer is NULL, then ASSERT().
 967
 968   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
 969                         Function and Register.
 970   @param  Size          Size in bytes of the transfer.
 971   @param  Buffer        Pointer to a buffer receiving the data read.
 972
 973   @return Size
 974
 975 **/
 976 UINTN
 977 EFIAPI
 978 PciExpressReadBuffer (
 979   IN      UINTN                     StartAddress,
 980   IN      UINTN                     Size,
 981   OUT     VOID                      *Buffer
 982   );
 983
 984 /**
 985   Copies the data in a caller supplied buffer to a specified range of PCI
 986   configuration space.
 987
 988   Writes the range of PCI configuration registers specified by StartAddress and
 989   Size from the buffer specified by Buffer. This function only allows the PCI
 990   configuration registers from a single PCI function to be written. Size is
 991   returned. When possible 32-bit PCI configuration write cycles are used to
 992   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
 993   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
 994   and the end of the range.
 995
 996   If StartAddress > 0x0FFFFFFF, then ASSERT().
 997   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 998   If Size > 0 and Buffer is NULL, then ASSERT().
 999
1000   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1001                         Function and Register.
1002   @param  Size          Size in bytes of the transfer.
1003   @param  Buffer        Pointer to a buffer containing the data to write.
1004
1005   @return Size
1006
1007 **/
1008 UINTN
1009 EFIAPI
1010 PciExpressWriteBuffer (
1011   IN      UINTN                     StartAddress,
1012   IN      UINTN                     Size,
1013   IN      VOID                      *Buffer
1014   );
1015
1016 #endif