Import Library Class from original MDE package. Also I added the EFI_PEI_CORE_ENTRY_P...
[mirror_edk2.git] / MdePkg / Include / Library / PciExpressLib.h
1 /** @file
2 Pci Express Library Services for PCI Segment #0
3
4 Copyright (c) 2006, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 Module Name: PciExpressLib.h
14
15 **/
16
17 #ifndef __PCI_EXPRESS_LIB_H__
18 #define __PCI_EXPRESS_LIB_H__
19
20 #include <Library/PciLib.h>
21
22 /**
23 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
24 address that can be passed to the PCI Library functions.
25
26 Computes an address that is compatible with the PCI Library functions. The
27 unused upper bits of Bus, Device, Function and Register are stripped prior to
28 the generation of the address.
29
30 @param Bus PCI Bus number. Range 0..255.
31 @param Device PCI Device number. Range 0..31.
32 @param Function PCI Function number. Range 0..7.
33 @param Register PCI Register number. Range 0..4095.
34
35 @return The encode PCI address.
36
37 **/
38 #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \
39 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
40
41 /**
42 Reads an 8-bit PCI configuration register.
43
44 Reads and returns the 8-bit PCI configuration register specified by Address.
45 This function must guarantee that all PCI read and write operations are
46 serialized.
47
48 If Address > 0x0FFFFFFF, then ASSERT().
49
50 @param Address Address that encodes the PCI Bus, Device, Function and
51 Register.
52
53 @return The read value from the PCI configuration register.
54
55 **/
56 UINT8
57 EFIAPI
58 PciExpressRead8 (
59 IN UINTN Address
60 );
61
62 /**
63 Writes an 8-bit PCI configuration register.
64
65 Writes the 8-bit PCI configuration register specified by Address with the
66 value specified by Value. Value is returned. This function must guarantee
67 that all PCI read and write operations are serialized.
68
69 If Address > 0x0FFFFFFF, then ASSERT().
70
71 @param Address Address that encodes the PCI Bus, Device, Function and
72 Register.
73 @param Value The value to write.
74
75 @return The value written to the PCI configuration register.
76
77 **/
78 UINT8
79 EFIAPI
80 PciExpressWrite8 (
81 IN UINTN Address,
82 IN UINT8 Data
83 );
84
85 /**
86 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
87 an 8-bit value.
88
89 Reads the 8-bit PCI configuration register specified by Address, performs a
90 bitwise inclusive OR between the read result and the value specified by
91 OrData, and writes the result to the 8-bit PCI configuration register
92 specified by Address. The value written to the PCI configuration register is
93 returned. This function must guarantee that all PCI read and write operations
94 are serialized.
95
96 If Address > 0x0FFFFFFF, then ASSERT().
97
98 @param Address Address that encodes the PCI Bus, Device, Function and
99 Register.
100 @param OrData The value to OR with the PCI configuration register.
101
102 @return The value written back to the PCI configuration register.
103
104 **/
105 UINT8
106 EFIAPI
107 PciExpressOr8 (
108 IN UINTN Address,
109 IN UINT8 OrData
110 );
111
112 /**
113 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
114 value.
115
116 Reads the 8-bit PCI configuration register specified by Address, performs a
117 bitwise AND between the read result and the value specified by AndData, and
118 writes the result to the 8-bit PCI configuration register specified by
119 Address. The value written to the PCI configuration register is returned.
120 This function must guarantee that all PCI read and write operations are
121 serialized.
122
123 If Address > 0x0FFFFFFF, then ASSERT().
124
125 @param Address Address that encodes the PCI Bus, Device, Function and
126 Register.
127 @param AndData The value to AND with the PCI configuration register.
128
129 @return The value written back to the PCI configuration register.
130
131 **/
132 UINT8
133 EFIAPI
134 PciExpressAnd8 (
135 IN UINTN Address,
136 IN UINT8 AndData
137 );
138
139 /**
140 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
141 value, followed a bitwise inclusive OR with another 8-bit value.
142
143 Reads the 8-bit PCI configuration register specified by Address, performs a
144 bitwise AND between the read result and the value specified by AndData,
145 performs a bitwise inclusive OR between the result of the AND operation and
146 the value specified by OrData, and writes the result to the 8-bit PCI
147 configuration register specified by Address. The value written to the PCI
148 configuration register is returned. This function must guarantee that all PCI
149 read and write operations are serialized.
150
151 If Address > 0x0FFFFFFF, then ASSERT().
152
153 @param Address Address that encodes the PCI Bus, Device, Function and
154 Register.
155 @param AndData The value to AND with the PCI configuration register.
156 @param OrData The value to OR with the result of the AND operation.
157
158 @return The value written back to the PCI configuration register.
159
160 **/
161 UINT8
162 EFIAPI
163 PciExpressAndThenOr8 (
164 IN UINTN Address,
165 IN UINT8 AndData,
166 IN UINT8 OrData
167 );
168
169 /**
170 Reads a bit field of a PCI configuration register.
171
172 Reads the bit field in an 8-bit PCI configuration register. The bit field is
173 specified by the StartBit and the EndBit. The value of the bit field is
174 returned.
175
176 If Address > 0x0FFFFFFF, then ASSERT().
177 If StartBit is greater than 7, then ASSERT().
178 If EndBit is greater than 7, then ASSERT().
179 If EndBit is less than StartBit, then ASSERT().
180
181 @param Address PCI configuration register to read.
182 @param StartBit The ordinal of the least significant bit in the bit field.
183 Range 0..7.
184 @param EndBit The ordinal of the most significant bit in the bit field.
185 Range 0..7.
186
187 @return The value of the bit field read from the PCI configuration register.
188
189 **/
190 UINT8
191 EFIAPI
192 PciExpressBitFieldRead8 (
193 IN UINTN Address,
194 IN UINTN StartBit,
195 IN UINTN EndBit
196 );
197
198 /**
199 Writes a bit field to a PCI configuration register.
200
201 Writes Value to the bit field of the PCI configuration register. The bit
202 field is specified by the StartBit and the EndBit. All other bits in the
203 destination PCI configuration register are preserved. The new value of the
204 8-bit register is returned.
205
206 If Address > 0x0FFFFFFF, then ASSERT().
207 If StartBit is greater than 7, then ASSERT().
208 If EndBit is greater than 7, then ASSERT().
209 If EndBit is less than StartBit, then ASSERT().
210
211 @param Address PCI configuration register to write.
212 @param StartBit The ordinal of the least significant bit in the bit field.
213 Range 0..7.
214 @param EndBit The ordinal of the most significant bit in the bit field.
215 Range 0..7.
216 @param Value New value of the bit field.
217
218 @return The value written back to the PCI configuration register.
219
220 **/
221 UINT8
222 EFIAPI
223 PciExpressBitFieldWrite8 (
224 IN UINTN Address,
225 IN UINTN StartBit,
226 IN UINTN EndBit,
227 IN UINT8 Value
228 );
229
230 /**
231 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
232 writes the result back to the bit field in the 8-bit port.
233
234 Reads the 8-bit PCI configuration register specified by Address, performs a
235 bitwise inclusive OR between the read result and the value specified by
236 OrData, and writes the result to the 8-bit PCI configuration register
237 specified by Address. The value written to the PCI configuration register is
238 returned. This function must guarantee that all PCI read and write operations
239 are serialized. Extra left bits in OrData are stripped.
240
241 If Address > 0x0FFFFFFF, then ASSERT().
242 If StartBit is greater than 7, then ASSERT().
243 If EndBit is greater than 7, then ASSERT().
244 If EndBit is less than StartBit, then ASSERT().
245
246 @param Address PCI configuration register to write.
247 @param StartBit The ordinal of the least significant bit in the bit field.
248 Range 0..7.
249 @param EndBit The ordinal of the most significant bit in the bit field.
250 Range 0..7.
251 @param OrData The value to OR with the PCI configuration register.
252
253 @return The value written back to the PCI configuration register.
254
255 **/
256 UINT8
257 EFIAPI
258 PciExpressBitFieldOr8 (
259 IN UINTN Address,
260 IN UINTN StartBit,
261 IN UINTN EndBit,
262 IN UINT8 OrData
263 );
264
265 /**
266 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
267 AND, and writes the result back to the bit field in the 8-bit register.
268
269 Reads the 8-bit PCI configuration register specified by Address, performs a
270 bitwise AND between the read result and the value specified by AndData, and
271 writes the result to the 8-bit PCI configuration register specified by
272 Address. The value written to the PCI configuration register is returned.
273 This function must guarantee that all PCI read and write operations are
274 serialized. Extra left bits in AndData are stripped.
275
276 If Address > 0x0FFFFFFF, then ASSERT().
277 If StartBit is greater than 7, then ASSERT().
278 If EndBit is greater than 7, then ASSERT().
279 If EndBit is less than StartBit, then ASSERT().
280
281 @param Address PCI configuration register to write.
282 @param StartBit The ordinal of the least significant bit in the bit field.
283 Range 0..7.
284 @param EndBit The ordinal of the most significant bit in the bit field.
285 Range 0..7.
286 @param AndData The value to AND with the PCI configuration register.
287
288 @return The value written back to the PCI configuration register.
289
290 **/
291 UINT8
292 EFIAPI
293 PciExpressBitFieldAnd8 (
294 IN UINTN Address,
295 IN UINTN StartBit,
296 IN UINTN EndBit,
297 IN UINT8 AndData
298 );
299
300 /**
301 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
302 bitwise inclusive OR, and writes the result back to the bit field in the
303 8-bit port.
304
305 Reads the 8-bit PCI configuration register specified by Address, performs a
306 bitwise AND followed by a bitwise inclusive OR between the read result and
307 the value specified by AndData, and writes the result to the 8-bit PCI
308 configuration register specified by Address. The value written to the PCI
309 configuration register is returned. This function must guarantee that all PCI
310 read and write operations are serialized. Extra left bits in both AndData and
311 OrData are stripped.
312
313 If Address > 0x0FFFFFFF, then ASSERT().
314 If StartBit is greater than 7, then ASSERT().
315 If EndBit is greater than 7, then ASSERT().
316 If EndBit is less than StartBit, then ASSERT().
317
318 @param Address PCI configuration register to write.
319 @param StartBit The ordinal of the least significant bit in the bit field.
320 Range 0..7.
321 @param EndBit The ordinal of the most significant bit in the bit field.
322 Range 0..7.
323 @param AndData The value to AND with the PCI configuration register.
324 @param OrData The value to OR with the result of the AND operation.
325
326 @return The value written back to the PCI configuration register.
327
328 **/
329 UINT8
330 EFIAPI
331 PciExpressBitFieldAndThenOr8 (
332 IN UINTN Address,
333 IN UINTN StartBit,
334 IN UINTN EndBit,
335 IN UINT8 AndData,
336 IN UINT8 OrData
337 );
338
339 /**
340 Reads a 16-bit PCI configuration register.
341
342 Reads and returns the 16-bit PCI configuration register specified by Address.
343 This function must guarantee that all PCI read and write operations are
344 serialized.
345
346 If Address > 0x0FFFFFFF, then ASSERT().
347 If Address is not aligned on a 16-bit boundary, then ASSERT().
348
349 @param Address Address that encodes the PCI Bus, Device, Function and
350 Register.
351
352 @return The read value from the PCI configuration register.
353
354 **/
355 UINT16
356 EFIAPI
357 PciExpressRead16 (
358 IN UINTN Address
359 );
360
361 /**
362 Writes a 16-bit PCI configuration register.
363
364 Writes the 16-bit PCI configuration register specified by Address with the
365 value specified by Value. Value is returned. This function must guarantee
366 that all PCI read and write operations are serialized.
367
368 If Address > 0x0FFFFFFF, then ASSERT().
369 If Address is not aligned on a 16-bit boundary, then ASSERT().
370
371 @param Address Address that encodes the PCI Bus, Device, Function and
372 Register.
373 @param Value The value to write.
374
375 @return The value written to the PCI configuration register.
376
377 **/
378 UINT16
379 EFIAPI
380 PciExpressWrite16 (
381 IN UINTN Address,
382 IN UINT16 Data
383 );
384
385 /**
386 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
387 a 16-bit value.
388
389 Reads the 16-bit PCI configuration register specified by Address, performs a
390 bitwise inclusive OR between the read result and the value specified by
391 OrData, and writes the result to the 16-bit PCI configuration register
392 specified by Address. The value written to the PCI configuration register is
393 returned. This function must guarantee that all PCI read and write operations
394 are serialized.
395
396 If Address > 0x0FFFFFFF, then ASSERT().
397 If Address is not aligned on a 16-bit boundary, then ASSERT().
398
399 @param Address Address that encodes the PCI Bus, Device, Function and
400 Register.
401 @param OrData The value to OR with the PCI configuration register.
402
403 @return The value written back to the PCI configuration register.
404
405 **/
406 UINT16
407 EFIAPI
408 PciExpressOr16 (
409 IN UINTN Address,
410 IN UINT16 OrData
411 );
412
413 /**
414 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
415 value.
416
417 Reads the 16-bit PCI configuration register specified by Address, performs a
418 bitwise AND between the read result and the value specified by AndData, and
419 writes the result to the 16-bit PCI configuration register specified by
420 Address. The value written to the PCI configuration register is returned.
421 This function must guarantee that all PCI read and write operations are
422 serialized.
423
424 If Address > 0x0FFFFFFF, then ASSERT().
425 If Address is not aligned on a 16-bit boundary, then ASSERT().
426
427 @param Address Address that encodes the PCI Bus, Device, Function and
428 Register.
429 @param AndData The value to AND with the PCI configuration register.
430
431 @return The value written back to the PCI configuration register.
432
433 **/
434 UINT16
435 EFIAPI
436 PciExpressAnd16 (
437 IN UINTN Address,
438 IN UINT16 AndData
439 );
440
441 /**
442 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
443 value, followed a bitwise inclusive OR with another 16-bit value.
444
445 Reads the 16-bit PCI configuration register specified by Address, performs a
446 bitwise AND between the read result and the value specified by AndData,
447 performs a bitwise inclusive OR between the result of the AND operation and
448 the value specified by OrData, and writes the result to the 16-bit PCI
449 configuration register specified by Address. The value written to the PCI
450 configuration register is returned. This function must guarantee that all PCI
451 read and write operations are serialized.
452
453 If Address > 0x0FFFFFFF, then ASSERT().
454 If Address is not aligned on a 16-bit boundary, then ASSERT().
455
456 @param Address Address that encodes the PCI Bus, Device, Function and
457 Register.
458 @param AndData The value to AND with the PCI configuration register.
459 @param OrData The value to OR with the result of the AND operation.
460
461 @return The value written back to the PCI configuration register.
462
463 **/
464 UINT16
465 EFIAPI
466 PciExpressAndThenOr16 (
467 IN UINTN Address,
468 IN UINT16 AndData,
469 IN UINT16 OrData
470 );
471
472 /**
473 Reads a bit field of a PCI configuration register.
474
475 Reads the bit field in a 16-bit PCI configuration register. The bit field is
476 specified by the StartBit and the EndBit. The value of the bit field is
477 returned.
478
479 If Address > 0x0FFFFFFF, then ASSERT().
480 If Address is not aligned on a 16-bit boundary, then ASSERT().
481 If StartBit is greater than 15, then ASSERT().
482 If EndBit is greater than 15, then ASSERT().
483 If EndBit is less than StartBit, then ASSERT().
484
485 @param Address PCI configuration register to read.
486 @param StartBit The ordinal of the least significant bit in the bit field.
487 Range 0..15.
488 @param EndBit The ordinal of the most significant bit in the bit field.
489 Range 0..15.
490
491 @return The value of the bit field read from the PCI configuration register.
492
493 **/
494 UINT16
495 EFIAPI
496 PciExpressBitFieldRead16 (
497 IN UINTN Address,
498 IN UINTN StartBit,
499 IN UINTN EndBit
500 );
501
502 /**
503 Writes a bit field to a PCI configuration register.
504
505 Writes Value to the bit field of the PCI configuration register. The bit
506 field is specified by the StartBit and the EndBit. All other bits in the
507 destination PCI configuration register are preserved. The new value of the
508 16-bit register is returned.
509
510 If Address > 0x0FFFFFFF, then ASSERT().
511 If Address is not aligned on a 16-bit boundary, then ASSERT().
512 If StartBit is greater than 15, then ASSERT().
513 If EndBit is greater than 15, then ASSERT().
514 If EndBit is less than StartBit, then ASSERT().
515
516 @param Address PCI configuration register to write.
517 @param StartBit The ordinal of the least significant bit in the bit field.
518 Range 0..15.
519 @param EndBit The ordinal of the most significant bit in the bit field.
520 Range 0..15.
521 @param Value New value of the bit field.
522
523 @return The value written back to the PCI configuration register.
524
525 **/
526 UINT16
527 EFIAPI
528 PciExpressBitFieldWrite16 (
529 IN UINTN Address,
530 IN UINTN StartBit,
531 IN UINTN EndBit,
532 IN UINT16 Value
533 );
534
535 /**
536 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
537 writes the result back to the bit field in the 16-bit port.
538
539 Reads the 16-bit PCI configuration register specified by Address, performs a
540 bitwise inclusive OR between the read result and the value specified by
541 OrData, and writes the result to the 16-bit PCI configuration register
542 specified by Address. The value written to the PCI configuration register is
543 returned. This function must guarantee that all PCI read and write operations
544 are serialized. Extra left bits in OrData are stripped.
545
546 If Address > 0x0FFFFFFF, then ASSERT().
547 If Address is not aligned on a 16-bit boundary, then ASSERT().
548 If StartBit is greater than 15, then ASSERT().
549 If EndBit is greater than 15, then ASSERT().
550 If EndBit is less than StartBit, then ASSERT().
551
552 @param Address PCI configuration register to write.
553 @param StartBit The ordinal of the least significant bit in the bit field.
554 Range 0..15.
555 @param EndBit The ordinal of the most significant bit in the bit field.
556 Range 0..15.
557 @param OrData The value to OR with the PCI configuration register.
558
559 @return The value written back to the PCI configuration register.
560
561 **/
562 UINT16
563 EFIAPI
564 PciExpressBitFieldOr16 (
565 IN UINTN Address,
566 IN UINTN StartBit,
567 IN UINTN EndBit,
568 IN UINT16 OrData
569 );
570
571 /**
572 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
573 AND, and writes the result back to the bit field in the 16-bit register.
574
575 Reads the 16-bit PCI configuration register specified by Address, performs a
576 bitwise AND between the read result and the value specified by AndData, and
577 writes the result to the 16-bit PCI configuration register specified by
578 Address. The value written to the PCI configuration register is returned.
579 This function must guarantee that all PCI read and write operations are
580 serialized. Extra left bits in AndData are stripped.
581
582 If Address > 0x0FFFFFFF, then ASSERT().
583 If Address is not aligned on a 16-bit boundary, then ASSERT().
584 If StartBit is greater than 15, then ASSERT().
585 If EndBit is greater than 15, then ASSERT().
586 If EndBit is less than StartBit, then ASSERT().
587
588 @param Address PCI configuration register to write.
589 @param StartBit The ordinal of the least significant bit in the bit field.
590 Range 0..15.
591 @param EndBit The ordinal of the most significant bit in the bit field.
592 Range 0..15.
593 @param AndData The value to AND with the PCI configuration register.
594
595 @return The value written back to the PCI configuration register.
596
597 **/
598 UINT16
599 EFIAPI
600 PciExpressBitFieldAnd16 (
601 IN UINTN Address,
602 IN UINTN StartBit,
603 IN UINTN EndBit,
604 IN UINT16 AndData
605 );
606
607 /**
608 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
609 bitwise inclusive OR, and writes the result back to the bit field in the
610 16-bit port.
611
612 Reads the 16-bit PCI configuration register specified by Address, performs a
613 bitwise AND followed by a bitwise inclusive OR between the read result and
614 the value specified by AndData, and writes the result to the 16-bit PCI
615 configuration register specified by Address. The value written to the PCI
616 configuration register is returned. This function must guarantee that all PCI
617 read and write operations are serialized. Extra left bits in both AndData and
618 OrData are stripped.
619
620 If Address > 0x0FFFFFFF, then ASSERT().
621 If Address is not aligned on a 16-bit boundary, then ASSERT().
622 If StartBit is greater than 15, then ASSERT().
623 If EndBit is greater than 15, then ASSERT().
624 If EndBit is less than StartBit, then ASSERT().
625
626 @param Address PCI configuration register to write.
627 @param StartBit The ordinal of the least significant bit in the bit field.
628 Range 0..15.
629 @param EndBit The ordinal of the most significant bit in the bit field.
630 Range 0..15.
631 @param AndData The value to AND with the PCI configuration register.
632 @param OrData The value to OR with the result of the AND operation.
633
634 @return The value written back to the PCI configuration register.
635
636 **/
637 UINT16
638 EFIAPI
639 PciExpressBitFieldAndThenOr16 (
640 IN UINTN Address,
641 IN UINTN StartBit,
642 IN UINTN EndBit,
643 IN UINT16 AndData,
644 IN UINT16 OrData
645 );
646
647 /**
648 Reads a 32-bit PCI configuration register.
649
650 Reads and returns the 32-bit PCI configuration register specified by Address.
651 This function must guarantee that all PCI read and write operations are
652 serialized.
653
654 If Address > 0x0FFFFFFF, then ASSERT().
655 If Address is not aligned on a 32-bit boundary, then ASSERT().
656
657 @param Address Address that encodes the PCI Bus, Device, Function and
658 Register.
659
660 @return The read value from the PCI configuration register.
661
662 **/
663 UINT32
664 EFIAPI
665 PciExpressRead32 (
666 IN UINTN Address
667 );
668
669 /**
670 Writes a 32-bit PCI configuration register.
671
672 Writes the 32-bit PCI configuration register specified by Address with the
673 value specified by Value. Value is returned. This function must guarantee
674 that all PCI read and write operations are serialized.
675
676 If Address > 0x0FFFFFFF, then ASSERT().
677 If Address is not aligned on a 32-bit boundary, then ASSERT().
678
679 @param Address Address that encodes the PCI Bus, Device, Function and
680 Register.
681 @param Value The value to write.
682
683 @return The value written to the PCI configuration register.
684
685 **/
686 UINT32
687 EFIAPI
688 PciExpressWrite32 (
689 IN UINTN Address,
690 IN UINT32 Data
691 );
692
693 /**
694 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
695 a 32-bit value.
696
697 Reads the 32-bit PCI configuration register specified by Address, performs a
698 bitwise inclusive OR between the read result and the value specified by
699 OrData, and writes the result to the 32-bit PCI configuration register
700 specified by Address. The value written to the PCI configuration register is
701 returned. This function must guarantee that all PCI read and write operations
702 are serialized.
703
704 If Address > 0x0FFFFFFF, then ASSERT().
705 If Address is not aligned on a 32-bit boundary, then ASSERT().
706
707 @param Address Address that encodes the PCI Bus, Device, Function and
708 Register.
709 @param OrData The value to OR with the PCI configuration register.
710
711 @return The value written back to the PCI configuration register.
712
713 **/
714 UINT32
715 EFIAPI
716 PciExpressOr32 (
717 IN UINTN Address,
718 IN UINT32 OrData
719 );
720
721 /**
722 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
723 value.
724
725 Reads the 32-bit PCI configuration register specified by Address, performs a
726 bitwise AND between the read result and the value specified by AndData, and
727 writes the result to the 32-bit PCI configuration register specified by
728 Address. The value written to the PCI configuration register is returned.
729 This function must guarantee that all PCI read and write operations are
730 serialized.
731
732 If Address > 0x0FFFFFFF, then ASSERT().
733 If Address is not aligned on a 32-bit boundary, then ASSERT().
734
735 @param Address Address that encodes the PCI Bus, Device, Function and
736 Register.
737 @param AndData The value to AND with the PCI configuration register.
738
739 @return The value written back to the PCI configuration register.
740
741 **/
742 UINT32
743 EFIAPI
744 PciExpressAnd32 (
745 IN UINTN Address,
746 IN UINT32 AndData
747 );
748
749 /**
750 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
751 value, followed a bitwise inclusive OR with another 32-bit value.
752
753 Reads the 32-bit PCI configuration register specified by Address, performs a
754 bitwise AND between the read result and the value specified by AndData,
755 performs a bitwise inclusive OR between the result of the AND operation and
756 the value specified by OrData, and writes the result to the 32-bit PCI
757 configuration register specified by Address. The value written to the PCI
758 configuration register is returned. This function must guarantee that all PCI
759 read and write operations are serialized.
760
761 If Address > 0x0FFFFFFF, then ASSERT().
762 If Address is not aligned on a 32-bit boundary, then ASSERT().
763
764 @param Address Address that encodes the PCI Bus, Device, Function and
765 Register.
766 @param AndData The value to AND with the PCI configuration register.
767 @param OrData The value to OR with the result of the AND operation.
768
769 @return The value written back to the PCI configuration register.
770
771 **/
772 UINT32
773 EFIAPI
774 PciExpressAndThenOr32 (
775 IN UINTN Address,
776 IN UINT32 AndData,
777 IN UINT32 OrData
778 );
779
780 /**
781 Reads a bit field of a PCI configuration register.
782
783 Reads the bit field in a 32-bit PCI configuration register. The bit field is
784 specified by the StartBit and the EndBit. The value of the bit field is
785 returned.
786
787 If Address > 0x0FFFFFFF, then ASSERT().
788 If Address is not aligned on a 32-bit boundary, then ASSERT().
789 If StartBit is greater than 31, then ASSERT().
790 If EndBit is greater than 31, then ASSERT().
791 If EndBit is less than StartBit, then ASSERT().
792
793 @param Address PCI configuration register to read.
794 @param StartBit The ordinal of the least significant bit in the bit field.
795 Range 0..31.
796 @param EndBit The ordinal of the most significant bit in the bit field.
797 Range 0..31.
798
799 @return The value of the bit field read from the PCI configuration register.
800
801 **/
802 UINT32
803 EFIAPI
804 PciExpressBitFieldRead32 (
805 IN UINTN Address,
806 IN UINTN StartBit,
807 IN UINTN EndBit
808 );
809
810 /**
811 Writes a bit field to a PCI configuration register.
812
813 Writes Value to the bit field of the PCI configuration register. The bit
814 field is specified by the StartBit and the EndBit. All other bits in the
815 destination PCI configuration register are preserved. The new value of the
816 32-bit register is returned.
817
818 If Address > 0x0FFFFFFF, then ASSERT().
819 If Address is not aligned on a 32-bit boundary, then ASSERT().
820 If StartBit is greater than 31, then ASSERT().
821 If EndBit is greater than 31, then ASSERT().
822 If EndBit is less than StartBit, then ASSERT().
823
824 @param Address PCI configuration register to write.
825 @param StartBit The ordinal of the least significant bit in the bit field.
826 Range 0..31.
827 @param EndBit The ordinal of the most significant bit in the bit field.
828 Range 0..31.
829 @param Value New value of the bit field.
830
831 @return The value written back to the PCI configuration register.
832
833 **/
834 UINT32
835 EFIAPI
836 PciExpressBitFieldWrite32 (
837 IN UINTN Address,
838 IN UINTN StartBit,
839 IN UINTN EndBit,
840 IN UINT32 Value
841 );
842
843 /**
844 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
845 writes the result back to the bit field in the 32-bit port.
846
847 Reads the 32-bit PCI configuration register specified by Address, performs a
848 bitwise inclusive OR between the read result and the value specified by
849 OrData, and writes the result to the 32-bit PCI configuration register
850 specified by Address. The value written to the PCI configuration register is
851 returned. This function must guarantee that all PCI read and write operations
852 are serialized. Extra left bits in OrData are stripped.
853
854 If Address > 0x0FFFFFFF, then ASSERT().
855 If Address is not aligned on a 32-bit boundary, then ASSERT().
856 If StartBit is greater than 31, then ASSERT().
857 If EndBit is greater than 31, then ASSERT().
858 If EndBit is less than StartBit, then ASSERT().
859
860 @param Address PCI configuration register to write.
861 @param StartBit The ordinal of the least significant bit in the bit field.
862 Range 0..31.
863 @param EndBit The ordinal of the most significant bit in the bit field.
864 Range 0..31.
865 @param OrData The value to OR with the PCI configuration register.
866
867 @return The value written back to the PCI configuration register.
868
869 **/
870 UINT32
871 EFIAPI
872 PciExpressBitFieldOr32 (
873 IN UINTN Address,
874 IN UINTN StartBit,
875 IN UINTN EndBit,
876 IN UINT32 OrData
877 );
878
879 /**
880 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
881 AND, and writes the result back to the bit field in the 32-bit register.
882
883 Reads the 32-bit PCI configuration register specified by Address, performs a
884 bitwise AND between the read result and the value specified by AndData, and
885 writes the result to the 32-bit PCI configuration register specified by
886 Address. The value written to the PCI configuration register is returned.
887 This function must guarantee that all PCI read and write operations are
888 serialized. Extra left bits in AndData are stripped.
889
890 If Address > 0x0FFFFFFF, then ASSERT().
891 If Address is not aligned on a 32-bit boundary, then ASSERT().
892 If StartBit is greater than 31, then ASSERT().
893 If EndBit is greater than 31, then ASSERT().
894 If EndBit is less than StartBit, then ASSERT().
895
896 @param Address PCI configuration register to write.
897 @param StartBit The ordinal of the least significant bit in the bit field.
898 Range 0..31.
899 @param EndBit The ordinal of the most significant bit in the bit field.
900 Range 0..31.
901 @param AndData The value to AND with the PCI configuration register.
902
903 @return The value written back to the PCI configuration register.
904
905 **/
906 UINT32
907 EFIAPI
908 PciExpressBitFieldAnd32 (
909 IN UINTN Address,
910 IN UINTN StartBit,
911 IN UINTN EndBit,
912 IN UINT32 AndData
913 );
914
915 /**
916 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
917 bitwise inclusive OR, and writes the result back to the bit field in the
918 32-bit port.
919
920 Reads the 32-bit PCI configuration register specified by Address, performs a
921 bitwise AND followed by a bitwise inclusive OR between the read result and
922 the value specified by AndData, and writes the result to the 32-bit PCI
923 configuration register specified by Address. The value written to the PCI
924 configuration register is returned. This function must guarantee that all PCI
925 read and write operations are serialized. Extra left bits in both AndData and
926 OrData are stripped.
927
928 If Address > 0x0FFFFFFF, then ASSERT().
929 If Address is not aligned on a 32-bit boundary, then ASSERT().
930 If StartBit is greater than 31, then ASSERT().
931 If EndBit is greater than 31, then ASSERT().
932 If EndBit is less than StartBit, then ASSERT().
933
934 @param Address PCI configuration register to write.
935 @param StartBit The ordinal of the least significant bit in the bit field.
936 Range 0..31.
937 @param EndBit The ordinal of the most significant bit in the bit field.
938 Range 0..31.
939 @param AndData The value to AND with the PCI configuration register.
940 @param OrData The value to OR with the result of the AND operation.
941
942 @return The value written back to the PCI configuration register.
943
944 **/
945 UINT32
946 EFIAPI
947 PciExpressBitFieldAndThenOr32 (
948 IN UINTN Address,
949 IN UINTN StartBit,
950 IN UINTN EndBit,
951 IN UINT32 AndData,
952 IN UINT32 OrData
953 );
954
955 /**
956 Reads a range of PCI configuration registers into a caller supplied buffer.
957
958 Reads the range of PCI configuration registers specified by StartAddress and
959 Size into the buffer specified by Buffer. This function only allows the PCI
960 configuration registers from a single PCI function to be read. Size is
961 returned. When possible 32-bit PCI configuration read cycles are used to read
962 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
963 and 16-bit PCI configuration read cycles may be used at the beginning and the
964 end of the range.
965
966 If StartAddress > 0x0FFFFFFF, then ASSERT().
967 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
968 If Size > 0 and Buffer is NULL, then ASSERT().
969
970 @param StartAddress Starting address that encodes the PCI Bus, Device,
971 Function and Register.
972 @param Size Size in bytes of the transfer.
973 @param Buffer Pointer to a buffer receiving the data read.
974
975 @return Size
976
977 **/
978 UINTN
979 EFIAPI
980 PciExpressReadBuffer (
981 IN UINTN StartAddress,
982 IN UINTN Size,
983 OUT VOID *Buffer
984 );
985
986 /**
987 Copies the data in a caller supplied buffer to a specified range of PCI
988 configuration space.
989
990 Writes the range of PCI configuration registers specified by StartAddress and
991 Size from the buffer specified by Buffer. This function only allows the PCI
992 configuration registers from a single PCI function to be written. Size is
993 returned. When possible 32-bit PCI configuration write cycles are used to
994 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
995 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
996 and the end of the range.
997
998 If StartAddress > 0x0FFFFFFF, then ASSERT().
999 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1000 If Size > 0 and Buffer is NULL, then ASSERT().
1001
1002 @param StartAddress Starting address that encodes the PCI Bus, Device,
1003 Function and Register.
1004 @param Size Size in bytes of the transfer.
1005 @param Buffer Pointer to a buffer containing the data to write.
1006
1007 @return Size
1008
1009 **/
1010 UINTN
1011 EFIAPI
1012 PciExpressWriteBuffer (
1013 IN UINTN StartAddress,
1014 IN UINTN Size,
1015 IN VOID *Buffer
1016 );
1017
1018 #endif