MdePkg/Include/Library/PciExpressLib.h

   1 /** @file
   2   Provides services to access PCI Configuration Space using the MMIO PCI Express window.
   3
   4   This library is identical to the PCI Library, except the access method for performing PCI
   5   configuration cycles must be through the 256 MB PCI Express MMIO window whose base address
   6   is defined by PcdPciExpressBaseAddress.
   7
   8 Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
   9 This program and the accompanying materials
  10 are licensed and made available under the terms and conditions of the BSD License
  11 which accompanies this distribution.  The full text of the license may be found at
  12 http://opensource.org/licenses/bsd-license.php
  13
  14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  16
  17 **/
  18
  19 #ifndef __PCI_EXPRESS_LIB_H__
  20 #define __PCI_EXPRESS_LIB_H__
  21
  22 /**
  23   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  24   address that can be passed to the PCI Library functions.
  25
  26   Computes an address that is compatible with the PCI Library functions. The
  27   unused upper bits of Bus, Device, Function and Register are stripped prior to
  28   the generation of the address.
  29
  30   @param  Bus       PCI Bus number. Range 0..255.
  31   @param  Device    PCI Device number. Range 0..31.
  32   @param  Function  PCI Function number. Range 0..7.
  33   @param  Register  PCI Register number. Range 0..4095.
  34
  35   @return The encode PCI address.
  36
  37 **/
  38 #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) PCI_ECAM_ADDRESS ((Bus), (Device), (Function), (Offset))
  39
  40 /**
  41   Registers a PCI device so PCI configuration registers may be accessed after
  42   SetVirtualAddressMap().
  43
  44   Registers the PCI device specified by Address so all the PCI configuration
  45   registers associated with that PCI device may be accessed after SetVirtualAddressMap()
  46   is called.
  47
  48   If Address > 0x0FFFFFFF, then ASSERT().
  49
  50   @param  Address Address that encodes the PCI Bus, Device, Function and
  51                   Register.
  52
  53   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
  54   @retval RETURN_UNSUPPORTED       An attempt was made to call this function
  55                                    after ExitBootServices().
  56   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
  57                                    at runtime could not be mapped.
  58   @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to
  59                                    complete the registration.
  60
  61 **/
  62 RETURN_STATUS
  63 EFIAPI
  64 PciExpressRegisterForRuntimeAccess (
  65   IN UINTN  Address
  66   );
  67
  68 /**
  69   Reads an 8-bit PCI configuration register.
  70
  71   Reads and returns the 8-bit PCI configuration register specified by Address.
  72   This function must guarantee that all PCI read and write operations are
  73   serialized.
  74
  75   If Address > 0x0FFFFFFF, then ASSERT().
  76
  77   @param  Address Address that encodes the PCI Bus, Device, Function and
  78                   Register.
  79
  80   @return The read value from the PCI configuration register.
  81
  82 **/
  83 UINT8
  84 EFIAPI
  85 PciExpressRead8 (
  86   IN      UINTN                     Address
  87   );
  88
  89 /**
  90   Writes an 8-bit PCI configuration register.
  91
  92   Writes the 8-bit PCI configuration register specified by Address with the
  93   value specified by Value. Value is returned. This function must guarantee
  94   that all PCI read and write operations are serialized.
  95
  96   If Address > 0x0FFFFFFF, then ASSERT().
  97
  98   @param  Address Address that encodes the PCI Bus, Device, Function and
  99                   Register.
 100   @param  Value   The value to write.
 101
 102   @return The value written to the PCI configuration register.
 103
 104 **/
 105 UINT8
 106 EFIAPI
 107 PciExpressWrite8 (
 108   IN      UINTN                     Address,
 109   IN      UINT8                     Value
 110   );
 111
 112 /**
 113   Performs a bitwise OR of an 8-bit PCI configuration register with
 114   an 8-bit value.
 115
 116   Reads the 8-bit PCI configuration register specified by Address, performs a
 117   bitwise OR between the read result and the value specified by
 118   OrData, and writes the result to the 8-bit PCI configuration register
 119   specified by Address. The value written to the PCI configuration register is
 120   returned. This function must guarantee that all PCI read and write operations
 121   are serialized.
 122
 123   If Address > 0x0FFFFFFF, then ASSERT().
 124
 125   @param  Address Address that encodes the PCI Bus, Device, Function and
 126                   Register.
 127   @param  OrData  The value to OR with the PCI configuration register.
 128
 129   @return The value written back to the PCI configuration register.
 130
 131 **/
 132 UINT8
 133 EFIAPI
 134 PciExpressOr8 (
 135   IN      UINTN                     Address,
 136   IN      UINT8                     OrData
 137   );
 138
 139 /**
 140   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 141   value.
 142
 143   Reads the 8-bit PCI configuration register specified by Address, performs a
 144   bitwise AND between the read result and the value specified by AndData, and
 145   writes the result to the 8-bit PCI configuration register specified by
 146   Address. The value written to the PCI configuration register is returned.
 147   This function must guarantee that all PCI read and write operations are
 148   serialized.
 149
 150   If Address > 0x0FFFFFFF, then ASSERT().
 151
 152   @param  Address Address that encodes the PCI Bus, Device, Function and
 153                   Register.
 154   @param  AndData The value to AND with the PCI configuration register.
 155
 156   @return The value written back to the PCI configuration register.
 157
 158 **/
 159 UINT8
 160 EFIAPI
 161 PciExpressAnd8 (
 162   IN      UINTN                     Address,
 163   IN      UINT8                     AndData
 164   );
 165
 166 /**
 167   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 168   value, followed a  bitwise OR with another 8-bit value.
 169
 170   Reads the 8-bit PCI configuration register specified by Address, performs a
 171   bitwise AND between the read result and the value specified by AndData,
 172   performs a bitwise OR between the result of the AND operation and
 173   the value specified by OrData, and writes the result to the 8-bit PCI
 174   configuration register specified by Address. The value written to the PCI
 175   configuration register is returned. This function must guarantee that all PCI
 176   read and write operations are serialized.
 177
 178   If Address > 0x0FFFFFFF, then ASSERT().
 179
 180   @param  Address Address that encodes the PCI Bus, Device, Function and
 181                   Register.
 182   @param  AndData The value to AND with the PCI configuration register.
 183   @param  OrData  The value to OR with the result of the AND operation.
 184
 185   @return The value written back to the PCI configuration register.
 186
 187 **/
 188 UINT8
 189 EFIAPI
 190 PciExpressAndThenOr8 (
 191   IN      UINTN                     Address,
 192   IN      UINT8                     AndData,
 193   IN      UINT8                     OrData
 194   );
 195
 196 /**
 197   Reads a bit field of a PCI configuration register.
 198
 199   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 200   specified by the StartBit and the EndBit. The value of the bit field is
 201   returned.
 202
 203   If Address > 0x0FFFFFFF, then ASSERT().
 204   If StartBit is greater than 7, then ASSERT().
 205   If EndBit is greater than 7, then ASSERT().
 206   If EndBit is less than StartBit, then ASSERT().
 207
 208   @param  Address   PCI configuration register to read.
 209   @param  StartBit  The ordinal of the least significant bit in the bit field.
 210                     Range 0..7.
 211   @param  EndBit    The ordinal of the most significant bit in the bit field.
 212                     Range 0..7.
 213
 214   @return The value of the bit field read from the PCI configuration register.
 215
 216 **/
 217 UINT8
 218 EFIAPI
 219 PciExpressBitFieldRead8 (
 220   IN      UINTN                     Address,
 221   IN      UINTN                     StartBit,
 222   IN      UINTN                     EndBit
 223   );
 224
 225 /**
 226   Writes a bit field to a PCI configuration register.
 227
 228   Writes Value to the bit field of the PCI configuration register. The bit
 229   field is specified by the StartBit and the EndBit. All other bits in the
 230   destination PCI configuration register are preserved. The new value of the
 231   8-bit register is returned.
 232
 233   If Address > 0x0FFFFFFF, then ASSERT().
 234   If StartBit is greater than 7, then ASSERT().
 235   If EndBit is greater than 7, then ASSERT().
 236   If EndBit is less than StartBit, then ASSERT().
 237   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 238
 239   @param  Address   PCI configuration register to write.
 240   @param  StartBit  The ordinal of the least significant bit in the bit field.
 241                     Range 0..7.
 242   @param  EndBit    The ordinal of the most significant bit in the bit field.
 243                     Range 0..7.
 244   @param  Value     New value of the bit field.
 245
 246   @return The value written back to the PCI configuration register.
 247
 248 **/
 249 UINT8
 250 EFIAPI
 251 PciExpressBitFieldWrite8 (
 252   IN      UINTN                     Address,
 253   IN      UINTN                     StartBit,
 254   IN      UINTN                     EndBit,
 255   IN      UINT8                     Value
 256   );
 257
 258 /**
 259   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 260   writes the result back to the bit field in the 8-bit port.
 261
 262   Reads the 8-bit PCI configuration register specified by Address, performs a
 263   bitwise OR between the read result and the value specified by
 264   OrData, and writes the result to the 8-bit PCI configuration register
 265   specified by Address. The value written to the PCI configuration register is
 266   returned. This function must guarantee that all PCI read and write operations
 267   are serialized. Extra left bits in OrData are stripped.
 268
 269   If Address > 0x0FFFFFFF, then ASSERT().
 270   If StartBit is greater than 7, then ASSERT().
 271   If EndBit is greater than 7, then ASSERT().
 272   If EndBit is less than StartBit, then ASSERT().
 273   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 274
 275   @param  Address   PCI configuration register to write.
 276   @param  StartBit  The ordinal of the least significant bit in the bit field.
 277                     Range 0..7.
 278   @param  EndBit    The ordinal of the most significant bit in the bit field.
 279                     Range 0..7.
 280   @param  OrData    The value to OR with the PCI configuration register.
 281
 282   @return The value written back to the PCI configuration register.
 283
 284 **/
 285 UINT8
 286 EFIAPI
 287 PciExpressBitFieldOr8 (
 288   IN      UINTN                     Address,
 289   IN      UINTN                     StartBit,
 290   IN      UINTN                     EndBit,
 291   IN      UINT8                     OrData
 292   );
 293
 294 /**
 295   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 296   AND, and writes the result back to the bit field in the 8-bit register.
 297
 298   Reads the 8-bit PCI configuration register specified by Address, performs a
 299   bitwise AND between the read result and the value specified by AndData, and
 300   writes the result to the 8-bit PCI configuration register specified by
 301   Address. The value written to the PCI configuration register is returned.
 302   This function must guarantee that all PCI read and write operations are
 303   serialized. Extra left bits in AndData are stripped.
 304
 305   If Address > 0x0FFFFFFF, then ASSERT().
 306   If StartBit is greater than 7, then ASSERT().
 307   If EndBit is greater than 7, then ASSERT().
 308   If EndBit is less than StartBit, then ASSERT().
 309   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 310
 311   @param  Address   PCI configuration register to write.
 312   @param  StartBit  The ordinal of the least significant bit in the bit field.
 313                     Range 0..7.
 314   @param  EndBit    The ordinal of the most significant bit in the bit field.
 315                     Range 0..7.
 316   @param  AndData   The value to AND with the PCI configuration register.
 317
 318   @return The value written back to the PCI configuration register.
 319
 320 **/
 321 UINT8
 322 EFIAPI
 323 PciExpressBitFieldAnd8 (
 324   IN      UINTN                     Address,
 325   IN      UINTN                     StartBit,
 326   IN      UINTN                     EndBit,
 327   IN      UINT8                     AndData
 328   );
 329
 330 /**
 331   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 332   bitwise OR, and writes the result back to the bit field in the
 333   8-bit port.
 334
 335   Reads the 8-bit PCI configuration register specified by Address, performs a
 336   bitwise AND followed by a bitwise OR between the read result and
 337   the value specified by AndData, and writes the result to the 8-bit PCI
 338   configuration register specified by Address. The value written to the PCI
 339   configuration register is returned. This function must guarantee that all PCI
 340   read and write operations are serialized. Extra left bits in both AndData and
 341   OrData are stripped.
 342
 343   If Address > 0x0FFFFFFF, then ASSERT().
 344   If StartBit is greater than 7, then ASSERT().
 345   If EndBit is greater than 7, then ASSERT().
 346   If EndBit is less than StartBit, then ASSERT().
 347   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 348   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 349
 350   @param  Address   PCI configuration register to write.
 351   @param  StartBit  The ordinal of the least significant bit in the bit field.
 352                     Range 0..7.
 353   @param  EndBit    The ordinal of the most significant bit in the bit field.
 354                     Range 0..7.
 355   @param  AndData   The value to AND with the PCI configuration register.
 356   @param  OrData    The value to OR with the result of the AND operation.
 357
 358   @return The value written back to the PCI configuration register.
 359
 360 **/
 361 UINT8
 362 EFIAPI
 363 PciExpressBitFieldAndThenOr8 (
 364   IN      UINTN                     Address,
 365   IN      UINTN                     StartBit,
 366   IN      UINTN                     EndBit,
 367   IN      UINT8                     AndData,
 368   IN      UINT8                     OrData
 369   );
 370
 371 /**
 372   Reads a 16-bit PCI configuration register.
 373
 374   Reads and returns the 16-bit PCI configuration register specified by Address.
 375   This function must guarantee that all PCI read and write operations are
 376   serialized.
 377
 378   If Address > 0x0FFFFFFF, then ASSERT().
 379   If Address is not aligned on a 16-bit boundary, then ASSERT().
 380
 381   @param  Address Address that encodes the PCI Bus, Device, Function and
 382                   Register.
 383
 384   @return The read value from the PCI configuration register.
 385
 386 **/
 387 UINT16
 388 EFIAPI
 389 PciExpressRead16 (
 390   IN      UINTN                     Address
 391   );
 392
 393 /**
 394   Writes a 16-bit PCI configuration register.
 395
 396   Writes the 16-bit PCI configuration register specified by Address with the
 397   value specified by Value. Value is returned. This function must guarantee
 398   that all PCI read and write operations are serialized.
 399
 400   If Address > 0x0FFFFFFF, then ASSERT().
 401   If Address is not aligned on a 16-bit boundary, then ASSERT().
 402
 403   @param  Address Address that encodes the PCI Bus, Device, Function and
 404                   Register.
 405   @param  Value   The value to write.
 406
 407   @return The value written to the PCI configuration register.
 408
 409 **/
 410 UINT16
 411 EFIAPI
 412 PciExpressWrite16 (
 413   IN      UINTN                     Address,
 414   IN      UINT16                    Value
 415   );
 416
 417 /**
 418   Performs a bitwise OR of a 16-bit PCI configuration register with
 419   a 16-bit value.
 420
 421   Reads the 16-bit PCI configuration register specified by Address, performs a
 422   bitwise OR between the read result and the value specified by
 423   OrData, and writes the result to the 16-bit PCI configuration register
 424   specified by Address. The value written to the PCI configuration register is
 425   returned. This function must guarantee that all PCI read and write operations
 426   are serialized.
 427
 428   If Address > 0x0FFFFFFF, then ASSERT().
 429   If Address is not aligned on a 16-bit boundary, then ASSERT().
 430
 431   @param  Address Address that encodes the PCI Bus, Device, Function and
 432                   Register.
 433   @param  OrData  The value to OR with the PCI configuration register.
 434
 435   @return The value written back to the PCI configuration register.
 436
 437 **/
 438 UINT16
 439 EFIAPI
 440 PciExpressOr16 (
 441   IN      UINTN                     Address,
 442   IN      UINT16                    OrData
 443   );
 444
 445 /**
 446   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 447   value.
 448
 449   Reads the 16-bit PCI configuration register specified by Address, performs a
 450   bitwise AND between the read result and the value specified by AndData, and
 451   writes the result to the 16-bit PCI configuration register specified by
 452   Address. The value written to the PCI configuration register is returned.
 453   This function must guarantee that all PCI read and write operations are
 454   serialized.
 455
 456   If Address > 0x0FFFFFFF, then ASSERT().
 457   If Address is not aligned on a 16-bit boundary, then ASSERT().
 458
 459   @param  Address Address that encodes the PCI Bus, Device, Function and
 460                   Register.
 461   @param  AndData The value to AND with the PCI configuration register.
 462
 463   @return The value written back to the PCI configuration register.
 464
 465 **/
 466 UINT16
 467 EFIAPI
 468 PciExpressAnd16 (
 469   IN      UINTN                     Address,
 470   IN      UINT16                    AndData
 471   );
 472
 473 /**
 474   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 475   value, followed a  bitwise OR with another 16-bit value.
 476
 477   Reads the 16-bit PCI configuration register specified by Address, performs a
 478   bitwise AND between the read result and the value specified by AndData,
 479   performs a bitwise OR between the result of the AND operation and
 480   the value specified by OrData, and writes the result to the 16-bit PCI
 481   configuration register specified by Address. The value written to the PCI
 482   configuration register is returned. This function must guarantee that all PCI
 483   read and write operations are serialized.
 484
 485   If Address > 0x0FFFFFFF, then ASSERT().
 486   If Address is not aligned on a 16-bit boundary, then ASSERT().
 487
 488   @param  Address Address that encodes the PCI Bus, Device, Function and
 489                   Register.
 490   @param  AndData The value to AND with the PCI configuration register.
 491   @param  OrData  The value to OR with the result of the AND operation.
 492
 493   @return The value written back to the PCI configuration register.
 494
 495 **/
 496 UINT16
 497 EFIAPI
 498 PciExpressAndThenOr16 (
 499   IN      UINTN                     Address,
 500   IN      UINT16                    AndData,
 501   IN      UINT16                    OrData
 502   );
 503
 504 /**
 505   Reads a bit field of a PCI configuration register.
 506
 507   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 508   specified by the StartBit and the EndBit. The value of the bit field is
 509   returned.
 510
 511   If Address > 0x0FFFFFFF, then ASSERT().
 512   If Address is not aligned on a 16-bit boundary, then ASSERT().
 513   If StartBit is greater than 15, then ASSERT().
 514   If EndBit is greater than 15, then ASSERT().
 515   If EndBit is less than StartBit, then ASSERT().
 516
 517   @param  Address   PCI configuration register to read.
 518   @param  StartBit  The ordinal of the least significant bit in the bit field.
 519                     Range 0..15.
 520   @param  EndBit    The ordinal of the most significant bit in the bit field.
 521                     Range 0..15.
 522
 523   @return The value of the bit field read from the PCI configuration register.
 524
 525 **/
 526 UINT16
 527 EFIAPI
 528 PciExpressBitFieldRead16 (
 529   IN      UINTN                     Address,
 530   IN      UINTN                     StartBit,
 531   IN      UINTN                     EndBit
 532   );
 533
 534 /**
 535   Writes a bit field to a PCI configuration register.
 536
 537   Writes Value to the bit field of the PCI configuration register. The bit
 538   field is specified by the StartBit and the EndBit. All other bits in the
 539   destination PCI configuration register are preserved. The new value of the
 540   16-bit register is returned.
 541
 542   If Address > 0x0FFFFFFF, then ASSERT().
 543   If Address is not aligned on a 16-bit boundary, then ASSERT().
 544   If StartBit is greater than 15, then ASSERT().
 545   If EndBit is greater than 15, then ASSERT().
 546   If EndBit is less than StartBit, then ASSERT().
 547   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 548
 549   @param  Address   PCI configuration register to write.
 550   @param  StartBit  The ordinal of the least significant bit in the bit field.
 551                     Range 0..15.
 552   @param  EndBit    The ordinal of the most significant bit in the bit field.
 553                     Range 0..15.
 554   @param  Value     New value of the bit field.
 555
 556   @return The value written back to the PCI configuration register.
 557
 558 **/
 559 UINT16
 560 EFIAPI
 561 PciExpressBitFieldWrite16 (
 562   IN      UINTN                     Address,
 563   IN      UINTN                     StartBit,
 564   IN      UINTN                     EndBit,
 565   IN      UINT16                    Value
 566   );
 567
 568 /**
 569   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 570   writes the result back to the bit field in the 16-bit port.
 571
 572   Reads the 16-bit PCI configuration register specified by Address, performs a
 573   bitwise OR between the read result and the value specified by
 574   OrData, and writes the result to the 16-bit PCI configuration register
 575   specified by Address. The value written to the PCI configuration register is
 576   returned. This function must guarantee that all PCI read and write operations
 577   are serialized. Extra left bits in OrData are stripped.
 578
 579   If Address > 0x0FFFFFFF, then ASSERT().
 580   If Address is not aligned on a 16-bit boundary, then ASSERT().
 581   If StartBit is greater than 15, then ASSERT().
 582   If EndBit is greater than 15, then ASSERT().
 583   If EndBit is less than StartBit, then ASSERT().
 584   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 585
 586   @param  Address   PCI configuration register to write.
 587   @param  StartBit  The ordinal of the least significant bit in the bit field.
 588                     Range 0..15.
 589   @param  EndBit    The ordinal of the most significant bit in the bit field.
 590                     Range 0..15.
 591   @param  OrData    The value to OR with the PCI configuration register.
 592
 593   @return The value written back to the PCI configuration register.
 594
 595 **/
 596 UINT16
 597 EFIAPI
 598 PciExpressBitFieldOr16 (
 599   IN      UINTN                     Address,
 600   IN      UINTN                     StartBit,
 601   IN      UINTN                     EndBit,
 602   IN      UINT16                    OrData
 603   );
 604
 605 /**
 606   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 607   AND, and writes the result back to the bit field in the 16-bit register.
 608
 609   Reads the 16-bit PCI configuration register specified by Address, performs a
 610   bitwise AND between the read result and the value specified by AndData, and
 611   writes the result to the 16-bit PCI configuration register specified by
 612   Address. The value written to the PCI configuration register is returned.
 613   This function must guarantee that all PCI read and write operations are
 614   serialized. Extra left bits in AndData are stripped.
 615
 616   If Address > 0x0FFFFFFF, then ASSERT().
 617   If Address is not aligned on a 16-bit boundary, then ASSERT().
 618   If StartBit is greater than 15, then ASSERT().
 619   If EndBit is greater than 15, then ASSERT().
 620   If EndBit is less than StartBit, then ASSERT().
 621   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 622
 623   @param  Address   PCI configuration register to write.
 624   @param  StartBit  The ordinal of the least significant bit in the bit field.
 625                     Range 0..15.
 626   @param  EndBit    The ordinal of the most significant bit in the bit field.
 627                     Range 0..15.
 628   @param  AndData   The value to AND with the PCI configuration register.
 629
 630   @return The value written back to the PCI configuration register.
 631
 632 **/
 633 UINT16
 634 EFIAPI
 635 PciExpressBitFieldAnd16 (
 636   IN      UINTN                     Address,
 637   IN      UINTN                     StartBit,
 638   IN      UINTN                     EndBit,
 639   IN      UINT16                    AndData
 640   );
 641
 642 /**
 643   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 644   bitwise OR, and writes the result back to the bit field in the
 645   16-bit port.
 646
 647   Reads the 16-bit PCI configuration register specified by Address, performs a
 648   bitwise AND followed by a bitwise OR between the read result and
 649   the value specified by AndData, and writes the result to the 16-bit PCI
 650   configuration register specified by Address. The value written to the PCI
 651   configuration register is returned. This function must guarantee that all PCI
 652   read and write operations are serialized. Extra left bits in both AndData and
 653   OrData are stripped.
 654
 655   If Address > 0x0FFFFFFF, then ASSERT().
 656   If Address is not aligned on a 16-bit boundary, then ASSERT().
 657   If StartBit is greater than 15, then ASSERT().
 658   If EndBit is greater than 15, then ASSERT().
 659   If EndBit is less than StartBit, then ASSERT().
 660   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 661   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 662
 663   @param  Address   PCI configuration register to write.
 664   @param  StartBit  The ordinal of the least significant bit in the bit field.
 665                     Range 0..15.
 666   @param  EndBit    The ordinal of the most significant bit in the bit field.
 667                     Range 0..15.
 668   @param  AndData   The value to AND with the PCI configuration register.
 669   @param  OrData    The value to OR with the result of the AND operation.
 670
 671   @return The value written back to the PCI configuration register.
 672
 673 **/
 674 UINT16
 675 EFIAPI
 676 PciExpressBitFieldAndThenOr16 (
 677   IN      UINTN                     Address,
 678   IN      UINTN                     StartBit,
 679   IN      UINTN                     EndBit,
 680   IN      UINT16                    AndData,
 681   IN      UINT16                    OrData
 682   );
 683
 684 /**
 685   Reads a 32-bit PCI configuration register.
 686
 687   Reads and returns the 32-bit PCI configuration register specified by Address.
 688   This function must guarantee that all PCI read and write operations are
 689   serialized.
 690
 691   If Address > 0x0FFFFFFF, then ASSERT().
 692   If Address is not aligned on a 32-bit boundary, then ASSERT().
 693
 694   @param  Address Address that encodes the PCI Bus, Device, Function and
 695                   Register.
 696
 697   @return The read value from the PCI configuration register.
 698
 699 **/
 700 UINT32
 701 EFIAPI
 702 PciExpressRead32 (
 703   IN      UINTN                     Address
 704   );
 705
 706 /**
 707   Writes a 32-bit PCI configuration register.
 708
 709   Writes the 32-bit PCI configuration register specified by Address with the
 710   value specified by Value. Value is returned. This function must guarantee
 711   that all PCI read and write operations are serialized.
 712
 713   If Address > 0x0FFFFFFF, then ASSERT().
 714   If Address is not aligned on a 32-bit boundary, then ASSERT().
 715
 716   @param  Address Address that encodes the PCI Bus, Device, Function and
 717                   Register.
 718   @param  Value   The value to write.
 719
 720   @return The value written to the PCI configuration register.
 721
 722 **/
 723 UINT32
 724 EFIAPI
 725 PciExpressWrite32 (
 726   IN      UINTN                     Address,
 727   IN      UINT32                    Value
 728   );
 729
 730 /**
 731   Performs a bitwise OR of a 32-bit PCI configuration register with
 732   a 32-bit value.
 733
 734   Reads the 32-bit PCI configuration register specified by Address, performs a
 735   bitwise OR between the read result and the value specified by
 736   OrData, and writes the result to the 32-bit PCI configuration register
 737   specified by Address. The value written to the PCI configuration register is
 738   returned. This function must guarantee that all PCI read and write operations
 739   are serialized.
 740
 741   If Address > 0x0FFFFFFF, then ASSERT().
 742   If Address is not aligned on a 32-bit boundary, then ASSERT().
 743
 744   @param  Address Address that encodes the PCI Bus, Device, Function and
 745                   Register.
 746   @param  OrData  The value to OR with the PCI configuration register.
 747
 748   @return The value written back to the PCI configuration register.
 749
 750 **/
 751 UINT32
 752 EFIAPI
 753 PciExpressOr32 (
 754   IN      UINTN                     Address,
 755   IN      UINT32                    OrData
 756   );
 757
 758 /**
 759   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 760   value.
 761
 762   Reads the 32-bit PCI configuration register specified by Address, performs a
 763   bitwise AND between the read result and the value specified by AndData, and
 764   writes the result to the 32-bit PCI configuration register specified by
 765   Address. The value written to the PCI configuration register is returned.
 766   This function must guarantee that all PCI read and write operations are
 767   serialized.
 768
 769   If Address > 0x0FFFFFFF, then ASSERT().
 770   If Address is not aligned on a 32-bit boundary, then ASSERT().
 771
 772   @param  Address Address that encodes the PCI Bus, Device, Function and
 773                   Register.
 774   @param  AndData The value to AND with the PCI configuration register.
 775
 776   @return The value written back to the PCI configuration register.
 777
 778 **/
 779 UINT32
 780 EFIAPI
 781 PciExpressAnd32 (
 782   IN      UINTN                     Address,
 783   IN      UINT32                    AndData
 784   );
 785
 786 /**
 787   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 788   value, followed a  bitwise OR with another 32-bit value.
 789
 790   Reads the 32-bit PCI configuration register specified by Address, performs a
 791   bitwise AND between the read result and the value specified by AndData,
 792   performs a bitwise OR between the result of the AND operation and
 793   the value specified by OrData, and writes the result to the 32-bit PCI
 794   configuration register specified by Address. The value written to the PCI
 795   configuration register is returned. This function must guarantee that all PCI
 796   read and write operations are serialized.
 797
 798   If Address > 0x0FFFFFFF, then ASSERT().
 799   If Address is not aligned on a 32-bit boundary, then ASSERT().
 800
 801   @param  Address Address that encodes the PCI Bus, Device, Function and
 802                   Register.
 803   @param  AndData The value to AND with the PCI configuration register.
 804   @param  OrData  The value to OR with the result of the AND operation.
 805
 806   @return The value written back to the PCI configuration register.
 807
 808 **/
 809 UINT32
 810 EFIAPI
 811 PciExpressAndThenOr32 (
 812   IN      UINTN                     Address,
 813   IN      UINT32                    AndData,
 814   IN      UINT32                    OrData
 815   );
 816
 817 /**
 818   Reads a bit field of a PCI configuration register.
 819
 820   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 821   specified by the StartBit and the EndBit. The value of the bit field is
 822   returned.
 823
 824   If Address > 0x0FFFFFFF, then ASSERT().
 825   If Address is not aligned on a 32-bit boundary, then ASSERT().
 826   If StartBit is greater than 31, then ASSERT().
 827   If EndBit is greater than 31, then ASSERT().
 828   If EndBit is less than StartBit, then ASSERT().
 829
 830   @param  Address   PCI configuration register to read.
 831   @param  StartBit  The ordinal of the least significant bit in the bit field.
 832                     Range 0..31.
 833   @param  EndBit    The ordinal of the most significant bit in the bit field.
 834                     Range 0..31.
 835
 836   @return The value of the bit field read from the PCI configuration register.
 837
 838 **/
 839 UINT32
 840 EFIAPI
 841 PciExpressBitFieldRead32 (
 842   IN      UINTN                     Address,
 843   IN      UINTN                     StartBit,
 844   IN      UINTN                     EndBit
 845   );
 846
 847 /**
 848   Writes a bit field to a PCI configuration register.
 849
 850   Writes Value to the bit field of the PCI configuration register. The bit
 851   field is specified by the StartBit and the EndBit. All other bits in the
 852   destination PCI configuration register are preserved. The new value of the
 853   32-bit register is returned.
 854
 855   If Address > 0x0FFFFFFF, then ASSERT().
 856   If Address is not aligned on a 32-bit boundary, then ASSERT().
 857   If StartBit is greater than 31, then ASSERT().
 858   If EndBit is greater than 31, then ASSERT().
 859   If EndBit is less than StartBit, then ASSERT().
 860   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 861
 862   @param  Address   PCI configuration register to write.
 863   @param  StartBit  The ordinal of the least significant bit in the bit field.
 864                     Range 0..31.
 865   @param  EndBit    The ordinal of the most significant bit in the bit field.
 866                     Range 0..31.
 867   @param  Value     New value of the bit field.
 868
 869   @return The value written back to the PCI configuration register.
 870
 871 **/
 872 UINT32
 873 EFIAPI
 874 PciExpressBitFieldWrite32 (
 875   IN      UINTN                     Address,
 876   IN      UINTN                     StartBit,
 877   IN      UINTN                     EndBit,
 878   IN      UINT32                    Value
 879   );
 880
 881 /**
 882   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 883   writes the result back to the bit field in the 32-bit port.
 884
 885   Reads the 32-bit PCI configuration register specified by Address, performs a
 886   bitwise OR between the read result and the value specified by
 887   OrData, and writes the result to the 32-bit PCI configuration register
 888   specified by Address. The value written to the PCI configuration register is
 889   returned. This function must guarantee that all PCI read and write operations
 890   are serialized. Extra left bits in OrData are stripped.
 891
 892   If Address > 0x0FFFFFFF, then ASSERT().
 893   If Address is not aligned on a 32-bit boundary, then ASSERT().
 894   If StartBit is greater than 31, then ASSERT().
 895   If EndBit is greater than 31, then ASSERT().
 896   If EndBit is less than StartBit, then ASSERT().
 897   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 898
 899   @param  Address   PCI configuration register to write.
 900   @param  StartBit  The ordinal of the least significant bit in the bit field.
 901                     Range 0..31.
 902   @param  EndBit    The ordinal of the most significant bit in the bit field.
 903                     Range 0..31.
 904   @param  OrData    The value to OR with the PCI configuration register.
 905
 906   @return The value written back to the PCI configuration register.
 907
 908 **/
 909 UINT32
 910 EFIAPI
 911 PciExpressBitFieldOr32 (
 912   IN      UINTN                     Address,
 913   IN      UINTN                     StartBit,
 914   IN      UINTN                     EndBit,
 915   IN      UINT32                    OrData
 916   );
 917
 918 /**
 919   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 920   AND, and writes the result back to the bit field in the 32-bit register.
 921
 922   Reads the 32-bit PCI configuration register specified by Address, performs a
 923   bitwise AND between the read result and the value specified by AndData, and
 924   writes the result to the 32-bit PCI configuration register specified by
 925   Address. The value written to the PCI configuration register is returned.
 926   This function must guarantee that all PCI read and write operations are
 927   serialized. Extra left bits in AndData are stripped.
 928
 929   If Address > 0x0FFFFFFF, then ASSERT().
 930   If Address is not aligned on a 32-bit boundary, then ASSERT().
 931   If StartBit is greater than 31, then ASSERT().
 932   If EndBit is greater than 31, then ASSERT().
 933   If EndBit is less than StartBit, then ASSERT().
 934   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 935
 936   @param  Address   PCI configuration register to write.
 937   @param  StartBit  The ordinal of the least significant bit in the bit field.
 938                     Range 0..31.
 939   @param  EndBit    The ordinal of the most significant bit in the bit field.
 940                     Range 0..31.
 941   @param  AndData   The value to AND with the PCI configuration register.
 942
 943   @return The value written back to the PCI configuration register.
 944
 945 **/
 946 UINT32
 947 EFIAPI
 948 PciExpressBitFieldAnd32 (
 949   IN      UINTN                     Address,
 950   IN      UINTN                     StartBit,
 951   IN      UINTN                     EndBit,
 952   IN      UINT32                    AndData
 953   );
 954
 955 /**
 956   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 957   bitwise OR, and writes the result back to the bit field in the
 958   32-bit port.
 959
 960   Reads the 32-bit PCI configuration register specified by Address, performs a
 961   bitwise AND followed by a bitwise OR between the read result and
 962   the value specified by AndData, and writes the result to the 32-bit PCI
 963   configuration register specified by Address. The value written to the PCI
 964   configuration register is returned. This function must guarantee that all PCI
 965   read and write operations are serialized. Extra left bits in both AndData and
 966   OrData are stripped.
 967
 968   If Address > 0x0FFFFFFF, then ASSERT().
 969   If Address is not aligned on a 32-bit boundary, then ASSERT().
 970   If StartBit is greater than 31, then ASSERT().
 971   If EndBit is greater than 31, then ASSERT().
 972   If EndBit is less than StartBit, then ASSERT().
 973   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 974   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 975
 976   @param  Address   PCI configuration register to write.
 977   @param  StartBit  The ordinal of the least significant bit in the bit field.
 978                     Range 0..31.
 979   @param  EndBit    The ordinal of the most significant bit in the bit field.
 980                     Range 0..31.
 981   @param  AndData   The value to AND with the PCI configuration register.
 982   @param  OrData    The value to OR with the result of the AND operation.
 983
 984   @return The value written back to the PCI configuration register.
 985
 986 **/
 987 UINT32
 988 EFIAPI
 989 PciExpressBitFieldAndThenOr32 (
 990   IN      UINTN                     Address,
 991   IN      UINTN                     StartBit,
 992   IN      UINTN                     EndBit,
 993   IN      UINT32                    AndData,
 994   IN      UINT32                    OrData
 995   );
 996
 997 /**
 998   Reads a range of PCI configuration registers into a caller supplied buffer.
 999
1000   Reads the range of PCI configuration registers specified by StartAddress and
1001   Size into the buffer specified by Buffer. This function only allows the PCI
1002   configuration registers from a single PCI function to be read. Size is
1003   returned. When possible 32-bit PCI configuration read cycles are used to read
1004   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1005   and 16-bit PCI configuration read cycles may be used at the beginning and the
1006   end of the range.
1007
1008   If StartAddress > 0x0FFFFFFF, then ASSERT().
1009   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1010   If Size > 0 and Buffer is NULL, then ASSERT().
1011
1012   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1013                         Function and Register.
1014   @param  Size          Size in bytes of the transfer.
1015   @param  Buffer        Pointer to a buffer receiving the data read.
1016
1017   @return Size read data from StartAddress.
1018
1019 **/
1020 UINTN
1021 EFIAPI
1022 PciExpressReadBuffer (
1023   IN      UINTN                     StartAddress,
1024   IN      UINTN                     Size,
1025   OUT     VOID                      *Buffer
1026   );
1027
1028 /**
1029   Copies the data in a caller supplied buffer to a specified range of PCI
1030   configuration space.
1031
1032   Writes the range of PCI configuration registers specified by StartAddress and
1033   Size from the buffer specified by Buffer. This function only allows the PCI
1034   configuration registers from a single PCI function to be written. Size is
1035   returned. When possible 32-bit PCI configuration write cycles are used to
1036   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1037   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1038   and the end of the range.
1039
1040   If StartAddress > 0x0FFFFFFF, then ASSERT().
1041   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1042   If Size > 0 and Buffer is NULL, then ASSERT().
1043
1044   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1045                         Function and Register.
1046   @param  Size          Size in bytes of the transfer.
1047   @param  Buffer        Pointer to a buffer containing the data to write.
1048
1049   @return Size written to StartAddress.
1050
1051 **/
1052 UINTN
1053 EFIAPI
1054 PciExpressWriteBuffer (
1055   IN      UINTN                     StartAddress,
1056   IN      UINTN                     Size,
1057   IN      VOID                      *Buffer
1058   );
1059
1060 #endif