MdePkg/Include/Library/PciLib.h

   1 /** @file
   2   PCI Library Services for PCI Segment #0
   3
   4   Copyright (c) 2006, Intel Corporation
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13   Module Name:  PciLib.h
  14
  15 **/
  16
  17 #ifndef __PCI_LIB_H__
  18 #define __PCI_LIB_H__
  19
  20 /**
  21   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  22   address that can be passed to the PCI Library functions.
  23
  24   @param  Bus       PCI Bus number. Range 0..255.
  25   @param  Device    PCI Device number. Range 0..31.
  26   @param  Function  PCI Function number. Range 0..7.
  27   @param  Register  PCI Register number. Range 0..255 for PCI. Range 0..4095
  28                     for PCI Express.
  29
  30   @return The encoded PCI address.
  31
  32 **/
  33 #define PCI_LIB_ADDRESS(Bus,Device,Function,Offset)   \
  34   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  35
  36 /**
  37   Reads an 8-bit PCI configuration register.
  38
  39   Reads and returns the 8-bit PCI configuration register specified by Address.
  40   This function must guarantee that all PCI read and write operations are
  41   serialized.
  42
  43   If Address > 0x0FFFFFFF, then ASSERT().
  44
  45   @param  Address Address that encodes the PCI Bus, Device, Function and
  46                   Register.
  47
  48   @return The read value from the PCI configuration register.
  49
  50 **/
  51 UINT8
  52 EFIAPI
  53 PciRead8 (
  54   IN      UINTN                     Address
  55   );
  56
  57 /**
  58   Writes an 8-bit PCI configuration register.
  59
  60   Writes the 8-bit PCI configuration register specified by Address with the
  61   value specified by Value. Value is returned. This function must guarantee
  62   that all PCI read and write operations are serialized.
  63
  64   If Address > 0x0FFFFFFF, then ASSERT().
  65
  66   @param  Address Address that encodes the PCI Bus, Device, Function and
  67                   Register.
  68   @param  Value   The value to write.
  69
  70   @return The value written to the PCI configuration register.
  71
  72 **/
  73 UINT8
  74 EFIAPI
  75 PciWrite8 (
  76   IN      UINTN                     Address,
  77   IN      UINT8                     Data
  78   );
  79
  80 /**
  81   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
  82   an 8-bit value.
  83
  84   Reads the 8-bit PCI configuration register specified by Address, performs a
  85   bitwise inclusive OR between the read result and the value specified by
  86   OrData, and writes the result to the 8-bit PCI configuration register
  87   specified by Address. The value written to the PCI configuration register is
  88   returned. This function must guarantee that all PCI read and write operations
  89   are serialized.
  90
  91   If Address > 0x0FFFFFFF, then ASSERT().
  92
  93   @param  Address Address that encodes the PCI Bus, Device, Function and
  94                   Register.
  95   @param  OrData  The value to OR with the PCI configuration register.
  96
  97   @return The value written back to the PCI configuration register.
  98
  99 **/
 100 UINT8
 101 EFIAPI
 102 PciOr8 (
 103   IN      UINTN                     Address,
 104   IN      UINT8                     OrData
 105   );
 106
 107 /**
 108   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 109   value.
 110
 111   Reads the 8-bit PCI configuration register specified by Address, performs a
 112   bitwise AND between the read result and the value specified by AndData, and
 113   writes the result to the 8-bit PCI configuration register specified by
 114   Address. The value written to the PCI configuration register is returned.
 115   This function must guarantee that all PCI read and write operations are
 116   serialized.
 117
 118   If Address > 0x0FFFFFFF, then ASSERT().
 119
 120   @param  Address Address that encodes the PCI Bus, Device, Function and
 121                   Register.
 122   @param  AndData The value to AND with the PCI configuration register.
 123
 124   @return The value written back to the PCI configuration register.
 125
 126 **/
 127 UINT8
 128 EFIAPI
 129 PciAnd8 (
 130   IN      UINTN                     Address,
 131   IN      UINT8                     AndData
 132   );
 133
 134 /**
 135   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 136   value, followed a  bitwise inclusive OR with another 8-bit value.
 137
 138   Reads the 8-bit PCI configuration register specified by Address, performs a
 139   bitwise AND between the read result and the value specified by AndData,
 140   performs a bitwise inclusive OR between the result of the AND operation and
 141   the value specified by OrData, and writes the result to the 8-bit PCI
 142   configuration register specified by Address. The value written to the PCI
 143   configuration register is returned. This function must guarantee that all PCI
 144   read and write operations are serialized.
 145
 146   If Address > 0x0FFFFFFF, then ASSERT().
 147
 148   @param  Address Address that encodes the PCI Bus, Device, Function and
 149                   Register.
 150   @param  AndData The value to AND with the PCI configuration register.
 151   @param  OrData  The value to OR with the result of the AND operation.
 152
 153   @return The value written back to the PCI configuration register.
 154
 155 **/
 156 UINT8
 157 EFIAPI
 158 PciAndThenOr8 (
 159   IN      UINTN                     Address,
 160   IN      UINT8                     AndData,
 161   IN      UINT8                     OrData
 162   );
 163
 164 /**
 165   Reads a bit field of a PCI configuration register.
 166
 167   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 168   specified by the StartBit and the EndBit. The value of the bit field is
 169   returned.
 170
 171   If Address > 0x0FFFFFFF, then ASSERT().
 172   If StartBit is greater than 7, then ASSERT().
 173   If EndBit is greater than 7, then ASSERT().
 174   If EndBit is less than StartBit, then ASSERT().
 175
 176   @param  Address   PCI configuration register to read.
 177   @param  StartBit  The ordinal of the least significant bit in the bit field.
 178                     Range 0..7.
 179   @param  EndBit    The ordinal of the most significant bit in the bit field.
 180                     Range 0..7.
 181
 182   @return The value of the bit field read from the PCI configuration register.
 183
 184 **/
 185 UINT8
 186 EFIAPI
 187 PciBitFieldRead8 (
 188   IN      UINTN                     Address,
 189   IN      UINTN                     StartBit,
 190   IN      UINTN                     EndBit
 191   );
 192
 193 /**
 194   Writes a bit field to a PCI configuration register.
 195
 196   Writes Value to the bit field of the PCI configuration register. The bit
 197   field is specified by the StartBit and the EndBit. All other bits in the
 198   destination PCI configuration register are preserved. The new value of the
 199   8-bit register is returned.
 200
 201   If Address > 0x0FFFFFFF, then ASSERT().
 202   If StartBit is greater than 7, then ASSERT().
 203   If EndBit is greater than 7, then ASSERT().
 204   If EndBit is less than StartBit, then ASSERT().
 205
 206   @param  Address   PCI configuration register to write.
 207   @param  StartBit  The ordinal of the least significant bit in the bit field.
 208                     Range 0..7.
 209   @param  EndBit    The ordinal of the most significant bit in the bit field.
 210                     Range 0..7.
 211   @param  Value     New value of the bit field.
 212
 213   @return The value written back to the PCI configuration register.
 214
 215 **/
 216 UINT8
 217 EFIAPI
 218 PciBitFieldWrite8 (
 219   IN      UINTN                     Address,
 220   IN      UINTN                     StartBit,
 221   IN      UINTN                     EndBit,
 222   IN      UINT8                     Value
 223   );
 224
 225 /**
 226   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 227   writes the result back to the bit field in the 8-bit port.
 228
 229   Reads the 8-bit PCI configuration register specified by Address, performs a
 230   bitwise inclusive OR between the read result and the value specified by
 231   OrData, and writes the result to the 8-bit PCI configuration register
 232   specified by Address. The value written to the PCI configuration register is
 233   returned. This function must guarantee that all PCI read and write operations
 234   are serialized. Extra left bits in OrData are stripped.
 235
 236   If Address > 0x0FFFFFFF, then ASSERT().
 237   If StartBit is greater than 7, then ASSERT().
 238   If EndBit is greater than 7, then ASSERT().
 239   If EndBit is less than StartBit, then ASSERT().
 240
 241   @param  Address   PCI configuration register to write.
 242   @param  StartBit  The ordinal of the least significant bit in the bit field.
 243                     Range 0..7.
 244   @param  EndBit    The ordinal of the most significant bit in the bit field.
 245                     Range 0..7.
 246   @param  OrData    The value to OR with the PCI configuration register.
 247
 248   @return The value written back to the PCI configuration register.
 249
 250 **/
 251 UINT8
 252 EFIAPI
 253 PciBitFieldOr8 (
 254   IN      UINTN                     Address,
 255   IN      UINTN                     StartBit,
 256   IN      UINTN                     EndBit,
 257   IN      UINT8                     OrData
 258   );
 259
 260 /**
 261   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 262   AND, and writes the result back to the bit field in the 8-bit register.
 263
 264   Reads the 8-bit PCI configuration register specified by Address, performs a
 265   bitwise AND between the read result and the value specified by AndData, and
 266   writes the result to the 8-bit PCI configuration register specified by
 267   Address. The value written to the PCI configuration register is returned.
 268   This function must guarantee that all PCI read and write operations are
 269   serialized. Extra left bits in AndData are stripped.
 270
 271   If Address > 0x0FFFFFFF, then ASSERT().
 272   If StartBit is greater than 7, then ASSERT().
 273   If EndBit is greater than 7, then ASSERT().
 274   If EndBit is less than StartBit, then ASSERT().
 275
 276   @param  Address   PCI configuration register to write.
 277   @param  StartBit  The ordinal of the least significant bit in the bit field.
 278                     Range 0..7.
 279   @param  EndBit    The ordinal of the most significant bit in the bit field.
 280                     Range 0..7.
 281   @param  AndData   The value to AND with the PCI configuration register.
 282
 283   @return The value written back to the PCI configuration register.
 284
 285 **/
 286 UINT8
 287 EFIAPI
 288 PciBitFieldAnd8 (
 289   IN      UINTN                     Address,
 290   IN      UINTN                     StartBit,
 291   IN      UINTN                     EndBit,
 292   IN      UINT8                     AndData
 293   );
 294
 295 /**
 296   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 297   bitwise inclusive OR, and writes the result back to the bit field in the
 298   8-bit port.
 299
 300   Reads the 8-bit PCI configuration register specified by Address, performs a
 301   bitwise AND followed by a bitwise inclusive OR between the read result and
 302   the value specified by AndData, and writes the result to the 8-bit PCI
 303   configuration register specified by Address. The value written to the PCI
 304   configuration register is returned. This function must guarantee that all PCI
 305   read and write operations are serialized. Extra left bits in both AndData and
 306   OrData are stripped.
 307
 308   If Address > 0x0FFFFFFF, then ASSERT().
 309   If StartBit is greater than 7, then ASSERT().
 310   If EndBit is greater than 7, then ASSERT().
 311   If EndBit is less than StartBit, then ASSERT().
 312
 313   @param  Address   PCI configuration register to write.
 314   @param  StartBit  The ordinal of the least significant bit in the bit field.
 315                     Range 0..7.
 316   @param  EndBit    The ordinal of the most significant bit in the bit field.
 317                     Range 0..7.
 318   @param  AndData   The value to AND with the PCI configuration register.
 319   @param  OrData    The value to OR with the result of the AND operation.
 320
 321   @return The value written back to the PCI configuration register.
 322
 323 **/
 324 UINT8
 325 EFIAPI
 326 PciBitFieldAndThenOr8 (
 327   IN      UINTN                     Address,
 328   IN      UINTN                     StartBit,
 329   IN      UINTN                     EndBit,
 330   IN      UINT8                     AndData,
 331   IN      UINT8                     OrData
 332   );
 333
 334 /**
 335   Reads a 16-bit PCI configuration register.
 336
 337   Reads and returns the 16-bit PCI configuration register specified by Address.
 338   This function must guarantee that all PCI read and write operations are
 339   serialized.
 340
 341   If Address > 0x0FFFFFFF, then ASSERT().
 342   If Address is not aligned on a 16-bit boundary, then ASSERT().
 343
 344   @param  Address Address that encodes the PCI Bus, Device, Function and
 345                   Register.
 346
 347   @return The read value from the PCI configuration register.
 348
 349 **/
 350 UINT16
 351 EFIAPI
 352 PciRead16 (
 353   IN      UINTN                     Address
 354   );
 355
 356 /**
 357   Writes a 16-bit PCI configuration register.
 358
 359   Writes the 16-bit PCI configuration register specified by Address with the
 360   value specified by Value. Value is returned. This function must guarantee
 361   that all PCI read and write operations are serialized.
 362
 363   If Address > 0x0FFFFFFF, then ASSERT().
 364   If Address is not aligned on a 16-bit boundary, then ASSERT().
 365
 366   @param  Address Address that encodes the PCI Bus, Device, Function and
 367                   Register.
 368   @param  Value   The value to write.
 369
 370   @return The value written to the PCI configuration register.
 371
 372 **/
 373 UINT16
 374 EFIAPI
 375 PciWrite16 (
 376   IN      UINTN                     Address,
 377   IN      UINT16                    Data
 378   );
 379
 380 /**
 381   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 382   a 16-bit value.
 383
 384   Reads the 16-bit PCI configuration register specified by Address, performs a
 385   bitwise inclusive OR between the read result and the value specified by
 386   OrData, and writes the result to the 16-bit PCI configuration register
 387   specified by Address. The value written to the PCI configuration register is
 388   returned. This function must guarantee that all PCI read and write operations
 389   are serialized.
 390
 391   If Address > 0x0FFFFFFF, then ASSERT().
 392   If Address is not aligned on a 16-bit boundary, then ASSERT().
 393
 394   @param  Address Address that encodes the PCI Bus, Device, Function and
 395                   Register.
 396   @param  OrData  The value to OR with the PCI configuration register.
 397
 398   @return The value written back to the PCI configuration register.
 399
 400 **/
 401 UINT16
 402 EFIAPI
 403 PciOr16 (
 404   IN      UINTN                     Address,
 405   IN      UINT16                    OrData
 406   );
 407
 408 /**
 409   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 410   value.
 411
 412   Reads the 16-bit PCI configuration register specified by Address, performs a
 413   bitwise AND between the read result and the value specified by AndData, and
 414   writes the result to the 16-bit PCI configuration register specified by
 415   Address. The value written to the PCI configuration register is returned.
 416   This function must guarantee that all PCI read and write operations are
 417   serialized.
 418
 419   If Address > 0x0FFFFFFF, then ASSERT().
 420   If Address is not aligned on a 16-bit boundary, then ASSERT().
 421
 422   @param  Address Address that encodes the PCI Bus, Device, Function and
 423                   Register.
 424   @param  AndData The value to AND with the PCI configuration register.
 425
 426   @return The value written back to the PCI configuration register.
 427
 428 **/
 429 UINT16
 430 EFIAPI
 431 PciAnd16 (
 432   IN      UINTN                     Address,
 433   IN      UINT16                    AndData
 434   );
 435
 436 /**
 437   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 438   value, followed a  bitwise inclusive OR with another 16-bit value.
 439
 440   Reads the 16-bit PCI configuration register specified by Address, performs a
 441   bitwise AND between the read result and the value specified by AndData,
 442   performs a bitwise inclusive OR between the result of the AND operation and
 443   the value specified by OrData, and writes the result to the 16-bit PCI
 444   configuration register specified by Address. The value written to the PCI
 445   configuration register is returned. This function must guarantee that all PCI
 446   read and write operations are serialized.
 447
 448   If Address > 0x0FFFFFFF, then ASSERT().
 449   If Address is not aligned on a 16-bit boundary, then ASSERT().
 450
 451   @param  Address Address that encodes the PCI Bus, Device, Function and
 452                   Register.
 453   @param  AndData The value to AND with the PCI configuration register.
 454   @param  OrData  The value to OR with the result of the AND operation.
 455
 456   @return The value written back to the PCI configuration register.
 457
 458 **/
 459 UINT16
 460 EFIAPI
 461 PciAndThenOr16 (
 462   IN      UINTN                     Address,
 463   IN      UINT16                    AndData,
 464   IN      UINT16                    OrData
 465   );
 466
 467 /**
 468   Reads a bit field of a PCI configuration register.
 469
 470   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 471   specified by the StartBit and the EndBit. The value of the bit field is
 472   returned.
 473
 474   If Address > 0x0FFFFFFF, then ASSERT().
 475   If Address is not aligned on a 16-bit boundary, then ASSERT().
 476   If StartBit is greater than 15, then ASSERT().
 477   If EndBit is greater than 15, then ASSERT().
 478   If EndBit is less than StartBit, then ASSERT().
 479
 480   @param  Address   PCI configuration register to read.
 481   @param  StartBit  The ordinal of the least significant bit in the bit field.
 482                     Range 0..15.
 483   @param  EndBit    The ordinal of the most significant bit in the bit field.
 484                     Range 0..15.
 485
 486   @return The value of the bit field read from the PCI configuration register.
 487
 488 **/
 489 UINT16
 490 EFIAPI
 491 PciBitFieldRead16 (
 492   IN      UINTN                     Address,
 493   IN      UINTN                     StartBit,
 494   IN      UINTN                     EndBit
 495   );
 496
 497 /**
 498   Writes a bit field to a PCI configuration register.
 499
 500   Writes Value to the bit field of the PCI configuration register. The bit
 501   field is specified by the StartBit and the EndBit. All other bits in the
 502   destination PCI configuration register are preserved. The new value of the
 503   16-bit register is returned.
 504
 505   If Address > 0x0FFFFFFF, then ASSERT().
 506   If Address is not aligned on a 16-bit boundary, then ASSERT().
 507   If StartBit is greater than 15, then ASSERT().
 508   If EndBit is greater than 15, then ASSERT().
 509   If EndBit is less than StartBit, then ASSERT().
 510
 511   @param  Address   PCI configuration register to write.
 512   @param  StartBit  The ordinal of the least significant bit in the bit field.
 513                     Range 0..15.
 514   @param  EndBit    The ordinal of the most significant bit in the bit field.
 515                     Range 0..15.
 516   @param  Value     New value of the bit field.
 517
 518   @return The value written back to the PCI configuration register.
 519
 520 **/
 521 UINT16
 522 EFIAPI
 523 PciBitFieldWrite16 (
 524   IN      UINTN                     Address,
 525   IN      UINTN                     StartBit,
 526   IN      UINTN                     EndBit,
 527   IN      UINT16                    Value
 528   );
 529
 530 /**
 531   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 532   writes the result back to the bit field in the 16-bit port.
 533
 534   Reads the 16-bit PCI configuration register specified by Address, performs a
 535   bitwise inclusive OR between the read result and the value specified by
 536   OrData, and writes the result to the 16-bit PCI configuration register
 537   specified by Address. The value written to the PCI configuration register is
 538   returned. This function must guarantee that all PCI read and write operations
 539   are serialized. Extra left bits in OrData are stripped.
 540
 541   If Address > 0x0FFFFFFF, then ASSERT().
 542   If Address is not aligned on a 16-bit boundary, then ASSERT().
 543   If StartBit is greater than 15, then ASSERT().
 544   If EndBit is greater than 15, then ASSERT().
 545   If EndBit is less than StartBit, then ASSERT().
 546
 547   @param  Address   PCI configuration register to write.
 548   @param  StartBit  The ordinal of the least significant bit in the bit field.
 549                     Range 0..15.
 550   @param  EndBit    The ordinal of the most significant bit in the bit field.
 551                     Range 0..15.
 552   @param  OrData    The value to OR with the PCI configuration register.
 553
 554   @return The value written back to the PCI configuration register.
 555
 556 **/
 557 UINT16
 558 EFIAPI
 559 PciBitFieldOr16 (
 560   IN      UINTN                     Address,
 561   IN      UINTN                     StartBit,
 562   IN      UINTN                     EndBit,
 563   IN      UINT16                    OrData
 564   );
 565
 566 /**
 567   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 568   AND, and writes the result back to the bit field in the 16-bit register.
 569
 570   Reads the 16-bit PCI configuration register specified by Address, performs a
 571   bitwise AND between the read result and the value specified by AndData, and
 572   writes the result to the 16-bit PCI configuration register specified by
 573   Address. The value written to the PCI configuration register is returned.
 574   This function must guarantee that all PCI read and write operations are
 575   serialized. Extra left bits in AndData are stripped.
 576
 577   If Address > 0x0FFFFFFF, then ASSERT().
 578   If Address is not aligned on a 16-bit boundary, then ASSERT().
 579   If StartBit is greater than 15, then ASSERT().
 580   If EndBit is greater than 15, then ASSERT().
 581   If EndBit is less than StartBit, then ASSERT().
 582
 583   @param  Address   PCI configuration register to write.
 584   @param  StartBit  The ordinal of the least significant bit in the bit field.
 585                     Range 0..15.
 586   @param  EndBit    The ordinal of the most significant bit in the bit field.
 587                     Range 0..15.
 588   @param  AndData   The value to AND with the PCI configuration register.
 589
 590   @return The value written back to the PCI configuration register.
 591
 592 **/
 593 UINT16
 594 EFIAPI
 595 PciBitFieldAnd16 (
 596   IN      UINTN                     Address,
 597   IN      UINTN                     StartBit,
 598   IN      UINTN                     EndBit,
 599   IN      UINT16                    AndData
 600   );
 601
 602 /**
 603   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 604   bitwise inclusive OR, and writes the result back to the bit field in the
 605   16-bit port.
 606
 607   Reads the 16-bit PCI configuration register specified by Address, performs a
 608   bitwise AND followed by a bitwise inclusive OR between the read result and
 609   the value specified by AndData, and writes the result to the 16-bit PCI
 610   configuration register specified by Address. The value written to the PCI
 611   configuration register is returned. This function must guarantee that all PCI
 612   read and write operations are serialized. Extra left bits in both AndData and
 613   OrData are stripped.
 614
 615   If Address > 0x0FFFFFFF, then ASSERT().
 616   If Address is not aligned on a 16-bit boundary, then ASSERT().
 617   If StartBit is greater than 15, then ASSERT().
 618   If EndBit is greater than 15, then ASSERT().
 619   If EndBit is less than StartBit, then ASSERT().
 620
 621   @param  Address   PCI configuration register to write.
 622   @param  StartBit  The ordinal of the least significant bit in the bit field.
 623                     Range 0..15.
 624   @param  EndBit    The ordinal of the most significant bit in the bit field.
 625                     Range 0..15.
 626   @param  AndData   The value to AND with the PCI configuration register.
 627   @param  OrData    The value to OR with the result of the AND operation.
 628
 629   @return The value written back to the PCI configuration register.
 630
 631 **/
 632 UINT16
 633 EFIAPI
 634 PciBitFieldAndThenOr16 (
 635   IN      UINTN                     Address,
 636   IN      UINTN                     StartBit,
 637   IN      UINTN                     EndBit,
 638   IN      UINT16                    AndData,
 639   IN      UINT16                    OrData
 640   );
 641
 642 /**
 643   Reads a 32-bit PCI configuration register.
 644
 645   Reads and returns the 32-bit PCI configuration register specified by Address.
 646   This function must guarantee that all PCI read and write operations are
 647   serialized.
 648
 649   If Address > 0x0FFFFFFF, then ASSERT().
 650   If Address is not aligned on a 32-bit boundary, then ASSERT().
 651
 652   @param  Address Address that encodes the PCI Bus, Device, Function and
 653                   Register.
 654
 655   @return The read value from the PCI configuration register.
 656
 657 **/
 658 UINT32
 659 EFIAPI
 660 PciRead32 (
 661   IN      UINTN                     Address
 662   );
 663
 664 /**
 665   Writes a 32-bit PCI configuration register.
 666
 667   Writes the 32-bit PCI configuration register specified by Address with the
 668   value specified by Value. Value is returned. This function must guarantee
 669   that all PCI read and write operations are serialized.
 670
 671   If Address > 0x0FFFFFFF, then ASSERT().
 672   If Address is not aligned on a 32-bit boundary, then ASSERT().
 673
 674   @param  Address Address that encodes the PCI Bus, Device, Function and
 675                   Register.
 676   @param  Value   The value to write.
 677
 678   @return The value written to the PCI configuration register.
 679
 680 **/
 681 UINT32
 682 EFIAPI
 683 PciWrite32 (
 684   IN      UINTN                     Address,
 685   IN      UINT32                    Data
 686   );
 687
 688 /**
 689   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 690   a 32-bit value.
 691
 692   Reads the 32-bit PCI configuration register specified by Address, performs a
 693   bitwise inclusive OR between the read result and the value specified by
 694   OrData, and writes the result to the 32-bit PCI configuration register
 695   specified by Address. The value written to the PCI configuration register is
 696   returned. This function must guarantee that all PCI read and write operations
 697   are serialized.
 698
 699   If Address > 0x0FFFFFFF, then ASSERT().
 700   If Address is not aligned on a 32-bit boundary, then ASSERT().
 701
 702   @param  Address Address that encodes the PCI Bus, Device, Function and
 703                   Register.
 704   @param  OrData  The value to OR with the PCI configuration register.
 705
 706   @return The value written back to the PCI configuration register.
 707
 708 **/
 709 UINT32
 710 EFIAPI
 711 PciOr32 (
 712   IN      UINTN                     Address,
 713   IN      UINT32                    OrData
 714   );
 715
 716 /**
 717   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 718   value.
 719
 720   Reads the 32-bit PCI configuration register specified by Address, performs a
 721   bitwise AND between the read result and the value specified by AndData, and
 722   writes the result to the 32-bit PCI configuration register specified by
 723   Address. The value written to the PCI configuration register is returned.
 724   This function must guarantee that all PCI read and write operations are
 725   serialized.
 726
 727   If Address > 0x0FFFFFFF, then ASSERT().
 728   If Address is not aligned on a 32-bit boundary, then ASSERT().
 729
 730   @param  Address Address that encodes the PCI Bus, Device, Function and
 731                   Register.
 732   @param  AndData The value to AND with the PCI configuration register.
 733
 734   @return The value written back to the PCI configuration register.
 735
 736 **/
 737 UINT32
 738 EFIAPI
 739 PciAnd32 (
 740   IN      UINTN                     Address,
 741   IN      UINT32                    AndData
 742   );
 743
 744 /**
 745   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 746   value, followed a  bitwise inclusive OR with another 32-bit value.
 747
 748   Reads the 32-bit PCI configuration register specified by Address, performs a
 749   bitwise AND between the read result and the value specified by AndData,
 750   performs a bitwise inclusive OR between the result of the AND operation and
 751   the value specified by OrData, and writes the result to the 32-bit PCI
 752   configuration register specified by Address. The value written to the PCI
 753   configuration register is returned. This function must guarantee that all PCI
 754   read and write operations are serialized.
 755
 756   If Address > 0x0FFFFFFF, then ASSERT().
 757   If Address is not aligned on a 32-bit boundary, then ASSERT().
 758
 759   @param  Address Address that encodes the PCI Bus, Device, Function and
 760                   Register.
 761   @param  AndData The value to AND with the PCI configuration register.
 762   @param  OrData  The value to OR with the result of the AND operation.
 763
 764   @return The value written back to the PCI configuration register.
 765
 766 **/
 767 UINT32
 768 EFIAPI
 769 PciAndThenOr32 (
 770   IN      UINTN                     Address,
 771   IN      UINT32                    AndData,
 772   IN      UINT32                    OrData
 773   );
 774
 775 /**
 776   Reads a bit field of a PCI configuration register.
 777
 778   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 779   specified by the StartBit and the EndBit. The value of the bit field is
 780   returned.
 781
 782   If Address > 0x0FFFFFFF, then ASSERT().
 783   If Address is not aligned on a 32-bit boundary, then ASSERT().
 784   If StartBit is greater than 31, then ASSERT().
 785   If EndBit is greater than 31, then ASSERT().
 786   If EndBit is less than StartBit, then ASSERT().
 787
 788   @param  Address   PCI configuration register to read.
 789   @param  StartBit  The ordinal of the least significant bit in the bit field.
 790                     Range 0..31.
 791   @param  EndBit    The ordinal of the most significant bit in the bit field.
 792                     Range 0..31.
 793
 794   @return The value of the bit field read from the PCI configuration register.
 795
 796 **/
 797 UINT32
 798 EFIAPI
 799 PciBitFieldRead32 (
 800   IN      UINTN                     Address,
 801   IN      UINTN                     StartBit,
 802   IN      UINTN                     EndBit
 803   );
 804
 805 /**
 806   Writes a bit field to a PCI configuration register.
 807
 808   Writes Value to the bit field of the PCI configuration register. The bit
 809   field is specified by the StartBit and the EndBit. All other bits in the
 810   destination PCI configuration register are preserved. The new value of the
 811   32-bit register is returned.
 812
 813   If Address > 0x0FFFFFFF, then ASSERT().
 814   If Address is not aligned on a 32-bit boundary, then ASSERT().
 815   If StartBit is greater than 31, then ASSERT().
 816   If EndBit is greater than 31, then ASSERT().
 817   If EndBit is less than StartBit, then ASSERT().
 818
 819   @param  Address   PCI configuration register to write.
 820   @param  StartBit  The ordinal of the least significant bit in the bit field.
 821                     Range 0..31.
 822   @param  EndBit    The ordinal of the most significant bit in the bit field.
 823                     Range 0..31.
 824   @param  Value     New value of the bit field.
 825
 826   @return The value written back to the PCI configuration register.
 827
 828 **/
 829 UINT32
 830 EFIAPI
 831 PciBitFieldWrite32 (
 832   IN      UINTN                     Address,
 833   IN      UINTN                     StartBit,
 834   IN      UINTN                     EndBit,
 835   IN      UINT32                    Value
 836   );
 837
 838 /**
 839   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 840   writes the result back to the bit field in the 32-bit port.
 841
 842   Reads the 32-bit PCI configuration register specified by Address, performs a
 843   bitwise inclusive OR between the read result and the value specified by
 844   OrData, and writes the result to the 32-bit PCI configuration register
 845   specified by Address. The value written to the PCI configuration register is
 846   returned. This function must guarantee that all PCI read and write operations
 847   are serialized. Extra left bits in OrData are stripped.
 848
 849   If Address > 0x0FFFFFFF, then ASSERT().
 850   If Address is not aligned on a 32-bit boundary, then ASSERT().
 851   If StartBit is greater than 31, then ASSERT().
 852   If EndBit is greater than 31, then ASSERT().
 853   If EndBit is less than StartBit, then ASSERT().
 854
 855   @param  Address   PCI configuration register to write.
 856   @param  StartBit  The ordinal of the least significant bit in the bit field.
 857                     Range 0..31.
 858   @param  EndBit    The ordinal of the most significant bit in the bit field.
 859                     Range 0..31.
 860   @param  OrData    The value to OR with the PCI configuration register.
 861
 862   @return The value written back to the PCI configuration register.
 863
 864 **/
 865 UINT32
 866 EFIAPI
 867 PciBitFieldOr32 (
 868   IN      UINTN                     Address,
 869   IN      UINTN                     StartBit,
 870   IN      UINTN                     EndBit,
 871   IN      UINT32                    OrData
 872   );
 873
 874 /**
 875   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 876   AND, and writes the result back to the bit field in the 32-bit register.
 877
 878   Reads the 32-bit PCI configuration register specified by Address, performs a
 879   bitwise AND between the read result and the value specified by AndData, and
 880   writes the result to the 32-bit PCI configuration register specified by
 881   Address. The value written to the PCI configuration register is returned.
 882   This function must guarantee that all PCI read and write operations are
 883   serialized. Extra left bits in AndData are stripped.
 884
 885   If Address > 0x0FFFFFFF, then ASSERT().
 886   If Address is not aligned on a 32-bit boundary, then ASSERT().
 887   If StartBit is greater than 31, then ASSERT().
 888   If EndBit is greater than 31, then ASSERT().
 889   If EndBit is less than StartBit, then ASSERT().
 890
 891   @param  Address   PCI configuration register to write.
 892   @param  StartBit  The ordinal of the least significant bit in the bit field.
 893                     Range 0..31.
 894   @param  EndBit    The ordinal of the most significant bit in the bit field.
 895                     Range 0..31.
 896   @param  AndData   The value to AND with the PCI configuration register.
 897
 898   @return The value written back to the PCI configuration register.
 899
 900 **/
 901 UINT32
 902 EFIAPI
 903 PciBitFieldAnd32 (
 904   IN      UINTN                     Address,
 905   IN      UINTN                     StartBit,
 906   IN      UINTN                     EndBit,
 907   IN      UINT32                    AndData
 908   );
 909
 910 /**
 911   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 912   bitwise inclusive OR, and writes the result back to the bit field in the
 913   32-bit port.
 914
 915   Reads the 32-bit PCI configuration register specified by Address, performs a
 916   bitwise AND followed by a bitwise inclusive OR between the read result and
 917   the value specified by AndData, and writes the result to the 32-bit PCI
 918   configuration register specified by Address. The value written to the PCI
 919   configuration register is returned. This function must guarantee that all PCI
 920   read and write operations are serialized. Extra left bits in both AndData and
 921   OrData are stripped.
 922
 923   If Address > 0x0FFFFFFF, then ASSERT().
 924   If Address is not aligned on a 32-bit boundary, then ASSERT().
 925   If StartBit is greater than 31, then ASSERT().
 926   If EndBit is greater than 31, then ASSERT().
 927   If EndBit is less than StartBit, then ASSERT().
 928
 929   @param  Address   PCI configuration register to write.
 930   @param  StartBit  The ordinal of the least significant bit in the bit field.
 931                     Range 0..31.
 932   @param  EndBit    The ordinal of the most significant bit in the bit field.
 933                     Range 0..31.
 934   @param  AndData   The value to AND with the PCI configuration register.
 935   @param  OrData    The value to OR with the result of the AND operation.
 936
 937   @return The value written back to the PCI configuration register.
 938
 939 **/
 940 UINT32
 941 EFIAPI
 942 PciBitFieldAndThenOr32 (
 943   IN      UINTN                     Address,
 944   IN      UINTN                     StartBit,
 945   IN      UINTN                     EndBit,
 946   IN      UINT32                    AndData,
 947   IN      UINT32                    OrData
 948   );
 949
 950 /**
 951   Reads a range of PCI configuration registers into a caller supplied buffer.
 952
 953   Reads the range of PCI configuration registers specified by StartAddress and
 954   Size into the buffer specified by Buffer. This function only allows the PCI
 955   configuration registers from a single PCI function to be read. Size is
 956   returned. When possible 32-bit PCI configuration read cycles are used to read
 957   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
 958   and 16-bit PCI configuration read cycles may be used at the beginning and the
 959   end of the range.
 960
 961   If StartAddress > 0x0FFFFFFF, then ASSERT().
 962   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 963   If Size > 0 and Buffer is NULL, then ASSERT().
 964
 965   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
 966                         Function and Register.
 967   @param  Size          Size in bytes of the transfer.
 968   @param  Buffer        Pointer to a buffer receiving the data read.
 969
 970   @return Size
 971
 972 **/
 973 UINTN
 974 EFIAPI
 975 PciReadBuffer (
 976   IN      UINTN                     StartAddress,
 977   IN      UINTN                     Size,
 978   OUT     VOID                      *Buffer
 979   );
 980
 981 /**
 982   Copies the data in a caller supplied buffer to a specified range of PCI
 983   configuration space.
 984
 985   Writes the range of PCI configuration registers specified by StartAddress and
 986   Size from the buffer specified by Buffer. This function only allows the PCI
 987   configuration registers from a single PCI function to be written. Size is
 988   returned. When possible 32-bit PCI configuration write cycles are used to
 989   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
 990   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
 991   and the end of the range.
 992
 993   If StartAddress > 0x0FFFFFFF, then ASSERT().
 994   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 995   If Size > 0 and Buffer is NULL, then ASSERT().
 996
 997   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
 998                         Function and Register.
 999   @param  Size          Size in bytes of the transfer.
1000   @param  Buffer        Pointer to a buffer containing the data to write.
1001
1002   @return Size
1003
1004 **/
1005 UINTN
1006 EFIAPI
1007 PciWriteBuffer (
1008   IN      UINTN                     StartAddress,
1009   IN      UINTN                     Size,
1010   IN      VOID                      *Buffer
1011   );
1012
1013 #endif