113501034e799e93c301eefda4a1bcbe0df54754
[mirror_edk2.git] / MdePkg / Include / Library / PciSegmentLib.h
1 /** @file
2 Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
3
4 The PCI Segment Library function provide services to read, write, and modify the PCI configuration
5 registers on PCI root bridges on any supported PCI segment. These library services take a single
6 address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.
7 The layout of this address parameter is as follows:
8
9 PCI Register: Bits 0..11
10 PCI Function Bits 12..14
11 PCI Device Bits 15..19
12 PCI Bus Bits 20..27
13 Reserved Bits 28..31. Must be 0.
14 PCI Segment Bits 32..47
15 Reserved Bits 48..63. Must be 0.
16
17 | Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |
18 63 48 47 32 31 28 27 20 19 15 14 12 11 0
19
20 These functions perform PCI configuration cycles using the default PCI configuration access
21 method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
22 may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate
23 access method. Modules will typically use the PCI Segment Library for its PCI configuration
24 accesses when PCI Segments other than Segment #0 must be accessed.
25
26 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
27 This program and the accompanying materials
28 are licensed and made available under the terms and conditions of the BSD License
29 which accompanies this distribution. The full text of the license may be found at
30 http://opensource.org/licenses/bsd-license.php
31
32 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
33 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
34
35 **/
36
37 #ifndef __PCI_SEGMENT_LIB__
38 #define __PCI_SEGMENT_LIB__
39
40
41 /**
42 Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
43 and PCI Register to an address that can be passed to the PCI Segment Library functions.
44
45 Computes an address that is compatible with the PCI Segment Library functions.
46 The unused upper bits of Segment, Bus, Device, Function,
47 and Register are stripped prior to the generation of the address.
48
49 @param Segment PCI Segment number. Range 0..65535.
50 @param Bus PCI Bus number. Range 0..255.
51 @param Device PCI Device number. Range 0..31.
52 @param Function PCI Function number. Range 0..7.
53 @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.
54
55 @return The address that is compatible with the PCI Segment Library functions.
56
57 **/
58 #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \
59 ( ((Register) & 0xfff) | \
60 (((Function) & 0x07) << 12) | \
61 (((Device) & 0x1f) << 15) | \
62 (((Bus) & 0xff) << 20) | \
63 (LShiftU64((Segment) & 0xffff, 32)) \
64 )
65
66 /**
67 Register a PCI device so PCI configuration registers may be accessed after
68 SetVirtualAddressMap().
69
70 If any reserved bits in Address are set, then ASSERT().
71
72 @param Address Address that encodes the PCI Bus, Device, Function and
73 Register.
74
75 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
76 @retval RETURN_UNSUPPORTED An attempt was made to call this function
77 after ExitBootServices().
78 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
79 at runtime could not be mapped.
80 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
81 complete the registration.
82
83 **/
84 RETURN_STATUS
85 EFIAPI
86 PciSegmentRegisterForRuntimeAccess (
87 IN UINTN Address
88 );
89
90 /**
91 Reads an 8-bit PCI configuration register.
92
93 Reads and returns the 8-bit PCI configuration register specified by Address.
94 This function must guarantee that all PCI read and write operations are serialized.
95
96 If any reserved bits in Address are set, then ASSERT().
97
98 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
99
100 @return The 8-bit PCI configuration register specified by Address.
101
102 **/
103 UINT8
104 EFIAPI
105 PciSegmentRead8 (
106 IN UINT64 Address
107 );
108
109 /**
110 Writes an 8-bit PCI configuration register.
111
112 Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
113 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
114
115 If any reserved bits in Address are set, then ASSERT().
116
117 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
118 @param Value The value to write.
119
120 @return The value written to the PCI configuration register.
121
122 **/
123 UINT8
124 EFIAPI
125 PciSegmentWrite8 (
126 IN UINT64 Address,
127 IN UINT8 Value
128 );
129
130 /**
131 Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
132
133 Reads the 8-bit PCI configuration register specified by Address,
134 performs a bitwise OR between the read result and the value specified by OrData,
135 and writes the result to the 8-bit PCI configuration register specified by Address.
136 The value written to the PCI configuration register is returned.
137 This function must guarantee that all PCI read and write operations are serialized.
138
139 If any reserved bits in Address are set, then ASSERT().
140
141 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
142 @param OrData The value to OR with the PCI configuration register.
143
144 @return The value written to the PCI configuration register.
145
146 **/
147 UINT8
148 EFIAPI
149 PciSegmentOr8 (
150 IN UINT64 Address,
151 IN UINT8 OrData
152 );
153
154 /**
155 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
156
157 Reads the 8-bit PCI configuration register specified by Address,
158 performs a bitwise AND between the read result and the value specified by AndData,
159 and writes the result to the 8-bit PCI configuration register specified by Address.
160 The value written to the PCI configuration register is returned.
161 This function must guarantee that all PCI read and write operations are serialized.
162 If any reserved bits in Address are set, then ASSERT().
163
164 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
165 @param AndData The value to AND with the PCI configuration register.
166
167 @return The value written to the PCI configuration register.
168
169 **/
170 UINT8
171 EFIAPI
172 PciSegmentAnd8 (
173 IN UINT64 Address,
174 IN UINT8 AndData
175 );
176
177 /**
178 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
179 followed a bitwise OR with another 8-bit value.
180
181 Reads the 8-bit PCI configuration register specified by Address,
182 performs a bitwise AND between the read result and the value specified by AndData,
183 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
184 and writes the result to the 8-bit PCI configuration register specified by Address.
185 The value written to the PCI configuration register is returned.
186 This function must guarantee that all PCI read and write operations are serialized.
187
188 If any reserved bits in Address are set, then ASSERT().
189
190 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
191 @param AndData The value to AND with the PCI configuration register.
192 @param OrData The value to OR with the PCI configuration register.
193
194 @return The value written to the PCI configuration register.
195
196 **/
197 UINT8
198 EFIAPI
199 PciSegmentAndThenOr8 (
200 IN UINT64 Address,
201 IN UINT8 AndData,
202 IN UINT8 OrData
203 );
204
205 /**
206 Reads a bit field of a PCI configuration register.
207
208 Reads the bit field in an 8-bit PCI configuration register. The bit field is
209 specified by the StartBit and the EndBit. The value of the bit field is
210 returned.
211
212 If any reserved bits in Address are set, then ASSERT().
213 If StartBit is greater than 7, then ASSERT().
214 If EndBit is greater than 7, then ASSERT().
215 If EndBit is less than StartBit, then ASSERT().
216
217 @param Address PCI configuration register to read.
218 @param StartBit The ordinal of the least significant bit in the bit field.
219 Range 0..7.
220 @param EndBit The ordinal of the most significant bit in the bit field.
221 Range 0..7.
222
223 @return The value of the bit field read from the PCI configuration register.
224
225 **/
226 UINT8
227 EFIAPI
228 PciSegmentBitFieldRead8 (
229 IN UINT64 Address,
230 IN UINTN StartBit,
231 IN UINTN EndBit
232 );
233
234 /**
235 Writes a bit field to a PCI configuration register.
236
237 Writes Value to the bit field of the PCI configuration register. The bit
238 field is specified by the StartBit and the EndBit. All other bits in the
239 destination PCI configuration register are preserved. The new value of the
240 8-bit register is returned.
241
242 If any reserved bits in Address are set, then ASSERT().
243 If StartBit is greater than 7, then ASSERT().
244 If EndBit is greater than 7, then ASSERT().
245 If EndBit is less than StartBit, then ASSERT().
246 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
247
248 @param Address PCI configuration register to write.
249 @param StartBit The ordinal of the least significant bit in the bit field.
250 Range 0..7.
251 @param EndBit The ordinal of the most significant bit in the bit field.
252 Range 0..7.
253 @param Value New value of the bit field.
254
255 @return The value written back to the PCI configuration register.
256
257 **/
258 UINT8
259 EFIAPI
260 PciSegmentBitFieldWrite8 (
261 IN UINT64 Address,
262 IN UINTN StartBit,
263 IN UINTN EndBit,
264 IN UINT8 Value
265 );
266
267 /**
268 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
269 writes the result back to the bit field in the 8-bit port.
270
271 Reads the 8-bit PCI configuration register specified by Address, performs a
272 bitwise OR between the read result and the value specified by
273 OrData, and writes the result to the 8-bit PCI configuration register
274 specified by Address. The value written to the PCI configuration register is
275 returned. This function must guarantee that all PCI read and write operations
276 are serialized. Extra left bits in OrData are stripped.
277
278 If any reserved bits in Address are set, then ASSERT().
279 If StartBit is greater than 7, then ASSERT().
280 If EndBit is greater than 7, then ASSERT().
281 If EndBit is less than StartBit, then ASSERT().
282 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
283
284 @param Address PCI configuration register to write.
285 @param StartBit The ordinal of the least significant bit in the bit field.
286 Range 0..7.
287 @param EndBit The ordinal of the most significant bit in the bit field.
288 Range 0..7.
289 @param OrData The value to OR with the PCI configuration register.
290
291 @return The value written back to the PCI configuration register.
292
293 **/
294 UINT8
295 EFIAPI
296 PciSegmentBitFieldOr8 (
297 IN UINT64 Address,
298 IN UINTN StartBit,
299 IN UINTN EndBit,
300 IN UINT8 OrData
301 );
302
303 /**
304 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
305 AND, and writes the result back to the bit field in the 8-bit register.
306
307 Reads the 8-bit PCI configuration register specified by Address, performs a
308 bitwise AND between the read result and the value specified by AndData, and
309 writes the result to the 8-bit PCI configuration register specified by
310 Address. The value written to the PCI configuration register is returned.
311 This function must guarantee that all PCI read and write operations are
312 serialized. Extra left bits in AndData are stripped.
313
314 If any reserved bits in Address are set, then ASSERT().
315 If StartBit is greater than 7, then ASSERT().
316 If EndBit is greater than 7, then ASSERT().
317 If EndBit is less than StartBit, then ASSERT().
318 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
319
320 @param Address PCI configuration register to write.
321 @param StartBit The ordinal of the least significant bit in the bit field.
322 Range 0..7.
323 @param EndBit The ordinal of the most significant bit in the bit field.
324 Range 0..7.
325 @param AndData The value to AND with the PCI configuration register.
326
327 @return The value written back to the PCI configuration register.
328
329 **/
330 UINT8
331 EFIAPI
332 PciSegmentBitFieldAnd8 (
333 IN UINT64 Address,
334 IN UINTN StartBit,
335 IN UINTN EndBit,
336 IN UINT8 AndData
337 );
338
339 /**
340 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
341 bitwise OR, and writes the result back to the bit field in the
342 8-bit port.
343
344 Reads the 8-bit PCI configuration register specified by Address, performs a
345 bitwise AND followed by a bitwise OR between the read result and
346 the value specified by AndData, and writes the result to the 8-bit PCI
347 configuration register specified by Address. The value written to the PCI
348 configuration register is returned. This function must guarantee that all PCI
349 read and write operations are serialized. Extra left bits in both AndData and
350 OrData are stripped.
351
352 If any reserved bits in Address are set, then ASSERT().
353 If StartBit is greater than 7, then ASSERT().
354 If EndBit is greater than 7, then ASSERT().
355 If EndBit is less than StartBit, then ASSERT().
356 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
357 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
358
359 @param Address PCI configuration register to write.
360 @param StartBit The ordinal of the least significant bit in the bit field.
361 Range 0..7.
362 @param EndBit The ordinal of the most significant bit in the bit field.
363 Range 0..7.
364 @param AndData The value to AND with the PCI configuration register.
365 @param OrData The value to OR with the result of the AND operation.
366
367 @return The value written back to the PCI configuration register.
368
369 **/
370 UINT8
371 EFIAPI
372 PciSegmentBitFieldAndThenOr8 (
373 IN UINT64 Address,
374 IN UINTN StartBit,
375 IN UINTN EndBit,
376 IN UINT8 AndData,
377 IN UINT8 OrData
378 );
379
380 /**
381 Reads a 16-bit PCI configuration register.
382
383 Reads and returns the 16-bit PCI configuration register specified by Address.
384 This function must guarantee that all PCI read and write operations are serialized.
385
386 If any reserved bits in Address are set, then ASSERT().
387 If Address is not aligned on a 16-bit boundary, then ASSERT().
388
389 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
390
391 @return The 16-bit PCI configuration register specified by Address.
392
393 **/
394 UINT16
395 EFIAPI
396 PciSegmentRead16 (
397 IN UINT64 Address
398 );
399
400 /**
401 Writes a 16-bit PCI configuration register.
402
403 Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
404 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
405
406 If any reserved bits in Address are set, then ASSERT().
407 If Address is not aligned on a 16-bit boundary, then ASSERT().
408
409 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
410 @param Value The value to write.
411
412 @return The parameter of Value.
413
414 **/
415 UINT16
416 EFIAPI
417 PciSegmentWrite16 (
418 IN UINT64 Address,
419 IN UINT16 Value
420 );
421
422 /**
423 Performs a bitwise OR of a 16-bit PCI configuration register with
424 a 16-bit value.
425
426 Reads the 16-bit PCI configuration register specified by Address, performs a
427 bitwise OR between the read result and the value specified by
428 OrData, and writes the result to the 16-bit PCI configuration register
429 specified by Address. The value written to the PCI configuration register is
430 returned. This function must guarantee that all PCI read and write operations
431 are serialized.
432
433 If any reserved bits in Address are set, then ASSERT().
434 If Address is not aligned on a 16-bit boundary, then ASSERT().
435
436 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
437 Register.
438 @param OrData The value to OR with the PCI configuration register.
439
440 @return The value written back to the PCI configuration register.
441
442 **/
443 UINT16
444 EFIAPI
445 PciSegmentOr16 (
446 IN UINT64 Address,
447 IN UINT16 OrData
448 );
449
450 /**
451 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
452
453 Reads the 16-bit PCI configuration register specified by Address,
454 performs a bitwise AND between the read result and the value specified by AndData,
455 and writes the result to the 16-bit PCI configuration register specified by Address.
456 The value written to the PCI configuration register is returned.
457 This function must guarantee that all PCI read and write operations are serialized.
458
459 If any reserved bits in Address are set, then ASSERT().
460 If Address is not aligned on a 16-bit boundary, then ASSERT().
461
462 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
463 @param AndData The value to AND with the PCI configuration register.
464
465 @return The value written to the PCI configuration register.
466
467 **/
468 UINT16
469 EFIAPI
470 PciSegmentAnd16 (
471 IN UINT64 Address,
472 IN UINT16 AndData
473 );
474
475 /**
476 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
477 followed a bitwise OR with another 16-bit value.
478
479 Reads the 16-bit PCI configuration register specified by Address,
480 performs a bitwise AND between the read result and the value specified by AndData,
481 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
482 and writes the result to the 16-bit PCI configuration register specified by Address.
483 The value written to the PCI configuration register is returned.
484 This function must guarantee that all PCI read and write operations are serialized.
485
486 If any reserved bits in Address are set, then ASSERT().
487 If Address is not aligned on a 16-bit boundary, then ASSERT().
488
489 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
490 @param AndData The value to AND with the PCI configuration register.
491 @param OrData The value to OR with the PCI configuration register.
492
493 @return The value written to the PCI configuration register.
494
495 **/
496 UINT16
497 EFIAPI
498 PciSegmentAndThenOr16 (
499 IN UINT64 Address,
500 IN UINT16 AndData,
501 IN UINT16 OrData
502 );
503
504 /**
505 Reads a bit field of a PCI configuration register.
506
507 Reads the bit field in a 16-bit PCI configuration register. The bit field is
508 specified by the StartBit and the EndBit. The value of the bit field is
509 returned.
510
511 If any reserved bits in Address are set, then ASSERT().
512 If Address is not aligned on a 16-bit boundary, then ASSERT().
513 If StartBit is greater than 15, then ASSERT().
514 If EndBit is greater than 15, then ASSERT().
515 If EndBit is less than StartBit, then ASSERT().
516
517 @param Address PCI configuration register to read.
518 @param StartBit The ordinal of the least significant bit in the bit field.
519 Range 0..15.
520 @param EndBit The ordinal of the most significant bit in the bit field.
521 Range 0..15.
522
523 @return The value of the bit field read from the PCI configuration register.
524
525 **/
526 UINT16
527 EFIAPI
528 PciSegmentBitFieldRead16 (
529 IN UINT64 Address,
530 IN UINTN StartBit,
531 IN UINTN EndBit
532 );
533
534 /**
535 Writes a bit field to a PCI configuration register.
536
537 Writes Value to the bit field of the PCI configuration register. The bit
538 field is specified by the StartBit and the EndBit. All other bits in the
539 destination PCI configuration register are preserved. The new value of the
540 16-bit register is returned.
541
542 If any reserved bits in Address are set, then ASSERT().
543 If Address is not aligned on a 16-bit boundary, then ASSERT().
544 If StartBit is greater than 15, then ASSERT().
545 If EndBit is greater than 15, then ASSERT().
546 If EndBit is less than StartBit, then ASSERT().
547 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
548
549 @param Address PCI configuration register to write.
550 @param StartBit The ordinal of the least significant bit in the bit field.
551 Range 0..15.
552 @param EndBit The ordinal of the most significant bit in the bit field.
553 Range 0..15.
554 @param Value New value of the bit field.
555
556 @return The value written back to the PCI configuration register.
557
558 **/
559 UINT16
560 EFIAPI
561 PciSegmentBitFieldWrite16 (
562 IN UINT64 Address,
563 IN UINTN StartBit,
564 IN UINTN EndBit,
565 IN UINT16 Value
566 );
567
568 /**
569 Reads the 16-bit PCI configuration register specified by Address,
570 performs a bitwise OR between the read result and the value specified by OrData,
571 and writes the result to the 16-bit PCI configuration register specified by Address.
572
573 If any reserved bits in Address are set, then ASSERT().
574 If Address is not aligned on a 16-bit boundary, then ASSERT().
575 If StartBit is greater than 15, then ASSERT().
576 If EndBit is greater than 15, then ASSERT().
577 If EndBit is less than StartBit, then ASSERT().
578 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
579
580 @param Address PCI configuration register to write.
581 @param StartBit The ordinal of the least significant bit in the bit field.
582 Range 0..15.
583 @param EndBit The ordinal of the most significant bit in the bit field.
584 Range 0..15.
585 @param OrData The value to OR with the PCI configuration register.
586
587 @return The value written back to the PCI configuration register.
588
589 **/
590 UINT16
591 EFIAPI
592 PciSegmentBitFieldOr16 (
593 IN UINT64 Address,
594 IN UINTN StartBit,
595 IN UINTN EndBit,
596 IN UINT16 OrData
597 );
598
599 /**
600 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
601 and writes the result back to the bit field in the 16-bit port.
602
603 Reads the 16-bit PCI configuration register specified by Address,
604 performs a bitwise OR between the read result and the value specified by OrData,
605 and writes the result to the 16-bit PCI configuration register specified by Address.
606 The value written to the PCI configuration register is returned.
607 This function must guarantee that all PCI read and write operations are serialized.
608 Extra left bits in OrData are stripped.
609
610 If any reserved bits in Address are set, then ASSERT().
611 If Address is not aligned on a 16-bit boundary, then ASSERT().
612 If StartBit is greater than 7, then ASSERT().
613 If EndBit is greater than 7, then ASSERT().
614 If EndBit is less than StartBit, then ASSERT().
615 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
616
617 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
618 @param StartBit The ordinal of the least significant bit in the bit field.
619 The ordinal of the least significant bit in a byte is bit 0.
620 @param EndBit The ordinal of the most significant bit in the bit field.
621 The ordinal of the most significant bit in a byte is bit 7.
622 @param AndData The value to AND with the read value from the PCI configuration register.
623
624 @return The value written to the PCI configuration register.
625
626 **/
627 UINT16
628 EFIAPI
629 PciSegmentBitFieldAnd16 (
630 IN UINT64 Address,
631 IN UINTN StartBit,
632 IN UINTN EndBit,
633 IN UINT16 AndData
634 );
635
636 /**
637 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
638 bitwise OR, and writes the result back to the bit field in the
639 16-bit port.
640
641 Reads the 16-bit PCI configuration register specified by Address, performs a
642 bitwise AND followed by a bitwise OR between the read result and
643 the value specified by AndData, and writes the result to the 16-bit PCI
644 configuration register specified by Address. The value written to the PCI
645 configuration register is returned. This function must guarantee that all PCI
646 read and write operations are serialized. Extra left bits in both AndData and
647 OrData are stripped.
648
649 If any reserved bits in Address are set, then ASSERT().
650 If StartBit is greater than 15, then ASSERT().
651 If EndBit is greater than 15, then ASSERT().
652 If EndBit is less than StartBit, then ASSERT().
653 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
654 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
655
656 @param Address PCI configuration register to write.
657 @param StartBit The ordinal of the least significant bit in the bit field.
658 Range 0..15.
659 @param EndBit The ordinal of the most significant bit in the bit field.
660 Range 0..15.
661 @param AndData The value to AND with the PCI configuration register.
662 @param OrData The value to OR with the result of the AND operation.
663
664 @return The value written back to the PCI configuration register.
665
666 **/
667 UINT16
668 EFIAPI
669 PciSegmentBitFieldAndThenOr16 (
670 IN UINT64 Address,
671 IN UINTN StartBit,
672 IN UINTN EndBit,
673 IN UINT16 AndData,
674 IN UINT16 OrData
675 );
676
677 /**
678 Reads a 32-bit PCI configuration register.
679
680 Reads and returns the 32-bit PCI configuration register specified by Address.
681 This function must guarantee that all PCI read and write operations are serialized.
682
683 If any reserved bits in Address are set, then ASSERT().
684 If Address is not aligned on a 32-bit boundary, then ASSERT().
685
686 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
687
688 @return The 32-bit PCI configuration register specified by Address.
689
690 **/
691 UINT32
692 EFIAPI
693 PciSegmentRead32 (
694 IN UINT64 Address
695 );
696
697 /**
698 Writes a 32-bit PCI configuration register.
699
700 Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
701 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
702
703 If any reserved bits in Address are set, then ASSERT().
704 If Address is not aligned on a 32-bit boundary, then ASSERT().
705
706 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
707 @param Value The value to write.
708
709 @return The parameter of Value.
710
711 **/
712 UINT32
713 EFIAPI
714 PciSegmentWrite32 (
715 IN UINT64 Address,
716 IN UINT32 Value
717 );
718
719 /**
720 Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
721
722 Reads the 32-bit PCI configuration register specified by Address,
723 performs a bitwise OR between the read result and the value specified by OrData,
724 and writes the result to the 32-bit PCI configuration register specified by Address.
725 The value written to the PCI configuration register is returned.
726 This function must guarantee that all PCI read and write operations are serialized.
727
728 If any reserved bits in Address are set, then ASSERT().
729 If Address is not aligned on a 32-bit boundary, then ASSERT().
730
731 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
732 @param OrData The value to OR with the PCI configuration register.
733
734 @return The value written to the PCI configuration register.
735
736 **/
737 UINT32
738 EFIAPI
739 PciSegmentOr32 (
740 IN UINT64 Address,
741 IN UINT32 OrData
742 );
743
744 /**
745 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
746
747 Reads the 32-bit PCI configuration register specified by Address,
748 performs a bitwise AND between the read result and the value specified by AndData,
749 and writes the result to the 32-bit PCI configuration register specified by Address.
750 The value written to the PCI configuration register is returned.
751 This function must guarantee that all PCI read and write operations are serialized.
752
753 If any reserved bits in Address are set, then ASSERT().
754 If Address is not aligned on a 32-bit boundary, then ASSERT().
755
756 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
757 @param AndData The value to AND with the PCI configuration register.
758
759 @return The value written to the PCI configuration register.
760
761 **/
762 UINT32
763 EFIAPI
764 PciSegmentAnd32 (
765 IN UINT64 Address,
766 IN UINT32 AndData
767 );
768
769 /**
770 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
771 followed a bitwise OR with another 32-bit value.
772
773 Reads the 32-bit PCI configuration register specified by Address,
774 performs a bitwise AND between the read result and the value specified by AndData,
775 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
776 and writes the result to the 32-bit PCI configuration register specified by Address.
777 The value written to the PCI configuration register is returned.
778 This function must guarantee that all PCI read and write operations are serialized.
779
780 If any reserved bits in Address are set, then ASSERT().
781 If Address is not aligned on a 32-bit boundary, then ASSERT().
782
783 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
784 @param AndData The value to AND with the PCI configuration register.
785 @param OrData The value to OR with the PCI configuration register.
786
787 @return The value written to the PCI configuration register.
788
789 **/
790 UINT32
791 EFIAPI
792 PciSegmentAndThenOr32 (
793 IN UINT64 Address,
794 IN UINT32 AndData,
795 IN UINT32 OrData
796 );
797
798 /**
799 Reads a bit field of a PCI configuration register.
800
801 Reads the bit field in a 32-bit PCI configuration register. The bit field is
802 specified by the StartBit and the EndBit. The value of the bit field is
803 returned.
804
805 If any reserved bits in Address are set, then ASSERT().
806 If Address is not aligned on a 32-bit boundary, then ASSERT().
807 If StartBit is greater than 31, then ASSERT().
808 If EndBit is greater than 31, then ASSERT().
809 If EndBit is less than StartBit, then ASSERT().
810
811 @param Address PCI configuration register to read.
812 @param StartBit The ordinal of the least significant bit in the bit field.
813 Range 0..31.
814 @param EndBit The ordinal of the most significant bit in the bit field.
815 Range 0..31.
816
817 @return The value of the bit field read from the PCI configuration register.
818
819 **/
820 UINT32
821 EFIAPI
822 PciSegmentBitFieldRead32 (
823 IN UINT64 Address,
824 IN UINTN StartBit,
825 IN UINTN EndBit
826 );
827
828 /**
829 Writes a bit field to a PCI configuration register.
830
831 Writes Value to the bit field of the PCI configuration register. The bit
832 field is specified by the StartBit and the EndBit. All other bits in the
833 destination PCI configuration register are preserved. The new value of the
834 32-bit register is returned.
835
836 If any reserved bits in Address are set, then ASSERT().
837 If Address is not aligned on a 32-bit boundary, then ASSERT().
838 If StartBit is greater than 31, then ASSERT().
839 If EndBit is greater than 31, then ASSERT().
840 If EndBit is less than StartBit, then ASSERT().
841 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
842
843 @param Address PCI configuration register to write.
844 @param StartBit The ordinal of the least significant bit in the bit field.
845 Range 0..31.
846 @param EndBit The ordinal of the most significant bit in the bit field.
847 Range 0..31.
848 @param Value New value of the bit field.
849
850 @return The value written back to the PCI configuration register.
851
852 **/
853 UINT32
854 EFIAPI
855 PciSegmentBitFieldWrite32 (
856 IN UINT64 Address,
857 IN UINTN StartBit,
858 IN UINTN EndBit,
859 IN UINT32 Value
860 );
861
862 /**
863 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
864 writes the result back to the bit field in the 32-bit port.
865
866 Reads the 32-bit PCI configuration register specified by Address, performs a
867 bitwise OR between the read result and the value specified by
868 OrData, and writes the result to the 32-bit PCI configuration register
869 specified by Address. The value written to the PCI configuration register is
870 returned. This function must guarantee that all PCI read and write operations
871 are serialized. Extra left bits in OrData are stripped.
872
873 If any reserved bits in Address are set, then ASSERT().
874 If StartBit is greater than 31, then ASSERT().
875 If EndBit is greater than 31, then ASSERT().
876 If EndBit is less than StartBit, then ASSERT().
877 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
878
879 @param Address PCI configuration register to write.
880 @param StartBit The ordinal of the least significant bit in the bit field.
881 Range 0..31.
882 @param EndBit The ordinal of the most significant bit in the bit field.
883 Range 0..31.
884 @param OrData The value to OR with the PCI configuration register.
885
886 @return The value written back to the PCI configuration register.
887
888 **/
889 UINT32
890 EFIAPI
891 PciSegmentBitFieldOr32 (
892 IN UINT64 Address,
893 IN UINTN StartBit,
894 IN UINTN EndBit,
895 IN UINT32 OrData
896 );
897
898 /**
899 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
900 AND, and writes the result back to the bit field in the 32-bit register.
901
902
903 Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
904 AND between the read result and the value specified by AndData, and writes the result
905 to the 32-bit PCI configuration register specified by Address. The value written to
906 the PCI configuration register is returned. This function must guarantee that all PCI
907 read and write operations are serialized. Extra left bits in AndData are stripped.
908 If any reserved bits in Address are set, then ASSERT().
909 If Address is not aligned on a 32-bit boundary, then ASSERT().
910 If StartBit is greater than 31, then ASSERT().
911 If EndBit is greater than 31, then ASSERT().
912 If EndBit is less than StartBit, then ASSERT().
913 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
914
915 @param Address PCI configuration register to write.
916 @param StartBit The ordinal of the least significant bit in the bit field.
917 Range 0..31.
918 @param EndBit The ordinal of the most significant bit in the bit field.
919 Range 0..31.
920 @param AndData The value to AND with the PCI configuration register.
921
922 @return The value written back to the PCI configuration register.
923
924 **/
925 UINT32
926 EFIAPI
927 PciSegmentBitFieldAnd32 (
928 IN UINT64 Address,
929 IN UINTN StartBit,
930 IN UINTN EndBit,
931 IN UINT32 AndData
932 );
933
934 /**
935 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
936 bitwise OR, and writes the result back to the bit field in the
937 32-bit port.
938
939 Reads the 32-bit PCI configuration register specified by Address, performs a
940 bitwise AND followed by a bitwise OR between the read result and
941 the value specified by AndData, and writes the result to the 32-bit PCI
942 configuration register specified by Address. The value written to the PCI
943 configuration register is returned. This function must guarantee that all PCI
944 read and write operations are serialized. Extra left bits in both AndData and
945 OrData are stripped.
946
947 If any reserved bits in Address are set, then ASSERT().
948 If StartBit is greater than 31, then ASSERT().
949 If EndBit is greater than 31, then ASSERT().
950 If EndBit is less than StartBit, then ASSERT().
951 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
952 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
953
954 @param Address PCI configuration register to write.
955 @param StartBit The ordinal of the least significant bit in the bit field.
956 Range 0..31.
957 @param EndBit The ordinal of the most significant bit in the bit field.
958 Range 0..31.
959 @param AndData The value to AND with the PCI configuration register.
960 @param OrData The value to OR with the result of the AND operation.
961
962 @return The value written back to the PCI configuration register.
963
964 **/
965 UINT32
966 EFIAPI
967 PciSegmentBitFieldAndThenOr32 (
968 IN UINT64 Address,
969 IN UINTN StartBit,
970 IN UINTN EndBit,
971 IN UINT32 AndData,
972 IN UINT32 OrData
973 );
974
975 /**
976 Reads a range of PCI configuration registers into a caller supplied buffer.
977
978 Reads the range of PCI configuration registers specified by StartAddress and
979 Size into the buffer specified by Buffer. This function only allows the PCI
980 configuration registers from a single PCI function to be read. Size is
981 returned. When possible 32-bit PCI configuration read cycles are used to read
982 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
983 and 16-bit PCI configuration read cycles may be used at the beginning and the
984 end of the range.
985
986 If any reserved bits in StartAddress are set, then ASSERT().
987 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
988 If Size > 0 and Buffer is NULL, then ASSERT().
989
990 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
991 Function and Register.
992 @param Size Size in bytes of the transfer.
993 @param Buffer Pointer to a buffer receiving the data read.
994
995 @return Size
996
997 **/
998 UINTN
999 EFIAPI
1000 PciSegmentReadBuffer (
1001 IN UINT64 StartAddress,
1002 IN UINTN Size,
1003 OUT VOID *Buffer
1004 );
1005
1006 /**
1007 Copies the data in a caller supplied buffer to a specified range of PCI
1008 configuration space.
1009
1010 Writes the range of PCI configuration registers specified by StartAddress and
1011 Size from the buffer specified by Buffer. This function only allows the PCI
1012 configuration registers from a single PCI function to be written. Size is
1013 returned. When possible 32-bit PCI configuration write cycles are used to
1014 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1015 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1016 and the end of the range.
1017
1018 If any reserved bits in StartAddress are set, then ASSERT().
1019 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1020 If Size > 0 and Buffer is NULL, then ASSERT().
1021
1022 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
1023 Function and Register.
1024 @param Size Size in bytes of the transfer.
1025 @param Buffer Pointer to a buffer containing the data to write.
1026
1027 @return The parameter of Size.
1028
1029 **/
1030 UINTN
1031 EFIAPI
1032 PciSegmentWriteBuffer (
1033 IN UINT64 StartAddress,
1034 IN UINTN Size,
1035 IN VOID *Buffer
1036 );
1037
1038 #endif