MdePkg/PciSegmentLib: Optimize PCI_SEGMENT_LIB_ADDRESS()
[mirror_edk2.git] / MdePkg / Include / Library / PciSegmentLib.h
1 /** @file
2 Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
3
4 The PCI Segment Library function provide services to read, write, and modify the PCI configuration
5 registers on PCI root bridges on any supported PCI segment. These library services take a single
6 address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.
7 The layout of this address parameter is as follows:
8
9 PCI Register: Bits 0..11
10 PCI Function Bits 12..14
11 PCI Device Bits 15..19
12 PCI Bus Bits 20..27
13 Reserved Bits 28..31. Must be 0.
14 PCI Segment Bits 32..47
15 Reserved Bits 48..63. Must be 0.
16
17 | Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |
18 63 48 47 32 31 28 27 20 19 15 14 12 11 0
19
20 These functions perform PCI configuration cycles using the default PCI configuration access
21 method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
22 may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate
23 access method. Modules will typically use the PCI Segment Library for its PCI configuration
24 accesses when PCI Segments other than Segment #0 must be accessed.
25
26 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
27 This program and the accompanying materials
28 are licensed and made available under the terms and conditions of the BSD License
29 which accompanies this distribution. The full text of the license may be found at
30 http://opensource.org/licenses/bsd-license.php
31
32 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
33 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
34
35 **/
36
37 #ifndef __PCI_SEGMENT_LIB__
38 #define __PCI_SEGMENT_LIB__
39
40
41 /**
42 Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
43 and PCI Register to an address that can be passed to the PCI Segment Library functions.
44
45 Computes an address that is compatible with the PCI Segment Library functions.
46 The unused upper bits of Segment, Bus, Device, Function,
47 and Register are stripped prior to the generation of the address.
48
49 @param Segment PCI Segment number. Range 0..65535.
50 @param Bus PCI Bus number. Range 0..255.
51 @param Device PCI Device number. Range 0..31.
52 @param Function PCI Function number. Range 0..7.
53 @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.
54
55 @return The address that is compatible with the PCI Segment Library functions.
56
57 **/
58 #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \
59 ((Segment != 0) ? \
60 ( ((Register) & 0xfff) | \
61 (((Function) & 0x07) << 12) | \
62 (((Device) & 0x1f) << 15) | \
63 (((Bus) & 0xff) << 20) | \
64 (LShiftU64 ((Segment) & 0xffff, 32)) \
65 ) : \
66 ( ((Register) & 0xfff) | \
67 (((Function) & 0x07) << 12) | \
68 (((Device) & 0x1f) << 15) | \
69 (((Bus) & 0xff) << 20) \
70 ) \
71 )
72
73 /**
74 Register a PCI device so PCI configuration registers may be accessed after
75 SetVirtualAddressMap().
76
77 If any reserved bits in Address are set, then ASSERT().
78
79 @param Address Address that encodes the PCI Bus, Device, Function and
80 Register.
81
82 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
83 @retval RETURN_UNSUPPORTED An attempt was made to call this function
84 after ExitBootServices().
85 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
86 at runtime could not be mapped.
87 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
88 complete the registration.
89
90 **/
91 RETURN_STATUS
92 EFIAPI
93 PciSegmentRegisterForRuntimeAccess (
94 IN UINTN Address
95 );
96
97 /**
98 Reads an 8-bit PCI configuration register.
99
100 Reads and returns the 8-bit PCI configuration register specified by Address.
101 This function must guarantee that all PCI read and write operations are serialized.
102
103 If any reserved bits in Address are set, then ASSERT().
104
105 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
106
107 @return The 8-bit PCI configuration register specified by Address.
108
109 **/
110 UINT8
111 EFIAPI
112 PciSegmentRead8 (
113 IN UINT64 Address
114 );
115
116 /**
117 Writes an 8-bit PCI configuration register.
118
119 Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
120 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
121
122 If any reserved bits in Address are set, then ASSERT().
123
124 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
125 @param Value The value to write.
126
127 @return The value written to the PCI configuration register.
128
129 **/
130 UINT8
131 EFIAPI
132 PciSegmentWrite8 (
133 IN UINT64 Address,
134 IN UINT8 Value
135 );
136
137 /**
138 Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
139
140 Reads the 8-bit PCI configuration register specified by Address,
141 performs a bitwise OR between the read result and the value specified by OrData,
142 and writes the result to the 8-bit PCI configuration register specified by Address.
143 The value written to the PCI configuration register is returned.
144 This function must guarantee that all PCI read and write operations are serialized.
145
146 If any reserved bits in Address are set, then ASSERT().
147
148 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
149 @param OrData The value to OR with the PCI configuration register.
150
151 @return The value written to the PCI configuration register.
152
153 **/
154 UINT8
155 EFIAPI
156 PciSegmentOr8 (
157 IN UINT64 Address,
158 IN UINT8 OrData
159 );
160
161 /**
162 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
163
164 Reads the 8-bit PCI configuration register specified by Address,
165 performs a bitwise AND between the read result and the value specified by AndData,
166 and writes the result to the 8-bit PCI configuration register specified by Address.
167 The value written to the PCI configuration register is returned.
168 This function must guarantee that all PCI read and write operations are serialized.
169 If any reserved bits in Address are set, then ASSERT().
170
171 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
172 @param AndData The value to AND with the PCI configuration register.
173
174 @return The value written to the PCI configuration register.
175
176 **/
177 UINT8
178 EFIAPI
179 PciSegmentAnd8 (
180 IN UINT64 Address,
181 IN UINT8 AndData
182 );
183
184 /**
185 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
186 followed a bitwise OR with another 8-bit value.
187
188 Reads the 8-bit PCI configuration register specified by Address,
189 performs a bitwise AND between the read result and the value specified by AndData,
190 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
191 and writes the result to the 8-bit PCI configuration register specified by Address.
192 The value written to the PCI configuration register is returned.
193 This function must guarantee that all PCI read and write operations are serialized.
194
195 If any reserved bits in Address are set, then ASSERT().
196
197 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
198 @param AndData The value to AND with the PCI configuration register.
199 @param OrData The value to OR with the PCI configuration register.
200
201 @return The value written to the PCI configuration register.
202
203 **/
204 UINT8
205 EFIAPI
206 PciSegmentAndThenOr8 (
207 IN UINT64 Address,
208 IN UINT8 AndData,
209 IN UINT8 OrData
210 );
211
212 /**
213 Reads a bit field of a PCI configuration register.
214
215 Reads the bit field in an 8-bit PCI configuration register. The bit field is
216 specified by the StartBit and the EndBit. The value of the bit field is
217 returned.
218
219 If any reserved bits in Address are set, then ASSERT().
220 If StartBit is greater than 7, then ASSERT().
221 If EndBit is greater than 7, then ASSERT().
222 If EndBit is less than StartBit, then ASSERT().
223
224 @param Address PCI configuration register to read.
225 @param StartBit The ordinal of the least significant bit in the bit field.
226 Range 0..7.
227 @param EndBit The ordinal of the most significant bit in the bit field.
228 Range 0..7.
229
230 @return The value of the bit field read from the PCI configuration register.
231
232 **/
233 UINT8
234 EFIAPI
235 PciSegmentBitFieldRead8 (
236 IN UINT64 Address,
237 IN UINTN StartBit,
238 IN UINTN EndBit
239 );
240
241 /**
242 Writes a bit field to a PCI configuration register.
243
244 Writes Value to the bit field of the PCI configuration register. The bit
245 field is specified by the StartBit and the EndBit. All other bits in the
246 destination PCI configuration register are preserved. The new value of the
247 8-bit register is returned.
248
249 If any reserved bits in Address are set, then ASSERT().
250 If StartBit is greater than 7, then ASSERT().
251 If EndBit is greater than 7, then ASSERT().
252 If EndBit is less than StartBit, then ASSERT().
253 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
254
255 @param Address PCI configuration register to write.
256 @param StartBit The ordinal of the least significant bit in the bit field.
257 Range 0..7.
258 @param EndBit The ordinal of the most significant bit in the bit field.
259 Range 0..7.
260 @param Value New value of the bit field.
261
262 @return The value written back to the PCI configuration register.
263
264 **/
265 UINT8
266 EFIAPI
267 PciSegmentBitFieldWrite8 (
268 IN UINT64 Address,
269 IN UINTN StartBit,
270 IN UINTN EndBit,
271 IN UINT8 Value
272 );
273
274 /**
275 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
276 writes the result back to the bit field in the 8-bit port.
277
278 Reads the 8-bit PCI configuration register specified by Address, performs a
279 bitwise OR between the read result and the value specified by
280 OrData, and writes the result to the 8-bit PCI configuration register
281 specified by Address. The value written to the PCI configuration register is
282 returned. This function must guarantee that all PCI read and write operations
283 are serialized. Extra left bits in OrData are stripped.
284
285 If any reserved bits in Address are set, then ASSERT().
286 If StartBit is greater than 7, then ASSERT().
287 If EndBit is greater than 7, then ASSERT().
288 If EndBit is less than StartBit, then ASSERT().
289 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
290
291 @param Address PCI configuration register to write.
292 @param StartBit The ordinal of the least significant bit in the bit field.
293 Range 0..7.
294 @param EndBit The ordinal of the most significant bit in the bit field.
295 Range 0..7.
296 @param OrData The value to OR with the PCI configuration register.
297
298 @return The value written back to the PCI configuration register.
299
300 **/
301 UINT8
302 EFIAPI
303 PciSegmentBitFieldOr8 (
304 IN UINT64 Address,
305 IN UINTN StartBit,
306 IN UINTN EndBit,
307 IN UINT8 OrData
308 );
309
310 /**
311 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
312 AND, and writes the result back to the bit field in the 8-bit register.
313
314 Reads the 8-bit PCI configuration register specified by Address, performs a
315 bitwise AND between the read result and the value specified by AndData, and
316 writes the result to the 8-bit PCI configuration register specified by
317 Address. The value written to the PCI configuration register is returned.
318 This function must guarantee that all PCI read and write operations are
319 serialized. Extra left bits in AndData are stripped.
320
321 If any reserved bits in Address are set, then ASSERT().
322 If StartBit is greater than 7, then ASSERT().
323 If EndBit is greater than 7, then ASSERT().
324 If EndBit is less than StartBit, then ASSERT().
325 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
326
327 @param Address PCI configuration register to write.
328 @param StartBit The ordinal of the least significant bit in the bit field.
329 Range 0..7.
330 @param EndBit The ordinal of the most significant bit in the bit field.
331 Range 0..7.
332 @param AndData The value to AND with the PCI configuration register.
333
334 @return The value written back to the PCI configuration register.
335
336 **/
337 UINT8
338 EFIAPI
339 PciSegmentBitFieldAnd8 (
340 IN UINT64 Address,
341 IN UINTN StartBit,
342 IN UINTN EndBit,
343 IN UINT8 AndData
344 );
345
346 /**
347 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
348 bitwise OR, and writes the result back to the bit field in the
349 8-bit port.
350
351 Reads the 8-bit PCI configuration register specified by Address, performs a
352 bitwise AND followed by a bitwise OR between the read result and
353 the value specified by AndData, and writes the result to the 8-bit PCI
354 configuration register specified by Address. The value written to the PCI
355 configuration register is returned. This function must guarantee that all PCI
356 read and write operations are serialized. Extra left bits in both AndData and
357 OrData are stripped.
358
359 If any reserved bits in Address are set, then ASSERT().
360 If StartBit is greater than 7, then ASSERT().
361 If EndBit is greater than 7, then ASSERT().
362 If EndBit is less than StartBit, then ASSERT().
363 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
364 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
365
366 @param Address PCI configuration register to write.
367 @param StartBit The ordinal of the least significant bit in the bit field.
368 Range 0..7.
369 @param EndBit The ordinal of the most significant bit in the bit field.
370 Range 0..7.
371 @param AndData The value to AND with the PCI configuration register.
372 @param OrData The value to OR with the result of the AND operation.
373
374 @return The value written back to the PCI configuration register.
375
376 **/
377 UINT8
378 EFIAPI
379 PciSegmentBitFieldAndThenOr8 (
380 IN UINT64 Address,
381 IN UINTN StartBit,
382 IN UINTN EndBit,
383 IN UINT8 AndData,
384 IN UINT8 OrData
385 );
386
387 /**
388 Reads a 16-bit PCI configuration register.
389
390 Reads and returns the 16-bit PCI configuration register specified by Address.
391 This function must guarantee that all PCI read and write operations are serialized.
392
393 If any reserved bits in Address are set, then ASSERT().
394 If Address is not aligned on a 16-bit boundary, then ASSERT().
395
396 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
397
398 @return The 16-bit PCI configuration register specified by Address.
399
400 **/
401 UINT16
402 EFIAPI
403 PciSegmentRead16 (
404 IN UINT64 Address
405 );
406
407 /**
408 Writes a 16-bit PCI configuration register.
409
410 Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
411 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
412
413 If any reserved bits in Address are set, then ASSERT().
414 If Address is not aligned on a 16-bit boundary, then ASSERT().
415
416 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
417 @param Value The value to write.
418
419 @return The parameter of Value.
420
421 **/
422 UINT16
423 EFIAPI
424 PciSegmentWrite16 (
425 IN UINT64 Address,
426 IN UINT16 Value
427 );
428
429 /**
430 Performs a bitwise OR of a 16-bit PCI configuration register with
431 a 16-bit value.
432
433 Reads the 16-bit PCI configuration register specified by Address, performs a
434 bitwise OR between the read result and the value specified by
435 OrData, and writes the result to the 16-bit PCI configuration register
436 specified by Address. The value written to the PCI configuration register is
437 returned. This function must guarantee that all PCI read and write operations
438 are serialized.
439
440 If any reserved bits in Address are set, then ASSERT().
441 If Address is not aligned on a 16-bit boundary, then ASSERT().
442
443 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
444 Register.
445 @param OrData The value to OR with the PCI configuration register.
446
447 @return The value written back to the PCI configuration register.
448
449 **/
450 UINT16
451 EFIAPI
452 PciSegmentOr16 (
453 IN UINT64 Address,
454 IN UINT16 OrData
455 );
456
457 /**
458 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
459
460 Reads the 16-bit PCI configuration register specified by Address,
461 performs a bitwise AND between the read result and the value specified by AndData,
462 and writes the result to the 16-bit PCI configuration register specified by Address.
463 The value written to the PCI configuration register is returned.
464 This function must guarantee that all PCI read and write operations are serialized.
465
466 If any reserved bits in Address are set, then ASSERT().
467 If Address is not aligned on a 16-bit boundary, then ASSERT().
468
469 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
470 @param AndData The value to AND with the PCI configuration register.
471
472 @return The value written to the PCI configuration register.
473
474 **/
475 UINT16
476 EFIAPI
477 PciSegmentAnd16 (
478 IN UINT64 Address,
479 IN UINT16 AndData
480 );
481
482 /**
483 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
484 followed a bitwise OR with another 16-bit value.
485
486 Reads the 16-bit PCI configuration register specified by Address,
487 performs a bitwise AND between the read result and the value specified by AndData,
488 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
489 and writes the result to the 16-bit PCI configuration register specified by Address.
490 The value written to the PCI configuration register is returned.
491 This function must guarantee that all PCI read and write operations are serialized.
492
493 If any reserved bits in Address are set, then ASSERT().
494 If Address is not aligned on a 16-bit boundary, then ASSERT().
495
496 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
497 @param AndData The value to AND with the PCI configuration register.
498 @param OrData The value to OR with the PCI configuration register.
499
500 @return The value written to the PCI configuration register.
501
502 **/
503 UINT16
504 EFIAPI
505 PciSegmentAndThenOr16 (
506 IN UINT64 Address,
507 IN UINT16 AndData,
508 IN UINT16 OrData
509 );
510
511 /**
512 Reads a bit field of a PCI configuration register.
513
514 Reads the bit field in a 16-bit PCI configuration register. The bit field is
515 specified by the StartBit and the EndBit. The value of the bit field is
516 returned.
517
518 If any reserved bits in Address are set, then ASSERT().
519 If Address is not aligned on a 16-bit boundary, then ASSERT().
520 If StartBit is greater than 15, then ASSERT().
521 If EndBit is greater than 15, then ASSERT().
522 If EndBit is less than StartBit, then ASSERT().
523
524 @param Address PCI configuration register to read.
525 @param StartBit The ordinal of the least significant bit in the bit field.
526 Range 0..15.
527 @param EndBit The ordinal of the most significant bit in the bit field.
528 Range 0..15.
529
530 @return The value of the bit field read from the PCI configuration register.
531
532 **/
533 UINT16
534 EFIAPI
535 PciSegmentBitFieldRead16 (
536 IN UINT64 Address,
537 IN UINTN StartBit,
538 IN UINTN EndBit
539 );
540
541 /**
542 Writes a bit field to a PCI configuration register.
543
544 Writes Value to the bit field of the PCI configuration register. The bit
545 field is specified by the StartBit and the EndBit. All other bits in the
546 destination PCI configuration register are preserved. The new value of the
547 16-bit register is returned.
548
549 If any reserved bits in Address are set, then ASSERT().
550 If Address is not aligned on a 16-bit boundary, then ASSERT().
551 If StartBit is greater than 15, then ASSERT().
552 If EndBit is greater than 15, then ASSERT().
553 If EndBit is less than StartBit, then ASSERT().
554 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
555
556 @param Address PCI configuration register to write.
557 @param StartBit The ordinal of the least significant bit in the bit field.
558 Range 0..15.
559 @param EndBit The ordinal of the most significant bit in the bit field.
560 Range 0..15.
561 @param Value New value of the bit field.
562
563 @return The value written back to the PCI configuration register.
564
565 **/
566 UINT16
567 EFIAPI
568 PciSegmentBitFieldWrite16 (
569 IN UINT64 Address,
570 IN UINTN StartBit,
571 IN UINTN EndBit,
572 IN UINT16 Value
573 );
574
575 /**
576 Reads the 16-bit PCI configuration register specified by Address,
577 performs a bitwise OR between the read result and the value specified by OrData,
578 and writes the result to the 16-bit PCI configuration register specified by Address.
579
580 If any reserved bits in Address are set, then ASSERT().
581 If Address is not aligned on a 16-bit boundary, then ASSERT().
582 If StartBit is greater than 15, then ASSERT().
583 If EndBit is greater than 15, then ASSERT().
584 If EndBit is less than StartBit, then ASSERT().
585 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
586
587 @param Address PCI configuration register to write.
588 @param StartBit The ordinal of the least significant bit in the bit field.
589 Range 0..15.
590 @param EndBit The ordinal of the most significant bit in the bit field.
591 Range 0..15.
592 @param OrData The value to OR with the PCI configuration register.
593
594 @return The value written back to the PCI configuration register.
595
596 **/
597 UINT16
598 EFIAPI
599 PciSegmentBitFieldOr16 (
600 IN UINT64 Address,
601 IN UINTN StartBit,
602 IN UINTN EndBit,
603 IN UINT16 OrData
604 );
605
606 /**
607 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
608 and writes the result back to the bit field in the 16-bit port.
609
610 Reads the 16-bit PCI configuration register specified by Address,
611 performs a bitwise OR between the read result and the value specified by OrData,
612 and writes the result to the 16-bit PCI configuration register specified by Address.
613 The value written to the PCI configuration register is returned.
614 This function must guarantee that all PCI read and write operations are serialized.
615 Extra left bits in OrData are stripped.
616
617 If any reserved bits in Address are set, then ASSERT().
618 If Address is not aligned on a 16-bit boundary, then ASSERT().
619 If StartBit is greater than 7, then ASSERT().
620 If EndBit is greater than 7, then ASSERT().
621 If EndBit is less than StartBit, then ASSERT().
622 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
623
624 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
625 @param StartBit The ordinal of the least significant bit in the bit field.
626 The ordinal of the least significant bit in a byte is bit 0.
627 @param EndBit The ordinal of the most significant bit in the bit field.
628 The ordinal of the most significant bit in a byte is bit 7.
629 @param AndData The value to AND with the read value from the PCI configuration register.
630
631 @return The value written to the PCI configuration register.
632
633 **/
634 UINT16
635 EFIAPI
636 PciSegmentBitFieldAnd16 (
637 IN UINT64 Address,
638 IN UINTN StartBit,
639 IN UINTN EndBit,
640 IN UINT16 AndData
641 );
642
643 /**
644 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
645 bitwise OR, and writes the result back to the bit field in the
646 16-bit port.
647
648 Reads the 16-bit PCI configuration register specified by Address, performs a
649 bitwise AND followed by a bitwise OR between the read result and
650 the value specified by AndData, and writes the result to the 16-bit PCI
651 configuration register specified by Address. The value written to the PCI
652 configuration register is returned. This function must guarantee that all PCI
653 read and write operations are serialized. Extra left bits in both AndData and
654 OrData are stripped.
655
656 If any reserved bits in Address are set, then ASSERT().
657 If StartBit is greater than 15, then ASSERT().
658 If EndBit is greater than 15, then ASSERT().
659 If EndBit is less than StartBit, then ASSERT().
660 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
661 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
662
663 @param Address PCI configuration register to write.
664 @param StartBit The ordinal of the least significant bit in the bit field.
665 Range 0..15.
666 @param EndBit The ordinal of the most significant bit in the bit field.
667 Range 0..15.
668 @param AndData The value to AND with the PCI configuration register.
669 @param OrData The value to OR with the result of the AND operation.
670
671 @return The value written back to the PCI configuration register.
672
673 **/
674 UINT16
675 EFIAPI
676 PciSegmentBitFieldAndThenOr16 (
677 IN UINT64 Address,
678 IN UINTN StartBit,
679 IN UINTN EndBit,
680 IN UINT16 AndData,
681 IN UINT16 OrData
682 );
683
684 /**
685 Reads a 32-bit PCI configuration register.
686
687 Reads and returns the 32-bit PCI configuration register specified by Address.
688 This function must guarantee that all PCI read and write operations are serialized.
689
690 If any reserved bits in Address are set, then ASSERT().
691 If Address is not aligned on a 32-bit boundary, then ASSERT().
692
693 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
694
695 @return The 32-bit PCI configuration register specified by Address.
696
697 **/
698 UINT32
699 EFIAPI
700 PciSegmentRead32 (
701 IN UINT64 Address
702 );
703
704 /**
705 Writes a 32-bit PCI configuration register.
706
707 Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
708 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
709
710 If any reserved bits in Address are set, then ASSERT().
711 If Address is not aligned on a 32-bit boundary, then ASSERT().
712
713 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
714 @param Value The value to write.
715
716 @return The parameter of Value.
717
718 **/
719 UINT32
720 EFIAPI
721 PciSegmentWrite32 (
722 IN UINT64 Address,
723 IN UINT32 Value
724 );
725
726 /**
727 Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
728
729 Reads the 32-bit PCI configuration register specified by Address,
730 performs a bitwise OR between the read result and the value specified by OrData,
731 and writes the result to the 32-bit PCI configuration register specified by Address.
732 The value written to the PCI configuration register is returned.
733 This function must guarantee that all PCI read and write operations are serialized.
734
735 If any reserved bits in Address are set, then ASSERT().
736 If Address is not aligned on a 32-bit boundary, then ASSERT().
737
738 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
739 @param OrData The value to OR with the PCI configuration register.
740
741 @return The value written to the PCI configuration register.
742
743 **/
744 UINT32
745 EFIAPI
746 PciSegmentOr32 (
747 IN UINT64 Address,
748 IN UINT32 OrData
749 );
750
751 /**
752 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
753
754 Reads the 32-bit PCI configuration register specified by Address,
755 performs a bitwise AND between the read result and the value specified by AndData,
756 and writes the result to the 32-bit PCI configuration register specified by Address.
757 The value written to the PCI configuration register is returned.
758 This function must guarantee that all PCI read and write operations are serialized.
759
760 If any reserved bits in Address are set, then ASSERT().
761 If Address is not aligned on a 32-bit boundary, then ASSERT().
762
763 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
764 @param AndData The value to AND with the PCI configuration register.
765
766 @return The value written to the PCI configuration register.
767
768 **/
769 UINT32
770 EFIAPI
771 PciSegmentAnd32 (
772 IN UINT64 Address,
773 IN UINT32 AndData
774 );
775
776 /**
777 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
778 followed a bitwise OR with another 32-bit value.
779
780 Reads the 32-bit PCI configuration register specified by Address,
781 performs a bitwise AND between the read result and the value specified by AndData,
782 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
783 and writes the result to the 32-bit PCI configuration register specified by Address.
784 The value written to the PCI configuration register is returned.
785 This function must guarantee that all PCI read and write operations are serialized.
786
787 If any reserved bits in Address are set, then ASSERT().
788 If Address is not aligned on a 32-bit boundary, then ASSERT().
789
790 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
791 @param AndData The value to AND with the PCI configuration register.
792 @param OrData The value to OR with the PCI configuration register.
793
794 @return The value written to the PCI configuration register.
795
796 **/
797 UINT32
798 EFIAPI
799 PciSegmentAndThenOr32 (
800 IN UINT64 Address,
801 IN UINT32 AndData,
802 IN UINT32 OrData
803 );
804
805 /**
806 Reads a bit field of a PCI configuration register.
807
808 Reads the bit field in a 32-bit PCI configuration register. The bit field is
809 specified by the StartBit and the EndBit. The value of the bit field is
810 returned.
811
812 If any reserved bits in Address are set, then ASSERT().
813 If Address is not aligned on a 32-bit boundary, then ASSERT().
814 If StartBit is greater than 31, then ASSERT().
815 If EndBit is greater than 31, then ASSERT().
816 If EndBit is less than StartBit, then ASSERT().
817
818 @param Address PCI configuration register to read.
819 @param StartBit The ordinal of the least significant bit in the bit field.
820 Range 0..31.
821 @param EndBit The ordinal of the most significant bit in the bit field.
822 Range 0..31.
823
824 @return The value of the bit field read from the PCI configuration register.
825
826 **/
827 UINT32
828 EFIAPI
829 PciSegmentBitFieldRead32 (
830 IN UINT64 Address,
831 IN UINTN StartBit,
832 IN UINTN EndBit
833 );
834
835 /**
836 Writes a bit field to a PCI configuration register.
837
838 Writes Value to the bit field of the PCI configuration register. The bit
839 field is specified by the StartBit and the EndBit. All other bits in the
840 destination PCI configuration register are preserved. The new value of the
841 32-bit register is returned.
842
843 If any reserved bits in Address are set, then ASSERT().
844 If Address is not aligned on a 32-bit boundary, then ASSERT().
845 If StartBit is greater than 31, then ASSERT().
846 If EndBit is greater than 31, then ASSERT().
847 If EndBit is less than StartBit, then ASSERT().
848 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
849
850 @param Address PCI configuration register to write.
851 @param StartBit The ordinal of the least significant bit in the bit field.
852 Range 0..31.
853 @param EndBit The ordinal of the most significant bit in the bit field.
854 Range 0..31.
855 @param Value New value of the bit field.
856
857 @return The value written back to the PCI configuration register.
858
859 **/
860 UINT32
861 EFIAPI
862 PciSegmentBitFieldWrite32 (
863 IN UINT64 Address,
864 IN UINTN StartBit,
865 IN UINTN EndBit,
866 IN UINT32 Value
867 );
868
869 /**
870 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
871 writes the result back to the bit field in the 32-bit port.
872
873 Reads the 32-bit PCI configuration register specified by Address, performs a
874 bitwise OR between the read result and the value specified by
875 OrData, and writes the result to the 32-bit PCI configuration register
876 specified by Address. The value written to the PCI configuration register is
877 returned. This function must guarantee that all PCI read and write operations
878 are serialized. Extra left bits in OrData are stripped.
879
880 If any reserved bits in Address are set, then ASSERT().
881 If StartBit is greater than 31, then ASSERT().
882 If EndBit is greater than 31, then ASSERT().
883 If EndBit is less than StartBit, then ASSERT().
884 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
885
886 @param Address PCI configuration register to write.
887 @param StartBit The ordinal of the least significant bit in the bit field.
888 Range 0..31.
889 @param EndBit The ordinal of the most significant bit in the bit field.
890 Range 0..31.
891 @param OrData The value to OR with the PCI configuration register.
892
893 @return The value written back to the PCI configuration register.
894
895 **/
896 UINT32
897 EFIAPI
898 PciSegmentBitFieldOr32 (
899 IN UINT64 Address,
900 IN UINTN StartBit,
901 IN UINTN EndBit,
902 IN UINT32 OrData
903 );
904
905 /**
906 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
907 AND, and writes the result back to the bit field in the 32-bit register.
908
909
910 Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
911 AND between the read result and the value specified by AndData, and writes the result
912 to the 32-bit PCI configuration register specified by Address. The value written to
913 the PCI configuration register is returned. This function must guarantee that all PCI
914 read and write operations are serialized. Extra left bits in AndData are stripped.
915 If any reserved bits in Address are set, then ASSERT().
916 If Address is not aligned on a 32-bit boundary, then ASSERT().
917 If StartBit is greater than 31, then ASSERT().
918 If EndBit is greater than 31, then ASSERT().
919 If EndBit is less than StartBit, then ASSERT().
920 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
921
922 @param Address PCI configuration register to write.
923 @param StartBit The ordinal of the least significant bit in the bit field.
924 Range 0..31.
925 @param EndBit The ordinal of the most significant bit in the bit field.
926 Range 0..31.
927 @param AndData The value to AND with the PCI configuration register.
928
929 @return The value written back to the PCI configuration register.
930
931 **/
932 UINT32
933 EFIAPI
934 PciSegmentBitFieldAnd32 (
935 IN UINT64 Address,
936 IN UINTN StartBit,
937 IN UINTN EndBit,
938 IN UINT32 AndData
939 );
940
941 /**
942 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
943 bitwise OR, and writes the result back to the bit field in the
944 32-bit port.
945
946 Reads the 32-bit PCI configuration register specified by Address, performs a
947 bitwise AND followed by a bitwise OR between the read result and
948 the value specified by AndData, and writes the result to the 32-bit PCI
949 configuration register specified by Address. The value written to the PCI
950 configuration register is returned. This function must guarantee that all PCI
951 read and write operations are serialized. Extra left bits in both AndData and
952 OrData are stripped.
953
954 If any reserved bits in Address are set, then ASSERT().
955 If StartBit is greater than 31, then ASSERT().
956 If EndBit is greater than 31, then ASSERT().
957 If EndBit is less than StartBit, then ASSERT().
958 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
959 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
960
961 @param Address PCI configuration register to write.
962 @param StartBit The ordinal of the least significant bit in the bit field.
963 Range 0..31.
964 @param EndBit The ordinal of the most significant bit in the bit field.
965 Range 0..31.
966 @param AndData The value to AND with the PCI configuration register.
967 @param OrData The value to OR with the result of the AND operation.
968
969 @return The value written back to the PCI configuration register.
970
971 **/
972 UINT32
973 EFIAPI
974 PciSegmentBitFieldAndThenOr32 (
975 IN UINT64 Address,
976 IN UINTN StartBit,
977 IN UINTN EndBit,
978 IN UINT32 AndData,
979 IN UINT32 OrData
980 );
981
982 /**
983 Reads a range of PCI configuration registers into a caller supplied buffer.
984
985 Reads the range of PCI configuration registers specified by StartAddress and
986 Size into the buffer specified by Buffer. This function only allows the PCI
987 configuration registers from a single PCI function to be read. Size is
988 returned. When possible 32-bit PCI configuration read cycles are used to read
989 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
990 and 16-bit PCI configuration read cycles may be used at the beginning and the
991 end of the range.
992
993 If any reserved bits in StartAddress are set, then ASSERT().
994 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
995 If Size > 0 and Buffer is NULL, then ASSERT().
996
997 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
998 Function and Register.
999 @param Size Size in bytes of the transfer.
1000 @param Buffer Pointer to a buffer receiving the data read.
1001
1002 @return Size
1003
1004 **/
1005 UINTN
1006 EFIAPI
1007 PciSegmentReadBuffer (
1008 IN UINT64 StartAddress,
1009 IN UINTN Size,
1010 OUT VOID *Buffer
1011 );
1012
1013 /**
1014 Copies the data in a caller supplied buffer to a specified range of PCI
1015 configuration space.
1016
1017 Writes the range of PCI configuration registers specified by StartAddress and
1018 Size from the buffer specified by Buffer. This function only allows the PCI
1019 configuration registers from a single PCI function to be written. Size is
1020 returned. When possible 32-bit PCI configuration write cycles are used to
1021 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1022 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1023 and the end of the range.
1024
1025 If any reserved bits in StartAddress are set, then ASSERT().
1026 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1027 If Size > 0 and Buffer is NULL, then ASSERT().
1028
1029 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
1030 Function and Register.
1031 @param Size Size in bytes of the transfer.
1032 @param Buffer Pointer to a buffer containing the data to write.
1033
1034 @return The parameter of Size.
1035
1036 **/
1037 UINTN
1038 EFIAPI
1039 PciSegmentWriteBuffer (
1040 IN UINT64 StartAddress,
1041 IN UINTN Size,
1042 IN VOID *Buffer
1043 );
1044
1045 #endif