Import Library Class from original MDE package. Also I added the EFI_PEI_CORE_ENTRY_P...
[mirror_edk2.git] / MdePkg / Include / Library / PciSegmentLib.h
1 /** @file
2 Functions accessing PCI configuration registers on any supported PCI segment
3
4 Copyright (c) 2006, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 Module Name: PciSegmentLib.h
14
15 **/
16
17 #ifndef __PCI_SEGMENT_LIB__
18 #define __PCI_SEGMENT_LIB__
19
20
21 /**
22 Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
23 and PCI Register to an address that can be passed to the PCI Segment Library functions.
24
25 Computes an address that is compatible with the PCI Segment Library functions.
26 The unused upper bits of Segment, Bus, Device, Function,
27 and Register are stripped prior to the generation of the address.
28
29 @param Segment PCI Segment number. Range 0..65535.
30 @param Bus PCI Bus number. Range 0..255.
31 @param Device PCI Device number. Range 0..31.
32 @param Function PCI Function number. Range 0..7.
33 @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.
34
35 @return The address that is compatible with the PCI Segment Library functions.
36
37 **/
38 #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \
39 ( ((Register) & 0xfff) | \
40 (((Function) & 0x07) << 12) | \
41 (((Device) & 0x1f) << 15) | \
42 (((Bus) & 0xff) << 20) | \
43 (LShiftU64((Segment) & 0xffff, 32)) \
44 )
45
46 /**
47 Reads an 8-bit PCI configuration register.
48
49 Reads and returns the 8-bit PCI configuration register specified by Address.
50 This function must guarantee that all PCI read and write operations are serialized.
51 If any reserved bits in Address are set, then ASSERT().
52
53 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
54
55 @return The 8-bit PCI configuration register specified by Address.
56
57 **/
58 UINT8
59 EFIAPI
60 PciSegmentRead8 (
61 IN UINT64 Address
62 )
63 ;
64
65 /**
66 Writes an 8-bit PCI configuration register.
67
68 Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
69 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
70 If Address > 0x0FFFFFFF, then ASSERT().
71
72 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
73 @param Value The value to write.
74
75 @return The parameter of Value.
76
77 **/
78 UINT8
79 EFIAPI
80 PciSegmentWrite8 (
81 IN UINT64 Address,
82 IN UINT8 Value
83 )
84 ;
85
86 /**
87 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with an 8-bit value.
88
89 Reads the 8-bit PCI configuration register specified by Address,
90 performs a bitwise inclusive OR between the read result and the value specified by OrData,
91 and writes the result to the 8-bit PCI configuration register specified by Address.
92 The value written to the PCI configuration register is returned.
93 This function must guarantee that all PCI read and write operations are serialized.
94 If any reserved bits in Address are set, then ASSERT().
95
96 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
97 @param OrData The value to OR with the PCI configuration register.
98
99 @return The value written to the PCI configuration register.
100
101 **/
102 UINT8
103 EFIAPI
104 PciSegmentOr8 (
105 IN UINT64 Address,
106 IN UINT8 OrData
107 )
108 ;
109
110 /**
111 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
112
113 Reads the 8-bit PCI configuration register specified by Address,
114 performs a bitwise AND between the read result and the value specified by AndData,
115 and writes the result to the 8-bit PCI configuration register specified by Address.
116 The value written to the PCI configuration register is returned.
117 This function must guarantee that all PCI read and write operations are serialized.
118 If any reserved bits in Address are set, then ASSERT().
119
120 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
121 @param Andata The value to AND with the PCI configuration register.
122
123 @return The value written to the PCI configuration register.
124
125 **/
126 UINT8
127 EFIAPI
128 PciSegmentAnd8 (
129 IN UINT64 Address,
130 IN UINT8 AndData
131 )
132 ;
133
134 /**
135 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
136 followed a bitwise inclusive OR with another 8-bit value.
137
138 Reads the 8-bit PCI configuration register specified by Address,
139 performs a bitwise AND between the read result and the value specified by AndData,
140 performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,
141 and writes the result to the 8-bit PCI configuration register specified by Address.
142 The value written to the PCI configuration register is returned.
143 This function must guarantee that all PCI read and write operations are serialized.
144 If any reserved bits in Address are set, then ASSERT().
145
146 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
147 @param Andata The value to AND with the PCI configuration register.
148 @param OrData The value to OR with the PCI configuration register.
149
150 @return The value written to the PCI configuration register.
151
152 **/
153 UINT8
154 EFIAPI
155 PciSegmentAndThenOr8 (
156 IN UINT64 Address,
157 IN UINT8 AndData,
158 IN UINT8 OrData
159 )
160 ;
161
162 /**
163 Reads a bit field of a PCI configuration register.
164
165 Reads the bit field in an 8-bit PCI configuration register.
166 The bit field is specified by the StartBit and the EndBit.
167 The value of the bit field is returned.
168 If any reserved bits in Address are set, then ASSERT().
169 If StartBit is greater than 7, then ASSERT().
170 If EndBit is greater than 7, then ASSERT().
171 If EndBit is less than StartBit, then ASSERT().
172
173 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
174 @param StartBit The ordinal of the least significant bit in the bit field.
175 The ordinal of the least significant bit in a byte is bit 0.
176 @param EndBit The ordinal of the most significant bit in the bit field.
177 The ordinal of the most significant bit in a byte is bit 7.
178
179 @return The value of the bit field.
180
181 **/
182 UINT8
183 EFIAPI
184 PciSegmentBitFieldRead8 (
185 IN UINT64 Address,
186 IN UINTN StartBit,
187 IN UINTN EndBit
188 )
189 ;
190
191 /**
192 Writes a bit field to a PCI configuration register.
193
194 Writes Value to the bit field of the PCI configuration register.
195 The bit field is specified by the StartBit and the EndBit.
196 All other bits in the destination PCI configuration register are preserved.
197 The new value of the 8-bit register is returned.
198 If any reserved bits in Address are set, then ASSERT().
199 If StartBit is greater than 7, then ASSERT().
200 If EndBit is greater than 7, then ASSERT().
201 If EndBit is less than StartBit, then ASSERT().
202
203 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
204 @param StartBit The ordinal of the least significant bit in the bit field.
205 The ordinal of the least significant bit in a byte is bit 0.
206 @param EndBit The ordinal of the most significant bit in the bit field.
207 The ordinal of the most significant bit in a byte is bit 7.
208 @param Value New value of the bit field.
209
210 @return The new value of the 8-bit register.
211
212 **/
213 UINT8
214 EFIAPI
215 PciSegmentBitFieldWrite8 (
216 IN UINT64 Address,
217 IN UINTN StartBit,
218 IN UINTN EndBit,
219 IN UINT8 Value
220 )
221 ;
222
223 /**
224 Reads the 8-bit PCI configuration register specified by Address,
225 performs a bitwise inclusive OR between the read result and the value specified by OrData,
226 and writes the result to the 8-bit PCI configuration register specified by Address.
227
228 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
229 @param StartBit The ordinal of the least significant bit in the bit field.
230 The ordinal of the least significant bit in a byte is bit 0.
231 @param EndBit The ordinal of the most significant bit in the bit field.
232 The ordinal of the most significant bit in a byte is bit 7.
233 @param OrData The value to OR with the read value from the PCI configuration register.
234
235 @return The value written to the PCI configuration register.
236
237 **/
238 UINT8
239 EFIAPI
240 PciSegmentBitFieldOr8 (
241 IN UINT64 Address,
242 IN UINTN StartBit,
243 IN UINTN EndBit,
244 IN UINT8 OrData
245 )
246 ;
247
248 /**
249 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR,
250 and writes the result back to the bit field in the 8-bit port.
251
252 Reads the 8-bit PCI configuration register specified by Address,
253 performs a bitwise inclusive OR between the read result and the value specified by OrData,
254 and writes the result to the 8-bit PCI configuration register specified by Address.
255 The value written to the PCI configuration register is returned.
256 This function must guarantee that all PCI read and write operations are serialized.
257 Extra left bits in OrData are stripped.
258 If any reserved bits in Address are set, then ASSERT().
259 If StartBit is greater than 7, then ASSERT().
260 If EndBit is greater than 7, then ASSERT().
261 If EndBit is less than StartBit, then ASSERT().
262
263 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
264 @param StartBit The ordinal of the least significant bit in the bit field.
265 The ordinal of the least significant bit in a byte is bit 0.
266 @param EndBit The ordinal of the most significant bit in the bit field.
267 The ordinal of the most significant bit in a byte is bit 7.
268 @param AndData The value to AND with the read value from the PCI configuration register.
269
270 @return The value written to the PCI configuration register.
271
272 **/
273 UINT8
274 EFIAPI
275 PciSegmentBitFieldAnd8 (
276 IN UINT64 Address,
277 IN UINTN StartBit,
278 IN UINTN EndBit,
279 IN UINT8 AndData
280 )
281 ;
282
283 /**
284 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND,
285 and writes the result back to the bit field in the 8-bit register.
286
287 Reads the 8-bit PCI configuration register specified by Address,
288 performs a bitwise AND between the read result and the value specified by AndData,
289 and writes the result to the 8-bit PCI configuration register specified by Address.
290 The value written to the PCI configuration register is returned.
291 This function must guarantee that all PCI read and write operations are serialized.
292 Extra left bits in AndData are stripped.
293 If any reserved bits in Address are set, then ASSERT().
294 If StartBit is greater than 7, then ASSERT().
295 If EndBit is greater than 7, then ASSERT().
296 If EndBit is less than StartBit, then ASSERT().
297
298 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
299 @param StartBit The ordinal of the least significant bit in the bit field.
300 The ordinal of the least significant bit in a byte is bit 0.
301 @param EndBit The ordinal of the most significant bit in the bit field.
302 The ordinal of the most significant bit in a byte is bit 7.
303 @param AndData The value to AND with the read value from the PCI configuration register.
304 @param OrData The value to OR with the read value from the PCI configuration register.
305
306 @return The value written to the PCI configuration register.
307
308 **/
309 UINT8
310 EFIAPI
311 PciSegmentBitFieldAndThenOr8 (
312 IN UINT64 Address,
313 IN UINTN StartBit,
314 IN UINTN EndBit,
315 IN UINT8 AndData,
316 IN UINT8 OrData
317 )
318 ;
319
320 /**
321 Reads a 16-bit PCI configuration register.
322
323 Reads and returns the 16-bit PCI configuration register specified by Address.
324 This function must guarantee that all PCI read and write operations are serialized.
325 If any reserved bits in Address are set, then ASSERT().
326
327 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
328
329 @return The 16-bit PCI configuration register specified by Address.
330
331 **/
332 UINT16
333 EFIAPI
334 PciSegmentRead16 (
335 IN UINT64 Address
336 )
337 ;
338
339 /**
340 Writes a 16-bit PCI configuration register.
341
342 Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
343 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
344 If Address > 0x0FFFFFFF, then ASSERT().
345
346 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
347 @param Value The value to write.
348
349 @return The parameter of Value.
350
351 **/
352 UINT16
353 EFIAPI
354 PciSegmentWrite16 (
355 IN UINT64 Address,
356 IN UINT16 Value
357 )
358 ;
359
360 /**
361 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with a 16-bit value.
362
363 Reads the 16-bit PCI configuration register specified by Address,
364 performs a bitwise inclusive OR between the read result and the value specified by OrData,
365 and writes the result to the 16-bit PCI configuration register specified by Address.
366 The value written to the PCI configuration register is returned.
367 This function must guarantee that all PCI read and write operations are serialized.
368 If any reserved bits in Address are set, then ASSERT().
369
370 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
371 @param OrData The value to OR with the PCI configuration register.
372
373 @return The value written to the PCI configuration register.
374
375 **/
376 UINT16
377 EFIAPI
378 PciSegmentOr16 (
379 IN UINT64 Address,
380 IN UINT16 OrData
381 )
382 ;
383
384 /**
385 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
386
387 Reads the 16-bit PCI configuration register specified by Address,
388 performs a bitwise AND between the read result and the value specified by AndData,
389 and writes the result to the 16-bit PCI configuration register specified by Address.
390 The value written to the PCI configuration register is returned.
391 This function must guarantee that all PCI read and write operations are serialized.
392 If any reserved bits in Address are set, then ASSERT().
393
394 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
395 @param Andata The value to AND with the PCI configuration register.
396
397 @return The value written to the PCI configuration register.
398
399 **/
400 UINT16
401 EFIAPI
402 PciSegmentAnd16 (
403 IN UINT64 Address,
404 IN UINT16 AndData
405 )
406 ;
407
408 /**
409 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
410 followed a bitwise inclusive OR with another 16-bit value.
411
412 Reads the 16-bit PCI configuration register specified by Address,
413 performs a bitwise AND between the read result and the value specified by AndData,
414 performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,
415 and writes the result to the 16-bit PCI configuration register specified by Address.
416 The value written to the PCI configuration register is returned.
417 This function must guarantee that all PCI read and write operations are serialized.
418 If any reserved bits in Address are set, then ASSERT().
419
420 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
421 @param Andata The value to AND with the PCI configuration register.
422 @param OrData The value to OR with the PCI configuration register.
423
424 @return The value written to the PCI configuration register.
425
426 **/
427 UINT16
428 EFIAPI
429 PciSegmentAndThenOr16 (
430 IN UINT64 Address,
431 IN UINT16 AndData,
432 IN UINT16 OrData
433 )
434 ;
435
436 /**
437 Reads a bit field of a PCI configuration register.
438
439 Reads the bit field in a 16-bit PCI configuration register.
440 The bit field is specified by the StartBit and the EndBit.
441 The value of the bit field is returned.
442 If any reserved bits in Address are set, then ASSERT().
443 If StartBit is greater than 7, then ASSERT().
444 If EndBit is greater than 7, then ASSERT().
445 If EndBit is less than StartBit, then ASSERT().
446
447 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
448 @param StartBit The ordinal of the least significant bit in the bit field.
449 The ordinal of the least significant bit in a byte is bit 0.
450 @param EndBit The ordinal of the most significant bit in the bit field.
451 The ordinal of the most significant bit in a byte is bit 7.
452
453 @return The value of the bit field.
454
455 **/
456 UINT16
457 EFIAPI
458 PciSegmentBitFieldRead16 (
459 IN UINT64 Address,
460 IN UINTN StartBit,
461 IN UINTN EndBit
462 )
463 ;
464
465 /**
466 Writes a bit field to a PCI configuration register.
467
468 Writes Value to the bit field of the PCI configuration register.
469 The bit field is specified by the StartBit and the EndBit.
470 All other bits in the destination PCI configuration register are preserved.
471 The new value of the 16-bit register is returned.
472 If any reserved bits in Address are set, then ASSERT().
473 If StartBit is greater than 7, then ASSERT().
474 If EndBit is greater than 7, then ASSERT().
475 If EndBit is less than StartBit, then ASSERT().
476
477 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
478 @param StartBit The ordinal of the least significant bit in the bit field.
479 The ordinal of the least significant bit in a byte is bit 0.
480 @param EndBit The ordinal of the most significant bit in the bit field.
481 The ordinal of the most significant bit in a byte is bit 7.
482 @param Value New value of the bit field.
483
484 @return The new value of the 16-bit register.
485
486 **/
487 UINT16
488 EFIAPI
489 PciSegmentBitFieldWrite16 (
490 IN UINT64 Address,
491 IN UINTN StartBit,
492 IN UINTN EndBit,
493 IN UINT16 Value
494 )
495 ;
496
497 /**
498 Reads the 16-bit PCI configuration register specified by Address,
499 performs a bitwise inclusive OR between the read result and the value specified by OrData,
500 and writes the result to the 16-bit PCI configuration register specified by Address.
501
502 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
503 @param StartBit The ordinal of the least significant bit in the bit field.
504 The ordinal of the least significant bit in a byte is bit 0.
505 @param EndBit The ordinal of the most significant bit in the bit field.
506 The ordinal of the most significant bit in a byte is bit 7.
507 @param OrData The value to OR with the read value from the PCI configuration register.
508
509 @return The value written to the PCI configuration register.
510
511 **/
512 UINT16
513 EFIAPI
514 PciSegmentBitFieldOr16 (
515 IN UINT64 Address,
516 IN UINTN StartBit,
517 IN UINTN EndBit,
518 IN UINT16 OrData
519 )
520 ;
521
522 /**
523 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
524 and writes the result back to the bit field in the 16-bit port.
525
526 Reads the 16-bit PCI configuration register specified by Address,
527 performs a bitwise inclusive OR between the read result and the value specified by OrData,
528 and writes the result to the 16-bit PCI configuration register specified by Address.
529 The value written to the PCI configuration register is returned.
530 This function must guarantee that all PCI read and write operations are serialized.
531 Extra left bits in OrData are stripped.
532 If any reserved bits in Address are set, then ASSERT().
533 If StartBit is greater than 7, then ASSERT().
534 If EndBit is greater than 7, then ASSERT().
535 If EndBit is less than StartBit, then ASSERT().
536
537 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
538 @param StartBit The ordinal of the least significant bit in the bit field.
539 The ordinal of the least significant bit in a byte is bit 0.
540 @param EndBit The ordinal of the most significant bit in the bit field.
541 The ordinal of the most significant bit in a byte is bit 7.
542 @param AndData The value to AND with the read value from the PCI configuration register.
543
544 @return The value written to the PCI configuration register.
545
546 **/
547 UINT16
548 EFIAPI
549 PciSegmentBitFieldAnd16 (
550 IN UINT64 Address,
551 IN UINTN StartBit,
552 IN UINTN EndBit,
553 IN UINT16 AndData
554 )
555 ;
556
557 /**
558 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND,
559 and writes the result back to the bit field in the 16-bit register.
560
561 Reads the 16-bit PCI configuration register specified by Address,
562 performs a bitwise AND between the read result and the value specified by AndData,
563 and writes the result to the 16-bit PCI configuration register specified by Address.
564 The value written to the PCI configuration register is returned.
565 This function must guarantee that all PCI read and write operations are serialized.
566 Extra left bits in AndData are stripped.
567 If any reserved bits in Address are set, then ASSERT().
568 If StartBit is greater than 7, then ASSERT().
569 If EndBit is greater than 7, then ASSERT().
570 If EndBit is less than StartBit, then ASSERT().
571
572 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
573 @param StartBit The ordinal of the least significant bit in the bit field.
574 The ordinal of the least significant bit in a byte is bit 0.
575 @param EndBit The ordinal of the most significant bit in the bit field.
576 The ordinal of the most significant bit in a byte is bit 7.
577 @param AndData The value to AND with the read value from the PCI configuration register.
578 @param OrData The value to OR with the read value from the PCI configuration register.
579
580 @return The value written to the PCI configuration register.
581
582 **/
583 UINT16
584 EFIAPI
585 PciSegmentBitFieldAndThenOr16 (
586 IN UINT64 Address,
587 IN UINTN StartBit,
588 IN UINTN EndBit,
589 IN UINT16 AndData,
590 IN UINT16 OrData
591 )
592 ;
593
594 /**
595 Reads a 32-bit PCI configuration register.
596
597 Reads and returns the 32-bit PCI configuration register specified by Address.
598 This function must guarantee that all PCI read and write operations are serialized.
599 If any reserved bits in Address are set, then ASSERT().
600
601 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
602
603 @return The 32-bit PCI configuration register specified by Address.
604
605 **/
606 UINT32
607 EFIAPI
608 PciSegmentRead32 (
609 IN UINT64 Address
610 )
611 ;
612
613 /**
614 Writes a 32-bit PCI configuration register.
615
616 Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
617 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
618 If Address > 0x0FFFFFFF, then ASSERT().
619
620 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
621 @param Value The value to write.
622
623 @return The parameter of Value.
624
625 **/
626 UINT32
627 EFIAPI
628 PciSegmentWrite32 (
629 IN UINT64 Address,
630 IN UINT32 Value
631 )
632 ;
633
634 /**
635 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with a 32-bit value.
636
637 Reads the 32-bit PCI configuration register specified by Address,
638 performs a bitwise inclusive OR between the read result and the value specified by OrData,
639 and writes the result to the 32-bit PCI configuration register specified by Address.
640 The value written to the PCI configuration register is returned.
641 This function must guarantee that all PCI read and write operations are serialized.
642 If any reserved bits in Address are set, then ASSERT().
643
644 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
645 @param OrData The value to OR with the PCI configuration register.
646
647 @return The value written to the PCI configuration register.
648
649 **/
650 UINT32
651 EFIAPI
652 PciSegmentOr32 (
653 IN UINT64 Address,
654 IN UINT32 OrData
655 )
656 ;
657
658 /**
659 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
660
661 Reads the 32-bit PCI configuration register specified by Address,
662 performs a bitwise AND between the read result and the value specified by AndData,
663 and writes the result to the 32-bit PCI configuration register specified by Address.
664 The value written to the PCI configuration register is returned.
665 This function must guarantee that all PCI read and write operations are serialized.
666 If any reserved bits in Address are set, then ASSERT().
667
668 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
669 @param Andata The value to AND with the PCI configuration register.
670
671 @return The value written to the PCI configuration register.
672
673 **/
674 UINT32
675 EFIAPI
676 PciSegmentAnd32 (
677 IN UINT64 Address,
678 IN UINT32 AndData
679 )
680 ;
681
682 /**
683 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
684 followed a bitwise inclusive OR with another 32-bit value.
685
686 Reads the 32-bit PCI configuration register specified by Address,
687 performs a bitwise AND between the read result and the value specified by AndData,
688 performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,
689 and writes the result to the 32-bit PCI configuration register specified by Address.
690 The value written to the PCI configuration register is returned.
691 This function must guarantee that all PCI read and write operations are serialized.
692 If any reserved bits in Address are set, then ASSERT().
693
694 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
695 @param Andata The value to AND with the PCI configuration register.
696 @param OrData The value to OR with the PCI configuration register.
697
698 @return The value written to the PCI configuration register.
699
700 **/
701 UINT32
702 EFIAPI
703 PciSegmentAndThenOr32 (
704 IN UINT64 Address,
705 IN UINT32 AndData,
706 IN UINT32 OrData
707 )
708 ;
709
710 /**
711 Reads a bit field of a PCI configuration register.
712
713 Reads the bit field in a 32-bit PCI configuration register.
714 The bit field is specified by the StartBit and the EndBit.
715 The value of the bit field is returned.
716 If any reserved bits in Address are set, then ASSERT().
717 If StartBit is greater than 7, then ASSERT().
718 If EndBit is greater than 7, then ASSERT().
719 If EndBit is less than StartBit, then ASSERT().
720
721 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
722 @param StartBit The ordinal of the least significant bit in the bit field.
723 The ordinal of the least significant bit in a byte is bit 0.
724 @param EndBit The ordinal of the most significant bit in the bit field.
725 The ordinal of the most significant bit in a byte is bit 7.
726
727 @return The value of the bit field.
728
729 **/
730 UINT32
731 EFIAPI
732 PciSegmentBitFieldRead32 (
733 IN UINT64 Address,
734 IN UINTN StartBit,
735 IN UINTN EndBit
736 )
737 ;
738
739 /**
740 Writes a bit field to a PCI configuration register.
741
742 Writes Value to the bit field of the PCI configuration register.
743 The bit field is specified by the StartBit and the EndBit.
744 All other bits in the destination PCI configuration register are preserved.
745 The new value of the 32-bit register is returned.
746 If any reserved bits in Address are set, then ASSERT().
747 If StartBit is greater than 7, then ASSERT().
748 If EndBit is greater than 7, then ASSERT().
749 If EndBit is less than StartBit, then ASSERT().
750
751 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
752 @param StartBit The ordinal of the least significant bit in the bit field.
753 The ordinal of the least significant bit in a byte is bit 0.
754 @param EndBit The ordinal of the most significant bit in the bit field.
755 The ordinal of the most significant bit in a byte is bit 7.
756 @param Value New value of the bit field.
757
758 @return The new value of the 32-bit register.
759
760 **/
761 UINT32
762 EFIAPI
763 PciSegmentBitFieldWrite32 (
764 IN UINT64 Address,
765 IN UINTN StartBit,
766 IN UINTN EndBit,
767 IN UINT32 Value
768 )
769 ;
770
771 /**
772 Reads the 32-bit PCI configuration register specified by Address,
773 performs a bitwise inclusive OR between the read result and the value specified by OrData,
774 and writes the result to the 32-bit PCI configuration register specified by Address.
775
776 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
777 @param StartBit The ordinal of the least significant bit in the bit field.
778 The ordinal of the least significant bit in a byte is bit 0.
779 @param EndBit The ordinal of the most significant bit in the bit field.
780 The ordinal of the most significant bit in a byte is bit 7.
781 @param OrData The value to OR with the read value from the PCI configuration register.
782
783 @return The value written to the PCI configuration register.
784
785 **/
786 UINT32
787 EFIAPI
788 PciSegmentBitFieldOr32 (
789 IN UINT64 Address,
790 IN UINTN StartBit,
791 IN UINTN EndBit,
792 IN UINT32 OrData
793 )
794 ;
795
796 /**
797 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR,
798 and writes the result back to the bit field in the 32-bit port.
799
800 Reads the 32-bit PCI configuration register specified by Address,
801 performs a bitwise inclusive OR between the read result and the value specified by OrData,
802 and writes the result to the 32-bit PCI configuration register specified by Address.
803 The value written to the PCI configuration register is returned.
804 This function must guarantee that all PCI read and write operations are serialized.
805 Extra left bits in OrData are stripped.
806 If any reserved bits in Address are set, then ASSERT().
807 If StartBit is greater than 7, then ASSERT().
808 If EndBit is greater than 7, then ASSERT().
809 If EndBit is less than StartBit, then ASSERT().
810
811 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
812 @param StartBit The ordinal of the least significant bit in the bit field.
813 The ordinal of the least significant bit in a byte is bit 0.
814 @param EndBit The ordinal of the most significant bit in the bit field.
815 The ordinal of the most significant bit in a byte is bit 7.
816 @param AndData The value to AND with the read value from the PCI configuration register.
817
818 @return The value written to the PCI configuration register.
819
820 **/
821 UINT32
822 EFIAPI
823 PciSegmentBitFieldAnd32 (
824 IN UINT64 Address,
825 IN UINTN StartBit,
826 IN UINTN EndBit,
827 IN UINT32 AndData
828 )
829 ;
830
831 /**
832 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND,
833 and writes the result back to the bit field in the 32-bit register.
834
835 Reads the 32-bit PCI configuration register specified by Address,
836 performs a bitwise AND between the read result and the value specified by AndData,
837 and writes the result to the 32-bit PCI configuration register specified by Address.
838 The value written to the PCI configuration register is returned.
839 This function must guarantee that all PCI read and write operations are serialized.
840 Extra left bits in AndData are stripped.
841 If any reserved bits in Address are set, then ASSERT().
842 If StartBit is greater than 7, then ASSERT().
843 If EndBit is greater than 7, then ASSERT().
844 If EndBit is less than StartBit, then ASSERT().
845
846 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
847 @param StartBit The ordinal of the least significant bit in the bit field.
848 The ordinal of the least significant bit in a byte is bit 0.
849 @param EndBit The ordinal of the most significant bit in the bit field.
850 The ordinal of the most significant bit in a byte is bit 7.
851 @param AndData The value to AND with the read value from the PCI configuration register.
852 @param OrData The value to OR with the read value from the PCI configuration register.
853
854 @return The value written to the PCI configuration register.
855
856 **/
857 UINT32
858 EFIAPI
859 PciSegmentBitFieldAndThenOr32 (
860 IN UINT64 Address,
861 IN UINTN StartBit,
862 IN UINTN EndBit,
863 IN UINT32 AndData,
864 IN UINT32 OrData
865 )
866 ;
867
868 /**
869 Reads a range of PCI configuration registers into a caller supplied buffer.
870
871 Reads the range of PCI configuration registers specified by StartAddress
872 and Size into the buffer specified by Buffer.
873 This function only allows the PCI configuration registers from a single PCI function to be read.
874 Size is returned.
875 If any reserved bits in StartAddress are set, then ASSERT().
876 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
877 If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().
878 If Buffer is NULL, then ASSERT().
879
880 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.
881 @param Size Size in bytes of the transfer.
882 @param Buffer Pointer to a buffer receiving the data read.
883
884 @return The paramter of Size.
885
886 **/
887 UINTN
888 EFIAPI
889 PciSegmentReadBuffer (
890 IN UINT64 StartAddress,
891 IN UINTN Size,
892 OUT VOID *Buffer
893 )
894 ;
895
896 /**
897 Copies the data in a caller supplied buffer to a specified range of PCI configuration space.
898
899 Writes the range of PCI configuration registers specified by StartAddress
900 and Size from the buffer specified by Buffer.
901 This function only allows the PCI configuration registers from a single PCI function to be written.
902 Size is returned.
903 If any reserved bits in StartAddress are set, then ASSERT().
904 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
905 If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().
906 If Buffer is NULL, then ASSERT().
907
908 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.
909 @param Size Size in bytes of the transfer.
910 @param Buffer Pointer to a buffer containing the data to write.
911
912 @return The paramter of Size.
913
914 **/
915 UINTN
916 EFIAPI
917 PciSegmentWriteBuffer (
918 IN UINT64 StartAddress,
919 IN UINTN Size,
920 IN VOID *Buffer
921 )
922 ;
923
924 #endif