MdePkg/Include/Library/PciSegmentLib.h

   1 /** @file
   2   Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
   3
   4   The PCI Segment Library function provide services to read, write, and modify the PCI configuration
   5   registers on PCI root bridges on any supported PCI segment.  These library services take a single
   6   address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.
   7   The layout of this address parameter is as follows:
   8
   9             PCI Register:       Bits 0..11
  10             PCI Function        Bits 12..14
  11             PCI Device  Bits 15..19
  12             PCI Bus     Bits 20..27
  13             Reserved    Bits 28..31.  Must be 0.
  14             PCI Segment Bits 32..47
  15             Reserved    Bits 48..63.  Must be 0.
  16
  17   | Reserved (MBZ) | Segment | Reserved (MBZ) |     Bus     | Device | Function | Register |
  18   63             48  47    32  31           28 27         20 19    15 14      12 11         0
  19
  20   These functions perform PCI configuration cycles using the default PCI configuration access
  21   method.  This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
  22   may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate
  23   access method.  Modules will typically use the PCI Segment Library for its PCI configuration
  24   accesses when PCI Segments other than Segment #0 must be accessed.
  25
  26 Copyright (c) 2006 - 2008, Intel Corporation
  27 All rights reserved. This program and the accompanying materials
  28 are licensed and made available under the terms and conditions of the BSD License
  29 which accompanies this distribution.  The full text of the license may be found at
  30 http://opensource.org/licenses/bsd-license.php
  31
  32 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  33 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  34
  35 **/
  36
  37 #ifndef __PCI_SEGMENT_LIB__
  38 #define __PCI_SEGMENT_LIB__
  39
  40
  41 /**
  42   Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
  43   and PCI Register to an address that can be passed to the PCI Segment Library functions.
  44
  45   Computes an address that is compatible with the PCI Segment Library functions.
  46   The unused upper bits of Segment, Bus, Device, Function,
  47   and Register are stripped prior to the generation of the address.
  48
  49   @param  Segment   PCI Segment number.  Range 0..65535.
  50   @param  Bus       PCI Bus number.  Range 0..255.
  51   @param  Device    PCI Device number.  Range 0..31.
  52   @param  Function  PCI Function number.  Range 0..7.
  53   @param  Register  PCI Register number.  Range 0..255 for PCI.  Range 0..4095 for PCI Express.
  54
  55   @return The address that is compatible with the PCI Segment Library functions.
  56
  57 **/
  58 #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \
  59   ( ((Register) & 0xfff)              | \
  60     (((Function) & 0x07) << 12)       | \
  61     (((Device) & 0x1f) << 15)         | \
  62     (((Bus) & 0xff) << 20)            | \
  63     (LShiftU64((Segment) & 0xffff, 32)) \
  64   )
  65
  66 /**
  67   Register a PCI device so PCI configuration registers may be accessed after
  68   SetVirtualAddressMap().
  69
  70   If Address > 0x0FFFFFFF, then ASSERT().
  71
  72   @param  Address Address that encodes the PCI Bus, Device, Function and
  73                   Register.
  74
  75   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
  76   @retval RETURN_UNSUPPORTED       An attempt was made to call this function
  77                                    after ExitBootServices().
  78   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
  79                                    at runtime could not be mapped.
  80   @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to
  81                                    complete the registration.
  82
  83 **/
  84 RETURN_STATUS
  85 EFIAPI
  86 PciSegmentRegisterForRuntimeAccess (
  87   IN UINTN  Address
  88   );
  89
  90 /**
  91   Reads an 8-bit PCI configuration register.
  92
  93   Reads and returns the 8-bit PCI configuration register specified by Address.
  94   This function must guarantee that all PCI read and write operations are serialized.
  95
  96   If any reserved bits in Address are set, then ASSERT().
  97
  98   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
  99
 100   @return The 8-bit PCI configuration register specified by Address.
 101
 102 **/
 103 UINT8
 104 EFIAPI
 105 PciSegmentRead8 (
 106   IN UINT64                    Address
 107   );
 108
 109 /**
 110   Writes an 8-bit PCI configuration register.
 111
 112   Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
 113   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 114
 115   If Address > 0x0FFFFFFF, then ASSERT().
 116
 117   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 118   @param  Value       The value to write.
 119
 120   @return The value written to the PCI configuration register.
 121
 122 **/
 123 UINT8
 124 EFIAPI
 125 PciSegmentWrite8 (
 126   IN UINT64                    Address,
 127   IN UINT8                     Value
 128   );
 129
 130 /**
 131   Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
 132
 133   Reads the 8-bit PCI configuration register specified by Address,
 134   performs a bitwise OR between the read result and the value specified by OrData,
 135   and writes the result to the 8-bit PCI configuration register specified by Address.
 136   The value written to the PCI configuration register is returned.
 137   This function must guarantee that all PCI read and write operations are serialized.
 138
 139   If any reserved bits in Address are set, then ASSERT().
 140
 141   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 142   @param  OrData    The value to OR with the PCI configuration register.
 143
 144   @return The value written to the PCI configuration register.
 145
 146 **/
 147 UINT8
 148 EFIAPI
 149 PciSegmentOr8 (
 150   IN UINT64                    Address,
 151   IN UINT8                     OrData
 152   );
 153
 154 /**
 155   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
 156
 157   Reads the 8-bit PCI configuration register specified by Address,
 158   performs a bitwise AND between the read result and the value specified by AndData,
 159   and writes the result to the 8-bit PCI configuration register specified by Address.
 160   The value written to the PCI configuration register is returned.
 161   This function must guarantee that all PCI read and write operations are serialized.
 162   If any reserved bits in Address are set, then ASSERT().
 163
 164   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 165   @param  AndData   The value to AND with the PCI configuration register.
 166
 167   @return The value written to the PCI configuration register.
 168
 169 **/
 170 UINT8
 171 EFIAPI
 172 PciSegmentAnd8 (
 173   IN UINT64                    Address,
 174   IN UINT8                     AndData
 175   );
 176
 177 /**
 178   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
 179   followed a  bitwise OR with another 8-bit value.
 180
 181   Reads the 8-bit PCI configuration register specified by Address,
 182   performs a bitwise AND between the read result and the value specified by AndData,
 183   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
 184   and writes the result to the 8-bit PCI configuration register specified by Address.
 185   The value written to the PCI configuration register is returned.
 186   This function must guarantee that all PCI read and write operations are serialized.
 187
 188   If any reserved bits in Address are set, then ASSERT().
 189
 190   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 191   @param  AndData    The value to AND with the PCI configuration register.
 192   @param  OrData    The value to OR with the PCI configuration register.
 193
 194   @return The value written to the PCI configuration register.
 195
 196 **/
 197 UINT8
 198 EFIAPI
 199 PciSegmentAndThenOr8 (
 200   IN UINT64                    Address,
 201   IN UINT8                     AndData,
 202   IN UINT8                     OrData
 203   );
 204
 205 /**
 206   Reads a bit field of a PCI configuration register.
 207
 208   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 209   specified by the StartBit and the EndBit. The value of the bit field is
 210   returned.
 211
 212   If any reserved bits in Address are set, then ASSERT().
 213   If StartBit is greater than 7, then ASSERT().
 214   If EndBit is greater than 7, then ASSERT().
 215   If EndBit is less than StartBit, then ASSERT().
 216
 217   @param  Address   PCI configuration register to read.
 218   @param  StartBit  The ordinal of the least significant bit in the bit field.
 219                     Range 0..7.
 220   @param  EndBit    The ordinal of the most significant bit in the bit field.
 221                     Range 0..7.
 222
 223   @return The value of the bit field read from the PCI configuration register.
 224
 225 **/
 226 UINT8
 227 EFIAPI
 228 PciSegmentBitFieldRead8 (
 229   IN UINT64                    Address,
 230   IN UINTN                     StartBit,
 231   IN UINTN                     EndBit
 232   );
 233
 234 /**
 235   Writes a bit field to a PCI configuration register.
 236
 237   Writes Value to the bit field of the PCI configuration register. The bit
 238   field is specified by the StartBit and the EndBit. All other bits in the
 239   destination PCI configuration register are preserved. The new value of the
 240   8-bit register is returned.
 241
 242   If any reserved bits in Address are set, then ASSERT().
 243   If StartBit is greater than 7, then ASSERT().
 244   If EndBit is greater than 7, then ASSERT().
 245   If EndBit is less than StartBit, then ASSERT().
 246
 247   @param  Address   PCI configuration register to write.
 248   @param  StartBit  The ordinal of the least significant bit in the bit field.
 249                     Range 0..7.
 250   @param  EndBit    The ordinal of the most significant bit in the bit field.
 251                     Range 0..7.
 252   @param  Value     New value of the bit field.
 253
 254   @return The value written back to the PCI configuration register.
 255
 256 **/
 257 UINT8
 258 EFIAPI
 259 PciSegmentBitFieldWrite8 (
 260   IN UINT64                    Address,
 261   IN UINTN                     StartBit,
 262   IN UINTN                     EndBit,
 263   IN UINT8                     Value
 264   );
 265
 266 /**
 267   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 268   writes the result back to the bit field in the 8-bit port.
 269
 270   Reads the 8-bit PCI configuration register specified by Address, performs a
 271   bitwise OR between the read result and the value specified by
 272   OrData, and writes the result to the 8-bit PCI configuration register
 273   specified by Address. The value written to the PCI configuration register is
 274   returned. This function must guarantee that all PCI read and write operations
 275   are serialized. Extra left bits in OrData are stripped.
 276
 277   If any reserved bits in Address are set, then ASSERT().
 278   If StartBit is greater than 7, then ASSERT().
 279   If EndBit is greater than 7, then ASSERT().
 280   If EndBit is less than StartBit, then ASSERT().
 281
 282   @param  Address   PCI configuration register to write.
 283   @param  StartBit  The ordinal of the least significant bit in the bit field.
 284                     Range 0..7.
 285   @param  EndBit    The ordinal of the most significant bit in the bit field.
 286                     Range 0..7.
 287   @param  OrData    The value to OR with the PCI configuration register.
 288
 289   @return The value written back to the PCI configuration register.
 290
 291 **/
 292 UINT8
 293 EFIAPI
 294 PciSegmentBitFieldOr8 (
 295   IN UINT64                    Address,
 296   IN UINTN                     StartBit,
 297   IN UINTN                     EndBit,
 298   IN UINT8                     OrData
 299   );
 300
 301 /**
 302   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 303   AND, and writes the result back to the bit field in the 8-bit register.
 304
 305   Reads the 8-bit PCI configuration register specified by Address, performs a
 306   bitwise AND between the read result and the value specified by AndData, and
 307   writes the result to the 8-bit PCI configuration register specified by
 308   Address. The value written to the PCI configuration register is returned.
 309   This function must guarantee that all PCI read and write operations are
 310   serialized. Extra left bits in AndData are stripped.
 311
 312   If any reserved bits in Address are set, then ASSERT().
 313   If StartBit is greater than 7, then ASSERT().
 314   If EndBit is greater than 7, then ASSERT().
 315   If EndBit is less than StartBit, then ASSERT().
 316
 317   @param  Address   PCI configuration register to write.
 318   @param  StartBit  The ordinal of the least significant bit in the bit field.
 319                     Range 0..7.
 320   @param  EndBit    The ordinal of the most significant bit in the bit field.
 321                     Range 0..7.
 322   @param  AndData   The value to AND with the PCI configuration register.
 323
 324   @return The value written back to the PCI configuration register.
 325
 326 **/
 327 UINT8
 328 EFIAPI
 329 PciSegmentBitFieldAnd8 (
 330   IN UINT64                    Address,
 331   IN UINTN                     StartBit,
 332   IN UINTN                     EndBit,
 333   IN UINT8                     AndData
 334   );
 335
 336 /**
 337   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 338   bitwise OR, and writes the result back to the bit field in the
 339   8-bit port.
 340
 341   Reads the 8-bit PCI configuration register specified by Address, performs a
 342   bitwise AND followed by a bitwise OR between the read result and
 343   the value specified by AndData, and writes the result to the 8-bit PCI
 344   configuration register specified by Address. The value written to the PCI
 345   configuration register is returned. This function must guarantee that all PCI
 346   read and write operations are serialized. Extra left bits in both AndData and
 347   OrData are stripped.
 348
 349   If any reserved bits in Address are set, then ASSERT().
 350   If StartBit is greater than 7, then ASSERT().
 351   If EndBit is greater than 7, then ASSERT().
 352   If EndBit is less than StartBit, then ASSERT().
 353
 354   @param  Address   PCI configuration register to write.
 355   @param  StartBit  The ordinal of the least significant bit in the bit field.
 356                     Range 0..7.
 357   @param  EndBit    The ordinal of the most significant bit in the bit field.
 358                     Range 0..7.
 359   @param  AndData   The value to AND with the PCI configuration register.
 360   @param  OrData    The value to OR with the result of the AND operation.
 361
 362   @return The value written back to the PCI configuration register.
 363
 364 **/
 365 UINT8
 366 EFIAPI
 367 PciSegmentBitFieldAndThenOr8 (
 368   IN UINT64                    Address,
 369   IN UINTN                     StartBit,
 370   IN UINTN                     EndBit,
 371   IN UINT8                     AndData,
 372   IN UINT8                     OrData
 373   );
 374
 375 /**
 376   Reads a 16-bit PCI configuration register.
 377
 378   Reads and returns the 16-bit PCI configuration register specified by Address.
 379   This function must guarantee that all PCI read and write operations are serialized.
 380
 381   If any reserved bits in Address are set, then ASSERT().
 382   If Address is not aligned on a 16-bit boundary, then ASSERT().
 383
 384   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 385
 386   @return The 16-bit PCI configuration register specified by Address.
 387
 388 **/
 389 UINT16
 390 EFIAPI
 391 PciSegmentRead16 (
 392   IN UINT64                    Address
 393   );
 394
 395 /**
 396   Writes a 16-bit PCI configuration register.
 397
 398   Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
 399   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 400
 401   If any reserved bits in Address are set, then ASSERT().
 402   If Address is not aligned on a 16-bit boundary, then ASSERT().
 403
 404   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 405   @param  Value       The value to write.
 406
 407   @return The parameter of Value.
 408
 409 **/
 410 UINT16
 411 EFIAPI
 412 PciSegmentWrite16 (
 413   IN UINT64                    Address,
 414   IN UINT16                    Value
 415   );
 416
 417 /**
 418   Performs a bitwise OR of a 16-bit PCI configuration register with
 419   a 16-bit value.
 420
 421   Reads the 16-bit PCI configuration register specified by Address, performs a
 422   bitwise OR between the read result and the value specified by
 423   OrData, and writes the result to the 16-bit PCI configuration register
 424   specified by Address. The value written to the PCI configuration register is
 425   returned. This function must guarantee that all PCI read and write operations
 426   are serialized.
 427
 428   If any reserved bits in Address are set, then ASSERT().
 429   If Address is not aligned on a 16-bit boundary, then ASSERT().
 430
 431   @param  Address Address that encodes the PCI Segment, Bus, Device, Function and
 432                   Register.
 433   @param  OrData  The value to OR with the PCI configuration register.
 434
 435   @return The value written back to the PCI configuration register.
 436
 437 **/
 438 UINT16
 439 EFIAPI
 440 PciSegmentOr16 (
 441   IN UINT64                    Address,
 442   IN UINT16                    OrData
 443   );
 444
 445 /**
 446   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
 447
 448   Reads the 16-bit PCI configuration register specified by Address,
 449   performs a bitwise AND between the read result and the value specified by AndData,
 450   and writes the result to the 16-bit PCI configuration register specified by Address.
 451   The value written to the PCI configuration register is returned.
 452   This function must guarantee that all PCI read and write operations are serialized.
 453
 454   If any reserved bits in Address are set, then ASSERT().
 455   If Address is not aligned on a 16-bit boundary, then ASSERT().
 456
 457   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 458   @param  AndData   The value to AND with the PCI configuration register.
 459
 460   @return The value written to the PCI configuration register.
 461
 462 **/
 463 UINT16
 464 EFIAPI
 465 PciSegmentAnd16 (
 466   IN UINT64                    Address,
 467   IN UINT16                    AndData
 468   );
 469
 470 /**
 471   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
 472   followed a  bitwise OR with another 16-bit value.
 473
 474   Reads the 16-bit PCI configuration register specified by Address,
 475   performs a bitwise AND between the read result and the value specified by AndData,
 476   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
 477   and writes the result to the 16-bit PCI configuration register specified by Address.
 478   The value written to the PCI configuration register is returned.
 479   This function must guarantee that all PCI read and write operations are serialized.
 480
 481   If any reserved bits in Address are set, then ASSERT().
 482   If Address is not aligned on a 16-bit boundary, then ASSERT().
 483
 484   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 485   @param  AndData    The value to AND with the PCI configuration register.
 486   @param  OrData    The value to OR with the PCI configuration register.
 487
 488   @return The value written to the PCI configuration register.
 489
 490 **/
 491 UINT16
 492 EFIAPI
 493 PciSegmentAndThenOr16 (
 494   IN UINT64                    Address,
 495   IN UINT16                    AndData,
 496   IN UINT16                    OrData
 497   );
 498
 499 /**
 500   Reads a bit field of a PCI configuration register.
 501
 502   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 503   specified by the StartBit and the EndBit. The value of the bit field is
 504   returned.
 505
 506   If any reserved bits in Address are set, then ASSERT().
 507   If Address is not aligned on a 16-bit boundary, then ASSERT().
 508   If StartBit is greater than 15, then ASSERT().
 509   If EndBit is greater than 15, then ASSERT().
 510   If EndBit is less than StartBit, then ASSERT().
 511
 512   @param  Address   PCI configuration register to read.
 513   @param  StartBit  The ordinal of the least significant bit in the bit field.
 514                     Range 0..15.
 515   @param  EndBit    The ordinal of the most significant bit in the bit field.
 516                     Range 0..15.
 517
 518   @return The value of the bit field read from the PCI configuration register.
 519
 520 **/
 521 UINT16
 522 EFIAPI
 523 PciSegmentBitFieldRead16 (
 524   IN UINT64                    Address,
 525   IN UINTN                     StartBit,
 526   IN UINTN                     EndBit
 527   );
 528
 529 /**
 530   Writes a bit field to a PCI configuration register.
 531
 532   Writes Value to the bit field of the PCI configuration register. The bit
 533   field is specified by the StartBit and the EndBit. All other bits in the
 534   destination PCI configuration register are preserved. The new value of the
 535   16-bit register is returned.
 536
 537   If any reserved bits in Address are set, then ASSERT().
 538   If Address is not aligned on a 16-bit boundary, then ASSERT().
 539   If StartBit is greater than 15, then ASSERT().
 540   If EndBit is greater than 15, then ASSERT().
 541   If EndBit is less than StartBit, then ASSERT().
 542
 543   @param  Address   PCI configuration register to write.
 544   @param  StartBit  The ordinal of the least significant bit in the bit field.
 545                     Range 0..15.
 546   @param  EndBit    The ordinal of the most significant bit in the bit field.
 547                     Range 0..15.
 548   @param  Value     New value of the bit field.
 549
 550   @return The value written back to the PCI configuration register.
 551
 552 **/
 553 UINT16
 554 EFIAPI
 555 PciSegmentBitFieldWrite16 (
 556   IN UINT64                    Address,
 557   IN UINTN                     StartBit,
 558   IN UINTN                     EndBit,
 559   IN UINT16                    Value
 560   );
 561
 562 /**
 563   Reads the 16-bit PCI configuration register specified by Address,
 564   performs a bitwise OR between the read result and the value specified by OrData,
 565   and writes the result to the 16-bit PCI configuration register specified by Address.
 566
 567   If any reserved bits in Address are set, then ASSERT().
 568   If Address is not aligned on a 16-bit boundary, then ASSERT().
 569   If StartBit is greater than 15, then ASSERT().
 570   If EndBit is greater than 15, then ASSERT().
 571   If EndBit is less than StartBit, then ASSERT().
 572
 573   @param  Address   PCI configuration register to write.
 574   @param  StartBit  The ordinal of the least significant bit in the bit field.
 575                     Range 0..15.
 576   @param  EndBit    The ordinal of the most significant bit in the bit field.
 577                     Range 0..15.
 578   @param  OrData    The value to OR with the PCI configuration register.
 579
 580   @return The value written back to the PCI configuration register.
 581
 582 **/
 583 UINT16
 584 EFIAPI
 585 PciSegmentBitFieldOr16 (
 586   IN UINT64                    Address,
 587   IN UINTN                     StartBit,
 588   IN UINTN                     EndBit,
 589   IN UINT16                    OrData
 590   );
 591
 592 /**
 593   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
 594   and writes the result back to the bit field in the 16-bit port.
 595
 596   Reads the 16-bit PCI configuration register specified by Address,
 597   performs a bitwise OR between the read result and the value specified by OrData,
 598   and writes the result to the 16-bit PCI configuration register specified by Address.
 599   The value written to the PCI configuration register is returned.
 600   This function must guarantee that all PCI read and write operations are serialized.
 601   Extra left bits in OrData are stripped.
 602
 603   If any reserved bits in Address are set, then ASSERT().
 604   If Address is not aligned on a 16-bit boundary, then ASSERT().
 605   If StartBit is greater than 7, then ASSERT().
 606   If EndBit is greater than 7, then ASSERT().
 607   If EndBit is less than StartBit, then ASSERT().
 608
 609   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 610   @param  StartBit  The ordinal of the least significant bit in the bit field.
 611                     The ordinal of the least significant bit in a byte is bit 0.
 612   @param  EndBit    The ordinal of the most significant bit in the bit field.
 613                     The ordinal of the most significant bit in a byte is bit 7.
 614   @param  AndData   The value to AND with the read value from the PCI configuration register.
 615
 616   @return The value written to the PCI configuration register.
 617
 618 **/
 619 UINT16
 620 EFIAPI
 621 PciSegmentBitFieldAnd16 (
 622   IN UINT64                    Address,
 623   IN UINTN                     StartBit,
 624   IN UINTN                     EndBit,
 625   IN UINT16                    AndData
 626   );
 627
 628 /**
 629   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 630   bitwise OR, and writes the result back to the bit field in the
 631   16-bit port.
 632
 633   Reads the 16-bit PCI configuration register specified by Address, performs a
 634   bitwise AND followed by a bitwise OR between the read result and
 635   the value specified by AndData, and writes the result to the 16-bit PCI
 636   configuration register specified by Address. The value written to the PCI
 637   configuration register is returned. This function must guarantee that all PCI
 638   read and write operations are serialized. Extra left bits in both AndData and
 639   OrData are stripped.
 640
 641   If any reserved bits in Address are set, then ASSERT().
 642   If StartBit is greater than 15, then ASSERT().
 643   If EndBit is greater than 15, then ASSERT().
 644   If EndBit is less than StartBit, then ASSERT().
 645
 646   @param  Address   PCI configuration register to write.
 647   @param  StartBit  The ordinal of the least significant bit in the bit field.
 648                     Range 0..15.
 649   @param  EndBit    The ordinal of the most significant bit in the bit field.
 650                     Range 0..15.
 651   @param  AndData   The value to AND with the PCI configuration register.
 652   @param  OrData    The value to OR with the result of the AND operation.
 653
 654   @return The value written back to the PCI configuration register.
 655
 656 **/
 657 UINT16
 658 EFIAPI
 659 PciSegmentBitFieldAndThenOr16 (
 660   IN UINT64                    Address,
 661   IN UINTN                     StartBit,
 662   IN UINTN                     EndBit,
 663   IN UINT16                    AndData,
 664   IN UINT16                    OrData
 665   );
 666
 667 /**
 668   Reads a 32-bit PCI configuration register.
 669
 670   Reads and returns the 32-bit PCI configuration register specified by Address.
 671   This function must guarantee that all PCI read and write operations are serialized.
 672
 673   If any reserved bits in Address are set, then ASSERT().
 674   If Address is not aligned on a 32-bit boundary, then ASSERT().
 675
 676   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 677
 678   @return The 32-bit PCI configuration register specified by Address.
 679
 680 **/
 681 UINT32
 682 EFIAPI
 683 PciSegmentRead32 (
 684   IN UINT64                    Address
 685   );
 686
 687 /**
 688   Writes a 32-bit PCI configuration register.
 689
 690   Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
 691   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 692
 693   If any reserved bits in Address are set, then ASSERT().
 694   If Address is not aligned on a 32-bit boundary, then ASSERT().
 695
 696   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 697   @param  Value       The value to write.
 698
 699   @return The parameter of Value.
 700
 701 **/
 702 UINT32
 703 EFIAPI
 704 PciSegmentWrite32 (
 705   IN UINT64                    Address,
 706   IN UINT32                    Value
 707   );
 708
 709 /**
 710   Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
 711
 712   Reads the 32-bit PCI configuration register specified by Address,
 713   performs a bitwise OR between the read result and the value specified by OrData,
 714   and writes the result to the 32-bit PCI configuration register specified by Address.
 715   The value written to the PCI configuration register is returned.
 716   This function must guarantee that all PCI read and write operations are serialized.
 717
 718   If any reserved bits in Address are set, then ASSERT().
 719   If Address is not aligned on a 32-bit boundary, then ASSERT().
 720
 721   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 722   @param  OrData    The value to OR with the PCI configuration register.
 723
 724   @return The value written to the PCI configuration register.
 725
 726 **/
 727 UINT32
 728 EFIAPI
 729 PciSegmentOr32 (
 730   IN UINT64                    Address,
 731   IN UINT32                    OrData
 732   );
 733
 734 /**
 735   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
 736
 737   Reads the 32-bit PCI configuration register specified by Address,
 738   performs a bitwise AND between the read result and the value specified by AndData,
 739   and writes the result to the 32-bit PCI configuration register specified by Address.
 740   The value written to the PCI configuration register is returned.
 741   This function must guarantee that all PCI read and write operations are serialized.
 742
 743   If any reserved bits in Address are set, then ASSERT().
 744   If Address is not aligned on a 32-bit boundary, then ASSERT().
 745
 746   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 747   @param  AndData   The value to AND with the PCI configuration register.
 748
 749   @return The value written to the PCI configuration register.
 750
 751 **/
 752 UINT32
 753 EFIAPI
 754 PciSegmentAnd32 (
 755   IN UINT64                    Address,
 756   IN UINT32                    AndData
 757   );
 758
 759 /**
 760   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
 761   followed a  bitwise OR with another 32-bit value.
 762
 763   Reads the 32-bit PCI configuration register specified by Address,
 764   performs a bitwise AND between the read result and the value specified by AndData,
 765   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
 766   and writes the result to the 32-bit PCI configuration register specified by Address.
 767   The value written to the PCI configuration register is returned.
 768   This function must guarantee that all PCI read and write operations are serialized.
 769
 770   If any reserved bits in Address are set, then ASSERT().
 771   If Address is not aligned on a 32-bit boundary, then ASSERT().
 772
 773   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 774   @param  AndData   The value to AND with the PCI configuration register.
 775   @param  OrData    The value to OR with the PCI configuration register.
 776
 777   @return The value written to the PCI configuration register.
 778
 779 **/
 780 UINT32
 781 EFIAPI
 782 PciSegmentAndThenOr32 (
 783   IN UINT64                    Address,
 784   IN UINT32                    AndData,
 785   IN UINT32                    OrData
 786   );
 787
 788 /**
 789   Reads a bit field of a PCI configuration register.
 790
 791   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 792   specified by the StartBit and the EndBit. The value of the bit field is
 793   returned.
 794
 795   If any reserved bits in Address are set, then ASSERT().
 796   If Address is not aligned on a 32-bit boundary, then ASSERT().
 797   If StartBit is greater than 31, then ASSERT().
 798   If EndBit is greater than 31, then ASSERT().
 799   If EndBit is less than StartBit, then ASSERT().
 800
 801   @param  Address   PCI configuration register to read.
 802   @param  StartBit  The ordinal of the least significant bit in the bit field.
 803                     Range 0..31.
 804   @param  EndBit    The ordinal of the most significant bit in the bit field.
 805                     Range 0..31.
 806
 807   @return The value of the bit field read from the PCI configuration register.
 808
 809 **/
 810 UINT32
 811 EFIAPI
 812 PciSegmentBitFieldRead32 (
 813   IN UINT64                    Address,
 814   IN UINTN                     StartBit,
 815   IN UINTN                     EndBit
 816   );
 817
 818 /**
 819   Writes a bit field to a PCI configuration register.
 820
 821   Writes Value to the bit field of the PCI configuration register. The bit
 822   field is specified by the StartBit and the EndBit. All other bits in the
 823   destination PCI configuration register are preserved. The new value of the
 824   32-bit register is returned.
 825
 826   If any reserved bits in Address are set, then ASSERT().
 827   If Address is not aligned on a 32-bit boundary, then ASSERT().
 828   If StartBit is greater than 31, then ASSERT().
 829   If EndBit is greater than 31, then ASSERT().
 830   If EndBit is less than StartBit, then ASSERT().
 831
 832   @param  Address   PCI configuration register to write.
 833   @param  StartBit  The ordinal of the least significant bit in the bit field.
 834                     Range 0..31.
 835   @param  EndBit    The ordinal of the most significant bit in the bit field.
 836                     Range 0..31.
 837   @param  Value     New value of the bit field.
 838
 839   @return The value written back to the PCI configuration register.
 840
 841 **/
 842 UINT32
 843 EFIAPI
 844 PciSegmentBitFieldWrite32 (
 845   IN UINT64                    Address,
 846   IN UINTN                     StartBit,
 847   IN UINTN                     EndBit,
 848   IN UINT32                    Value
 849   );
 850
 851 /**
 852   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 853   writes the result back to the bit field in the 32-bit port.
 854
 855   Reads the 32-bit PCI configuration register specified by Address, performs a
 856   bitwise OR between the read result and the value specified by
 857   OrData, and writes the result to the 32-bit PCI configuration register
 858   specified by Address. The value written to the PCI configuration register is
 859   returned. This function must guarantee that all PCI read and write operations
 860   are serialized. Extra left bits in OrData are stripped.
 861
 862   If any reserved bits in Address are set, then ASSERT().
 863   If StartBit is greater than 31, then ASSERT().
 864   If EndBit is greater than 31, then ASSERT().
 865   If EndBit is less than StartBit, then ASSERT().
 866
 867   @param  Address   PCI configuration register to write.
 868   @param  StartBit  The ordinal of the least significant bit in the bit field.
 869                     Range 0..31.
 870   @param  EndBit    The ordinal of the most significant bit in the bit field.
 871                     Range 0..31.
 872   @param  OrData    The value to OR with the PCI configuration register.
 873
 874   @return The value written back to the PCI configuration register.
 875
 876 **/
 877 UINT32
 878 EFIAPI
 879 PciSegmentBitFieldOr32 (
 880   IN UINT64                    Address,
 881   IN UINTN                     StartBit,
 882   IN UINTN                     EndBit,
 883   IN UINT32                    OrData
 884   );
 885
 886 /**
 887   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 888   AND, and writes the result back to the bit field in the 32-bit register.
 889
 890
 891   Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
 892   AND between the read result and the value specified by AndData, and writes the result
 893   to the 32-bit PCI configuration register specified by Address. The value written to
 894   the PCI configuration register is returned.  This function must guarantee that all PCI
 895   read and write operations are serialized.  Extra left bits in AndData are stripped.
 896   If any reserved bits in Address are set, then ASSERT().
 897   If Address is not aligned on a 32-bit boundary, then ASSERT().
 898   If StartBit is greater than 31, then ASSERT().
 899   If EndBit is greater than 31, then ASSERT().
 900   If EndBit is less than StartBit, then ASSERT().
 901
 902
 903   @param  Address   PCI configuration register to write.
 904   @param  StartBit  The ordinal of the least significant bit in the bit field.
 905                     Range 0..31.
 906   @param  EndBit    The ordinal of the most significant bit in the bit field.
 907                     Range 0..31.
 908   @param  AndData   The value to AND with the PCI configuration register.
 909
 910   @return The value written back to the PCI configuration register.
 911
 912 **/
 913 UINT32
 914 EFIAPI
 915 PciSegmentBitFieldAnd32 (
 916   IN UINT64                    Address,
 917   IN UINTN                     StartBit,
 918   IN UINTN                     EndBit,
 919   IN UINT32                    AndData
 920   );
 921
 922 /**
 923   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 924   bitwise OR, and writes the result back to the bit field in the
 925   32-bit port.
 926
 927   Reads the 32-bit PCI configuration register specified by Address, performs a
 928   bitwise AND followed by a bitwise OR between the read result and
 929   the value specified by AndData, and writes the result to the 32-bit PCI
 930   configuration register specified by Address. The value written to the PCI
 931   configuration register is returned. This function must guarantee that all PCI
 932   read and write operations are serialized. Extra left bits in both AndData and
 933   OrData are stripped.
 934
 935   If any reserved bits in Address are set, then ASSERT().
 936   If StartBit is greater than 31, then ASSERT().
 937   If EndBit is greater than 31, then ASSERT().
 938   If EndBit is less than StartBit, then ASSERT().
 939
 940   @param  Address   PCI configuration register to write.
 941   @param  StartBit  The ordinal of the least significant bit in the bit field.
 942                     Range 0..31.
 943   @param  EndBit    The ordinal of the most significant bit in the bit field.
 944                     Range 0..31.
 945   @param  AndData   The value to AND with the PCI configuration register.
 946   @param  OrData    The value to OR with the result of the AND operation.
 947
 948   @return The value written back to the PCI configuration register.
 949
 950 **/
 951 UINT32
 952 EFIAPI
 953 PciSegmentBitFieldAndThenOr32 (
 954   IN UINT64                    Address,
 955   IN UINTN                     StartBit,
 956   IN UINTN                     EndBit,
 957   IN UINT32                    AndData,
 958   IN UINT32                    OrData
 959   );
 960
 961 /**
 962   Reads a range of PCI configuration registers into a caller supplied buffer.
 963
 964   Reads the range of PCI configuration registers specified by StartAddress and
 965   Size into the buffer specified by Buffer. This function only allows the PCI
 966   configuration registers from a single PCI function to be read. Size is
 967   returned. When possible 32-bit PCI configuration read cycles are used to read
 968   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
 969   and 16-bit PCI configuration read cycles may be used at the beginning and the
 970   end of the range.
 971
 972   If StartAddress > 0x0FFFFFFF, then ASSERT().
 973   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 974   If Size > 0 and Buffer is NULL, then ASSERT().
 975
 976   @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,
 977                         Function and Register.
 978   @param  Size          Size in bytes of the transfer.
 979   @param  Buffer        Pointer to a buffer receiving the data read.
 980
 981   @return Size
 982
 983 **/
 984 UINTN
 985 EFIAPI
 986 PciSegmentReadBuffer (
 987   IN  UINT64                   StartAddress,
 988   IN  UINTN                    Size,
 989   OUT VOID                     *Buffer
 990   );
 991
 992 /**
 993   Copies the data in a caller supplied buffer to a specified range of PCI
 994   configuration space.
 995
 996   Writes the range of PCI configuration registers specified by StartAddress and
 997   Size from the buffer specified by Buffer. This function only allows the PCI
 998   configuration registers from a single PCI function to be written. Size is
 999   returned. When possible 32-bit PCI configuration write cycles are used to
1000   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1001   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1002   and the end of the range.
1003
1004   If StartAddress > 0x0FFFFFFF, then ASSERT().
1005   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1006   If Size > 0 and Buffer is NULL, then ASSERT().
1007
1008   @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,
1009                         Function and Register.
1010   @param  Size          Size in bytes of the transfer.
1011   @param  Buffer        Pointer to a buffer containing the data to write.
1012
1013   @return The parameter of Size.
1014
1015 **/
1016 UINTN
1017 EFIAPI
1018 PciSegmentWriteBuffer (
1019   IN UINT64                    StartAddress,
1020   IN UINTN                     Size,
1021   IN VOID                      *Buffer
1022   );
1023
1024 #endif