MdePkg/Include/Library/PciSegmentLib.h

   1 /** @file
   2   Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
   3
   4   The PCI Segment Library function provide services to read, write, and modify the PCI configuration
   5   registers on PCI root bridges on any supported PCI segment.  These library services take a single
   6   address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.
   7   The layout of this address parameter is as follows:
   8
   9             PCI Register: Bits 0..11
  10             PCI Function  Bits 12..14
  11             PCI Device  Bits 15..19
  12             PCI Bus Bits 20..27
  13             Reserved  Bits 28..31.  Must be 0.
  14             PCI Segment Bits 32..47
  15             Reserved  Bits 48..63.  Must be 0.
  16
  17   | Reserved (MBZ) | Segment | Reserved (MBZ) |     Bus     | Device | Function | Register |
  18   63             48  47    32  31           28 27         20 19    15 14      12 11         0
  19
  20   These functions perform PCI configuration cycles using the default PCI configuration access
  21   method.  This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
  22   may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate
  23   access method.  Modules will typically use the PCI Segment Library for its PCI configuration
  24   accesses when PCI Segments other than Segment #0 must be accessed.
  25
  26 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
  27 SPDX-License-Identifier: BSD-2-Clause-Patent
  28
  29 **/
  30
  31 #ifndef __PCI_SEGMENT_LIB__
  32 #define __PCI_SEGMENT_LIB__
  33
  34
  35 /**
  36   Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
  37   and PCI Register to an address that can be passed to the PCI Segment Library functions.
  38
  39   Computes an address that is compatible with the PCI Segment Library functions.
  40   The unused upper bits of Segment, Bus, Device, Function,
  41   and Register are stripped prior to the generation of the address.
  42
  43   @param  Segment   PCI Segment number.  Range 0..65535.
  44   @param  Bus       PCI Bus number.  Range 0..255.
  45   @param  Device    PCI Device number.  Range 0..31.
  46   @param  Function  PCI Function number.  Range 0..7.
  47   @param  Register  PCI Register number.  Range 0..255 for PCI.  Range 0..4095 for PCI Express.
  48
  49   @return The address that is compatible with the PCI Segment Library functions.
  50
  51 **/
  52 #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \
  53   ((Segment != 0) ? \
  54     ( ((Register) & 0xfff)                 | \
  55       (((Function) & 0x07) << 12)          | \
  56       (((Device) & 0x1f) << 15)            | \
  57       (((Bus) & 0xff) << 20)               | \
  58       (LShiftU64 ((Segment) & 0xffff, 32))   \
  59     ) :                                      \
  60     ( ((Register) & 0xfff)                 | \
  61       (((Function) & 0x07) << 12)          | \
  62       (((Device) & 0x1f) << 15)            | \
  63       (((Bus) & 0xff) << 20)                 \
  64     )                                        \
  65   )
  66
  67 /**
  68   Register a PCI device so PCI configuration registers may be accessed after
  69   SetVirtualAddressMap().
  70
  71   If any reserved bits in Address are set, then ASSERT().
  72
  73   @param  Address Address that encodes the PCI Bus, Device, Function and
  74                   Register.
  75
  76   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
  77   @retval RETURN_UNSUPPORTED       An attempt was made to call this function
  78                                    after ExitBootServices().
  79   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
  80                                    at runtime could not be mapped.
  81   @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to
  82                                    complete the registration.
  83
  84 **/
  85 RETURN_STATUS
  86 EFIAPI
  87 PciSegmentRegisterForRuntimeAccess (
  88   IN UINTN  Address
  89   );
  90
  91 /**
  92   Reads an 8-bit PCI configuration register.
  93
  94   Reads and returns the 8-bit PCI configuration register specified by Address.
  95   This function must guarantee that all PCI read and write operations are serialized.
  96
  97   If any reserved bits in Address are set, then ASSERT().
  98
  99   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 100
 101   @return The 8-bit PCI configuration register specified by Address.
 102
 103 **/
 104 UINT8
 105 EFIAPI
 106 PciSegmentRead8 (
 107   IN UINT64                    Address
 108   );
 109
 110 /**
 111   Writes an 8-bit PCI configuration register.
 112
 113   Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
 114   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 115
 116   If any reserved bits in Address are set, then ASSERT().
 117
 118   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 119   @param  Value       The value to write.
 120
 121   @return The value written to the PCI configuration register.
 122
 123 **/
 124 UINT8
 125 EFIAPI
 126 PciSegmentWrite8 (
 127   IN UINT64                    Address,
 128   IN UINT8                     Value
 129   );
 130
 131 /**
 132   Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
 133
 134   Reads the 8-bit PCI configuration register specified by Address,
 135   performs a bitwise OR between the read result and the value specified by OrData,
 136   and writes the result to the 8-bit PCI configuration register specified by Address.
 137   The value written to the PCI configuration register is returned.
 138   This function must guarantee that all PCI read and write operations are serialized.
 139
 140   If any reserved bits in Address are set, then ASSERT().
 141
 142   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 143   @param  OrData    The value to OR with the PCI configuration register.
 144
 145   @return The value written to the PCI configuration register.
 146
 147 **/
 148 UINT8
 149 EFIAPI
 150 PciSegmentOr8 (
 151   IN UINT64                    Address,
 152   IN UINT8                     OrData
 153   );
 154
 155 /**
 156   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
 157
 158   Reads the 8-bit PCI configuration register specified by Address,
 159   performs a bitwise AND between the read result and the value specified by AndData,
 160   and writes the result to the 8-bit PCI configuration register specified by Address.
 161   The value written to the PCI configuration register is returned.
 162   This function must guarantee that all PCI read and write operations are serialized.
 163   If any reserved bits in Address are set, then ASSERT().
 164
 165   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 166   @param  AndData   The value to AND with the PCI configuration register.
 167
 168   @return The value written to the PCI configuration register.
 169
 170 **/
 171 UINT8
 172 EFIAPI
 173 PciSegmentAnd8 (
 174   IN UINT64                    Address,
 175   IN UINT8                     AndData
 176   );
 177
 178 /**
 179   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
 180   followed a  bitwise OR with another 8-bit value.
 181
 182   Reads the 8-bit PCI configuration register specified by Address,
 183   performs a bitwise AND between the read result and the value specified by AndData,
 184   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
 185   and writes the result to the 8-bit PCI configuration register specified by Address.
 186   The value written to the PCI configuration register is returned.
 187   This function must guarantee that all PCI read and write operations are serialized.
 188
 189   If any reserved bits in Address are set, then ASSERT().
 190
 191   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 192   @param  AndData   The value to AND with the PCI configuration register.
 193   @param  OrData    The value to OR with the PCI configuration register.
 194
 195   @return The value written to the PCI configuration register.
 196
 197 **/
 198 UINT8
 199 EFIAPI
 200 PciSegmentAndThenOr8 (
 201   IN UINT64                    Address,
 202   IN UINT8                     AndData,
 203   IN UINT8                     OrData
 204   );
 205
 206 /**
 207   Reads a bit field of a PCI configuration register.
 208
 209   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 210   specified by the StartBit and the EndBit. The value of the bit field is
 211   returned.
 212
 213   If any reserved bits in Address are set, then ASSERT().
 214   If StartBit is greater than 7, then ASSERT().
 215   If EndBit is greater than 7, then ASSERT().
 216   If EndBit is less than StartBit, then ASSERT().
 217
 218   @param  Address   PCI configuration register to read.
 219   @param  StartBit  The ordinal of the least significant bit in the bit field.
 220                     Range 0..7.
 221   @param  EndBit    The ordinal of the most significant bit in the bit field.
 222                     Range 0..7.
 223
 224   @return The value of the bit field read from the PCI configuration register.
 225
 226 **/
 227 UINT8
 228 EFIAPI
 229 PciSegmentBitFieldRead8 (
 230   IN UINT64                    Address,
 231   IN UINTN                     StartBit,
 232   IN UINTN                     EndBit
 233   );
 234
 235 /**
 236   Writes a bit field to a PCI configuration register.
 237
 238   Writes Value to the bit field of the PCI configuration register. The bit
 239   field is specified by the StartBit and the EndBit. All other bits in the
 240   destination PCI configuration register are preserved. The new value of the
 241   8-bit register is returned.
 242
 243   If any reserved bits in Address are set, then ASSERT().
 244   If StartBit is greater than 7, then ASSERT().
 245   If EndBit is greater than 7, then ASSERT().
 246   If EndBit is less than StartBit, then ASSERT().
 247   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 248
 249   @param  Address   PCI configuration register to write.
 250   @param  StartBit  The ordinal of the least significant bit in the bit field.
 251                     Range 0..7.
 252   @param  EndBit    The ordinal of the most significant bit in the bit field.
 253                     Range 0..7.
 254   @param  Value     New value of the bit field.
 255
 256   @return The value written back to the PCI configuration register.
 257
 258 **/
 259 UINT8
 260 EFIAPI
 261 PciSegmentBitFieldWrite8 (
 262   IN UINT64                    Address,
 263   IN UINTN                     StartBit,
 264   IN UINTN                     EndBit,
 265   IN UINT8                     Value
 266   );
 267
 268 /**
 269   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 270   writes the result back to the bit field in the 8-bit port.
 271
 272   Reads the 8-bit PCI configuration register specified by Address, performs a
 273   bitwise OR between the read result and the value specified by
 274   OrData, and writes the result to the 8-bit PCI configuration register
 275   specified by Address. The value written to the PCI configuration register is
 276   returned. This function must guarantee that all PCI read and write operations
 277   are serialized. Extra left bits in OrData are stripped.
 278
 279   If any reserved bits in Address are set, then ASSERT().
 280   If StartBit is greater than 7, then ASSERT().
 281   If EndBit is greater than 7, then ASSERT().
 282   If EndBit is less than StartBit, then ASSERT().
 283   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 284
 285   @param  Address   PCI configuration register to write.
 286   @param  StartBit  The ordinal of the least significant bit in the bit field.
 287                     Range 0..7.
 288   @param  EndBit    The ordinal of the most significant bit in the bit field.
 289                     Range 0..7.
 290   @param  OrData    The value to OR with the PCI configuration register.
 291
 292   @return The value written back to the PCI configuration register.
 293
 294 **/
 295 UINT8
 296 EFIAPI
 297 PciSegmentBitFieldOr8 (
 298   IN UINT64                    Address,
 299   IN UINTN                     StartBit,
 300   IN UINTN                     EndBit,
 301   IN UINT8                     OrData
 302   );
 303
 304 /**
 305   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 306   AND, and writes the result back to the bit field in the 8-bit register.
 307
 308   Reads the 8-bit PCI configuration register specified by Address, performs a
 309   bitwise AND between the read result and the value specified by AndData, and
 310   writes the result to the 8-bit PCI configuration register specified by
 311   Address. The value written to the PCI configuration register is returned.
 312   This function must guarantee that all PCI read and write operations are
 313   serialized. Extra left bits in AndData are stripped.
 314
 315   If any reserved bits in Address are set, then ASSERT().
 316   If StartBit is greater than 7, then ASSERT().
 317   If EndBit is greater than 7, then ASSERT().
 318   If EndBit is less than StartBit, then ASSERT().
 319   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 320
 321   @param  Address   PCI configuration register to write.
 322   @param  StartBit  The ordinal of the least significant bit in the bit field.
 323                     Range 0..7.
 324   @param  EndBit    The ordinal of the most significant bit in the bit field.
 325                     Range 0..7.
 326   @param  AndData   The value to AND with the PCI configuration register.
 327
 328   @return The value written back to the PCI configuration register.
 329
 330 **/
 331 UINT8
 332 EFIAPI
 333 PciSegmentBitFieldAnd8 (
 334   IN UINT64                    Address,
 335   IN UINTN                     StartBit,
 336   IN UINTN                     EndBit,
 337   IN UINT8                     AndData
 338   );
 339
 340 /**
 341   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 342   bitwise OR, and writes the result back to the bit field in the 8-bit port.
 343
 344   Reads the 8-bit PCI configuration register specified by Address, performs a
 345   bitwise AND followed by a bitwise OR between the read result and
 346   the value specified by AndData, and writes the result to the 8-bit PCI
 347   configuration register specified by Address. The value written to the PCI
 348   configuration register is returned. This function must guarantee that all PCI
 349   read and write operations are serialized. Extra left bits in both AndData and
 350   OrData are stripped.
 351
 352   If any reserved bits in Address are set, then ASSERT().
 353   If StartBit is greater than 7, then ASSERT().
 354   If EndBit is greater than 7, then ASSERT().
 355   If EndBit is less than StartBit, then ASSERT().
 356   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 357   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 358
 359   @param  Address   PCI configuration register to write.
 360   @param  StartBit  The ordinal of the least significant bit in the bit field.
 361                     Range 0..7.
 362   @param  EndBit    The ordinal of the most significant bit in the bit field.
 363                     Range 0..7.
 364   @param  AndData   The value to AND with the PCI configuration register.
 365   @param  OrData    The value to OR with the result of the AND operation.
 366
 367   @return The value written back to the PCI configuration register.
 368
 369 **/
 370 UINT8
 371 EFIAPI
 372 PciSegmentBitFieldAndThenOr8 (
 373   IN UINT64                    Address,
 374   IN UINTN                     StartBit,
 375   IN UINTN                     EndBit,
 376   IN UINT8                     AndData,
 377   IN UINT8                     OrData
 378   );
 379
 380 /**
 381   Reads a 16-bit PCI configuration register.
 382
 383   Reads and returns the 16-bit PCI configuration register specified by Address.
 384   This function must guarantee that all PCI read and write operations are serialized.
 385
 386   If any reserved bits in Address are set, then ASSERT().
 387   If Address is not aligned on a 16-bit boundary, then ASSERT().
 388
 389   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 390
 391   @return The 16-bit PCI configuration register specified by Address.
 392
 393 **/
 394 UINT16
 395 EFIAPI
 396 PciSegmentRead16 (
 397   IN UINT64                    Address
 398   );
 399
 400 /**
 401   Writes a 16-bit PCI configuration register.
 402
 403   Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
 404   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 405
 406   If any reserved bits in Address are set, then ASSERT().
 407   If Address is not aligned on a 16-bit boundary, then ASSERT().
 408
 409   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 410   @param  Value       The value to write.
 411
 412   @return The parameter of Value.
 413
 414 **/
 415 UINT16
 416 EFIAPI
 417 PciSegmentWrite16 (
 418   IN UINT64                    Address,
 419   IN UINT16                    Value
 420   );
 421
 422 /**
 423   Performs a bitwise OR of a 16-bit PCI configuration register with
 424   a 16-bit value.
 425
 426   Reads the 16-bit PCI configuration register specified by Address, performs a
 427   bitwise OR between the read result and the value specified by OrData, and
 428   writes the result to the 16-bit PCI configuration register specified by Address.
 429   The value written to the PCI configuration register is returned. This function
 430   must guarantee that all PCI read and write operations are serialized.
 431
 432   If any reserved bits in Address are set, then ASSERT().
 433   If Address is not aligned on a 16-bit boundary, then ASSERT().
 434
 435   @param  Address Address that encodes the PCI Segment, Bus, Device, Function and
 436                   Register.
 437   @param  OrData  The value to OR with the PCI configuration register.
 438
 439   @return The value written back to the PCI configuration register.
 440
 441 **/
 442 UINT16
 443 EFIAPI
 444 PciSegmentOr16 (
 445   IN UINT64                    Address,
 446   IN UINT16                    OrData
 447   );
 448
 449 /**
 450   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
 451
 452   Reads the 16-bit PCI configuration register specified by Address,
 453   performs a bitwise AND between the read result and the value specified by AndData,
 454   and writes the result to the 16-bit PCI configuration register specified by Address.
 455   The value written to the PCI configuration register is returned.
 456   This function must guarantee that all PCI read and write operations are serialized.
 457
 458   If any reserved bits in Address are set, then ASSERT().
 459   If Address is not aligned on a 16-bit boundary, then ASSERT().
 460
 461   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 462   @param  AndData   The value to AND with the PCI configuration register.
 463
 464   @return The value written to the PCI configuration register.
 465
 466 **/
 467 UINT16
 468 EFIAPI
 469 PciSegmentAnd16 (
 470   IN UINT64                    Address,
 471   IN UINT16                    AndData
 472   );
 473
 474 /**
 475   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
 476   followed a  bitwise OR with another 16-bit value.
 477
 478   Reads the 16-bit PCI configuration register specified by Address,
 479   performs a bitwise AND between the read result and the value specified by AndData,
 480   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
 481   and writes the result to the 16-bit PCI configuration register specified by Address.
 482   The value written to the PCI configuration register is returned.
 483   This function must guarantee that all PCI read and write operations are serialized.
 484
 485   If any reserved bits in Address are set, then ASSERT().
 486   If Address is not aligned on a 16-bit boundary, then ASSERT().
 487
 488   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 489   @param  AndData   The value to AND with the PCI configuration register.
 490   @param  OrData    The value to OR with the PCI configuration register.
 491
 492   @return The value written to the PCI configuration register.
 493
 494 **/
 495 UINT16
 496 EFIAPI
 497 PciSegmentAndThenOr16 (
 498   IN UINT64                    Address,
 499   IN UINT16                    AndData,
 500   IN UINT16                    OrData
 501   );
 502
 503 /**
 504   Reads a bit field of a PCI configuration register.
 505
 506   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 507   specified by the StartBit and the EndBit. The value of the bit field is
 508   returned.
 509
 510   If any reserved bits in Address are set, then ASSERT().
 511   If Address is not aligned on a 16-bit boundary, then ASSERT().
 512   If StartBit is greater than 15, then ASSERT().
 513   If EndBit is greater than 15, then ASSERT().
 514   If EndBit is less than StartBit, then ASSERT().
 515
 516   @param  Address   PCI configuration register to read.
 517   @param  StartBit  The ordinal of the least significant bit in the bit field.
 518                     Range 0..15.
 519   @param  EndBit    The ordinal of the most significant bit in the bit field.
 520                     Range 0..15.
 521
 522   @return The value of the bit field read from the PCI configuration register.
 523
 524 **/
 525 UINT16
 526 EFIAPI
 527 PciSegmentBitFieldRead16 (
 528   IN UINT64                    Address,
 529   IN UINTN                     StartBit,
 530   IN UINTN                     EndBit
 531   );
 532
 533 /**
 534   Writes a bit field to a PCI configuration register.
 535
 536   Writes Value to the bit field of the PCI configuration register. The bit
 537   field is specified by the StartBit and the EndBit. All other bits in the
 538   destination PCI configuration register are preserved. The new value of the
 539   16-bit register is returned.
 540
 541   If any reserved bits in Address are set, then ASSERT().
 542   If Address is not aligned on a 16-bit boundary, then ASSERT().
 543   If StartBit is greater than 15, then ASSERT().
 544   If EndBit is greater than 15, then ASSERT().
 545   If EndBit is less than StartBit, then ASSERT().
 546   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 547
 548   @param  Address   PCI configuration register to write.
 549   @param  StartBit  The ordinal of the least significant bit in the bit field.
 550                     Range 0..15.
 551   @param  EndBit    The ordinal of the most significant bit in the bit field.
 552                     Range 0..15.
 553   @param  Value     New value of the bit field.
 554
 555   @return The value written back to the PCI configuration register.
 556
 557 **/
 558 UINT16
 559 EFIAPI
 560 PciSegmentBitFieldWrite16 (
 561   IN UINT64                    Address,
 562   IN UINTN                     StartBit,
 563   IN UINTN                     EndBit,
 564   IN UINT16                    Value
 565   );
 566
 567 /**
 568   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
 569   the result back to the bit field in the 16-bit port.
 570
 571   Reads the 16-bit PCI configuration register specified by Address, performs a
 572   bitwise OR between the read result and the value specified by
 573   OrData, and writes the result to the 16-bit PCI configuration register
 574   specified by Address. The value written to the PCI configuration register is
 575   returned. This function must guarantee that all PCI read and write operations
 576   are serialized. Extra left bits in OrData are stripped.
 577
 578   If any reserved bits in Address are set, then ASSERT().
 579   If Address is not aligned on a 16-bit boundary, then ASSERT().
 580   If StartBit is greater than 15, then ASSERT().
 581   If EndBit is greater than 15, then ASSERT().
 582   If EndBit is less than StartBit, then ASSERT().
 583   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 584
 585   @param  Address   PCI configuration register to write.
 586   @param  StartBit  The ordinal of the least significant bit in the bit field.
 587                     Range 0..15.
 588   @param  EndBit    The ordinal of the most significant bit in the bit field.
 589                     Range 0..15.
 590   @param  OrData    The value to OR with the PCI configuration register.
 591
 592   @return The value written back to the PCI configuration register.
 593
 594 **/
 595 UINT16
 596 EFIAPI
 597 PciSegmentBitFieldOr16 (
 598   IN UINT64                    Address,
 599   IN UINTN                     StartBit,
 600   IN UINTN                     EndBit,
 601   IN UINT16                    OrData
 602   );
 603
 604 /**
 605   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 606   AND, writes the result back to the bit field in the 16-bit register.
 607
 608   Reads the 16-bit PCI configuration register specified by Address, performs a
 609   bitwise AND between the read result and the value specified by AndData, and
 610   writes the result to the 16-bit PCI configuration register specified by
 611   Address. The value written to the PCI configuration register is returned.
 612   This function must guarantee that all PCI read and write operations are
 613   serialized. Extra left bits in AndData are stripped.
 614
 615   If any reserved bits in Address are set, then ASSERT().
 616   If Address is not aligned on a 16-bit boundary, then ASSERT().
 617   If StartBit is greater than 15, then ASSERT().
 618   If EndBit is greater than 15, then ASSERT().
 619   If EndBit is less than StartBit, then ASSERT().
 620   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 621
 622   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 623   @param  StartBit  The ordinal of the least significant bit in the bit field.
 624                     Range 0..15.
 625   @param  EndBit    The ordinal of the most significant bit in the bit field.
 626                     Range 0..15.
 627   @param  AndData   The value to AND with the PCI configuration register.
 628
 629   @return The value written back to the PCI configuration register.
 630
 631 **/
 632 UINT16
 633 EFIAPI
 634 PciSegmentBitFieldAnd16 (
 635   IN UINT64                    Address,
 636   IN UINTN                     StartBit,
 637   IN UINTN                     EndBit,
 638   IN UINT16                    AndData
 639   );
 640
 641 /**
 642   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 643   bitwise OR, and writes the result back to the bit field in the
 644   16-bit port.
 645
 646   Reads the 16-bit PCI configuration register specified by Address, performs a
 647   bitwise AND followed by a bitwise OR between the read result and
 648   the value specified by AndData, and writes the result to the 16-bit PCI
 649   configuration register specified by Address. The value written to the PCI
 650   configuration register is returned. This function must guarantee that all PCI
 651   read and write operations are serialized. Extra left bits in both AndData and
 652   OrData are stripped.
 653
 654   If any reserved bits in Address are set, then ASSERT().
 655   If StartBit is greater than 15, then ASSERT().
 656   If EndBit is greater than 15, then ASSERT().
 657   If EndBit is less than StartBit, then ASSERT().
 658   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 659   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 660
 661   @param  Address   PCI configuration register to write.
 662   @param  StartBit  The ordinal of the least significant bit in the bit field.
 663                     Range 0..15.
 664   @param  EndBit    The ordinal of the most significant bit in the bit field.
 665                     Range 0..15.
 666   @param  AndData   The value to AND with the PCI configuration register.
 667   @param  OrData    The value to OR with the result of the AND operation.
 668
 669   @return The value written back to the PCI configuration register.
 670
 671 **/
 672 UINT16
 673 EFIAPI
 674 PciSegmentBitFieldAndThenOr16 (
 675   IN UINT64                    Address,
 676   IN UINTN                     StartBit,
 677   IN UINTN                     EndBit,
 678   IN UINT16                    AndData,
 679   IN UINT16                    OrData
 680   );
 681
 682 /**
 683   Reads a 32-bit PCI configuration register.
 684
 685   Reads and returns the 32-bit PCI configuration register specified by Address.
 686   This function must guarantee that all PCI read and write operations are serialized.
 687
 688   If any reserved bits in Address are set, then ASSERT().
 689   If Address is not aligned on a 32-bit boundary, then ASSERT().
 690
 691   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 692
 693   @return The 32-bit PCI configuration register specified by Address.
 694
 695 **/
 696 UINT32
 697 EFIAPI
 698 PciSegmentRead32 (
 699   IN UINT64                    Address
 700   );
 701
 702 /**
 703   Writes a 32-bit PCI configuration register.
 704
 705   Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
 706   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 707
 708   If any reserved bits in Address are set, then ASSERT().
 709   If Address is not aligned on a 32-bit boundary, then ASSERT().
 710
 711   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 712   @param  Value       The value to write.
 713
 714   @return The parameter of Value.
 715
 716 **/
 717 UINT32
 718 EFIAPI
 719 PciSegmentWrite32 (
 720   IN UINT64                    Address,
 721   IN UINT32                    Value
 722   );
 723
 724 /**
 725   Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
 726
 727   Reads the 32-bit PCI configuration register specified by Address,
 728   performs a bitwise OR between the read result and the value specified by OrData,
 729   and writes the result to the 32-bit PCI configuration register specified by Address.
 730   The value written to the PCI configuration register is returned.
 731   This function must guarantee that all PCI read and write operations are serialized.
 732
 733   If any reserved bits in Address are set, then ASSERT().
 734   If Address is not aligned on a 32-bit boundary, then ASSERT().
 735
 736   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 737   @param  OrData    The value to OR with the PCI configuration register.
 738
 739   @return The value written to the PCI configuration register.
 740
 741 **/
 742 UINT32
 743 EFIAPI
 744 PciSegmentOr32 (
 745   IN UINT64                    Address,
 746   IN UINT32                    OrData
 747   );
 748
 749 /**
 750   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
 751
 752   Reads the 32-bit PCI configuration register specified by Address,
 753   performs a bitwise AND between the read result and the value specified by AndData,
 754   and writes the result to the 32-bit PCI configuration register specified by Address.
 755   The value written to the PCI configuration register is returned.
 756   This function must guarantee that all PCI read and write operations are serialized.
 757
 758   If any reserved bits in Address are set, then ASSERT().
 759   If Address is not aligned on a 32-bit boundary, then ASSERT().
 760
 761   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 762   @param  AndData   The value to AND with the PCI configuration register.
 763
 764   @return The value written to the PCI configuration register.
 765
 766 **/
 767 UINT32
 768 EFIAPI
 769 PciSegmentAnd32 (
 770   IN UINT64                    Address,
 771   IN UINT32                    AndData
 772   );
 773
 774 /**
 775   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
 776   followed a  bitwise OR with another 32-bit value.
 777
 778   Reads the 32-bit PCI configuration register specified by Address,
 779   performs a bitwise AND between the read result and the value specified by AndData,
 780   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
 781   and writes the result to the 32-bit PCI configuration register specified by Address.
 782   The value written to the PCI configuration register is returned.
 783   This function must guarantee that all PCI read and write operations are serialized.
 784
 785   If any reserved bits in Address are set, then ASSERT().
 786   If Address is not aligned on a 32-bit boundary, then ASSERT().
 787
 788   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 789   @param  AndData   The value to AND with the PCI configuration register.
 790   @param  OrData    The value to OR with the PCI configuration register.
 791
 792   @return The value written to the PCI configuration register.
 793
 794 **/
 795 UINT32
 796 EFIAPI
 797 PciSegmentAndThenOr32 (
 798   IN UINT64                    Address,
 799   IN UINT32                    AndData,
 800   IN UINT32                    OrData
 801   );
 802
 803 /**
 804   Reads a bit field of a PCI configuration register.
 805
 806   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 807   specified by the StartBit and the EndBit. The value of the bit field is
 808   returned.
 809
 810   If any reserved bits in Address are set, then ASSERT().
 811   If Address is not aligned on a 32-bit boundary, then ASSERT().
 812   If StartBit is greater than 31, then ASSERT().
 813   If EndBit is greater than 31, then ASSERT().
 814   If EndBit is less than StartBit, then ASSERT().
 815
 816   @param  Address   PCI configuration register to read.
 817   @param  StartBit  The ordinal of the least significant bit in the bit field.
 818                     Range 0..31.
 819   @param  EndBit    The ordinal of the most significant bit in the bit field.
 820                     Range 0..31.
 821
 822   @return The value of the bit field read from the PCI configuration register.
 823
 824 **/
 825 UINT32
 826 EFIAPI
 827 PciSegmentBitFieldRead32 (
 828   IN UINT64                    Address,
 829   IN UINTN                     StartBit,
 830   IN UINTN                     EndBit
 831   );
 832
 833 /**
 834   Writes a bit field to a PCI configuration register.
 835
 836   Writes Value to the bit field of the PCI configuration register. The bit
 837   field is specified by the StartBit and the EndBit. All other bits in the
 838   destination PCI configuration register are preserved. The new value of the
 839   32-bit register is returned.
 840
 841   If any reserved bits in Address are set, then ASSERT().
 842   If Address is not aligned on a 32-bit boundary, then ASSERT().
 843   If StartBit is greater than 31, then ASSERT().
 844   If EndBit is greater than 31, then ASSERT().
 845   If EndBit is less than StartBit, then ASSERT().
 846   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 847
 848   @param  Address   PCI configuration register to write.
 849   @param  StartBit  The ordinal of the least significant bit in the bit field.
 850                     Range 0..31.
 851   @param  EndBit    The ordinal of the most significant bit in the bit field.
 852                     Range 0..31.
 853   @param  Value     New value of the bit field.
 854
 855   @return The value written back to the PCI configuration register.
 856
 857 **/
 858 UINT32
 859 EFIAPI
 860 PciSegmentBitFieldWrite32 (
 861   IN UINT64                    Address,
 862   IN UINTN                     StartBit,
 863   IN UINTN                     EndBit,
 864   IN UINT32                    Value
 865   );
 866
 867 /**
 868   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 869   writes the result back to the bit field in the 32-bit port.
 870
 871   Reads the 32-bit PCI configuration register specified by Address, performs a
 872   bitwise OR between the read result and the value specified by
 873   OrData, and writes the result to the 32-bit PCI configuration register
 874   specified by Address. The value written to the PCI configuration register is
 875   returned. This function must guarantee that all PCI read and write operations
 876   are serialized. Extra left bits in OrData are stripped.
 877
 878   If any reserved bits in Address are set, then ASSERT().
 879   If StartBit is greater than 31, then ASSERT().
 880   If EndBit is greater than 31, then ASSERT().
 881   If EndBit is less than StartBit, then ASSERT().
 882   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 883
 884   @param  Address   PCI configuration register to write.
 885   @param  StartBit  The ordinal of the least significant bit in the bit field.
 886                     Range 0..31.
 887   @param  EndBit    The ordinal of the most significant bit in the bit field.
 888                     Range 0..31.
 889   @param  OrData    The value to OR with the PCI configuration register.
 890
 891   @return The value written back to the PCI configuration register.
 892
 893 **/
 894 UINT32
 895 EFIAPI
 896 PciSegmentBitFieldOr32 (
 897   IN UINT64                    Address,
 898   IN UINTN                     StartBit,
 899   IN UINTN                     EndBit,
 900   IN UINT32                    OrData
 901   );
 902
 903 /**
 904   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 905   AND, and writes the result back to the bit field in the 32-bit register.
 906
 907
 908   Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
 909   AND between the read result and the value specified by AndData, and writes the result
 910   to the 32-bit PCI configuration register specified by Address. The value written to
 911   the PCI configuration register is returned.  This function must guarantee that all PCI
 912   read and write operations are serialized.  Extra left bits in AndData are stripped.
 913   If any reserved bits in Address are set, then ASSERT().
 914   If Address is not aligned on a 32-bit boundary, then ASSERT().
 915   If StartBit is greater than 31, then ASSERT().
 916   If EndBit is greater than 31, then ASSERT().
 917   If EndBit is less than StartBit, then ASSERT().
 918   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 919
 920   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 921   @param  StartBit  The ordinal of the least significant bit in the bit field.
 922                     Range 0..31.
 923   @param  EndBit    The ordinal of the most significant bit in the bit field.
 924                     Range 0..31.
 925   @param  AndData   The value to AND with the PCI configuration register.
 926
 927   @return The value written back to the PCI configuration register.
 928
 929 **/
 930 UINT32
 931 EFIAPI
 932 PciSegmentBitFieldAnd32 (
 933   IN UINT64                    Address,
 934   IN UINTN                     StartBit,
 935   IN UINTN                     EndBit,
 936   IN UINT32                    AndData
 937   );
 938
 939 /**
 940   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 941   bitwise OR, and writes the result back to the bit field in the
 942   32-bit port.
 943
 944   Reads the 32-bit PCI configuration register specified by Address, performs a
 945   bitwise AND followed by a bitwise OR between the read result and
 946   the value specified by AndData, and writes the result to the 32-bit PCI
 947   configuration register specified by Address. The value written to the PCI
 948   configuration register is returned. This function must guarantee that all PCI
 949   read and write operations are serialized. Extra left bits in both AndData and
 950   OrData are stripped.
 951
 952   If any reserved bits in Address are set, then ASSERT().
 953   If StartBit is greater than 31, then ASSERT().
 954   If EndBit is greater than 31, then ASSERT().
 955   If EndBit is less than StartBit, then ASSERT().
 956   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 957   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 958
 959   @param  Address   PCI configuration register to write.
 960   @param  StartBit  The ordinal of the least significant bit in the bit field.
 961                     Range 0..31.
 962   @param  EndBit    The ordinal of the most significant bit in the bit field.
 963                     Range 0..31.
 964   @param  AndData   The value to AND with the PCI configuration register.
 965   @param  OrData    The value to OR with the result of the AND operation.
 966
 967   @return The value written back to the PCI configuration register.
 968
 969 **/
 970 UINT32
 971 EFIAPI
 972 PciSegmentBitFieldAndThenOr32 (
 973   IN UINT64                    Address,
 974   IN UINTN                     StartBit,
 975   IN UINTN                     EndBit,
 976   IN UINT32                    AndData,
 977   IN UINT32                    OrData
 978   );
 979
 980 /**
 981   Reads a range of PCI configuration registers into a caller supplied buffer.
 982
 983   Reads the range of PCI configuration registers specified by StartAddress and
 984   Size into the buffer specified by Buffer. This function only allows the PCI
 985   configuration registers from a single PCI function to be read. Size is
 986   returned. When possible 32-bit PCI configuration read cycles are used to read
 987   from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
 988   and 16-bit PCI configuration read cycles may be used at the beginning and the
 989   end of the range.
 990
 991   If any reserved bits in StartAddress are set, then ASSERT().
 992   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 993   If Size > 0 and Buffer is NULL, then ASSERT().
 994
 995   @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,
 996                         Function and Register.
 997   @param  Size          Size in bytes of the transfer.
 998   @param  Buffer        Pointer to a buffer receiving the data read.
 999
1000   @return Size
1001
1002 **/
1003 UINTN
1004 EFIAPI
1005 PciSegmentReadBuffer (
1006   IN  UINT64                   StartAddress,
1007   IN  UINTN                    Size,
1008   OUT VOID                     *Buffer
1009   );
1010
1011 /**
1012   Copies the data in a caller supplied buffer to a specified range of PCI
1013   configuration space.
1014
1015   Writes the range of PCI configuration registers specified by StartAddress and
1016   Size from the buffer specified by Buffer. This function only allows the PCI
1017   configuration registers from a single PCI function to be written. Size is
1018   returned. When possible 32-bit PCI configuration write cycles are used to
1019   write from StartAddress to StartAddress + Size. Due to alignment restrictions,
1020   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1021   and the end of the range.
1022
1023   If any reserved bits in StartAddress are set, then ASSERT().
1024   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1025   If Size > 0 and Buffer is NULL, then ASSERT().
1026
1027   @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,
1028                         Function and Register.
1029   @param  Size          Size in bytes of the transfer.
1030   @param  Buffer        Pointer to a buffer containing the data to write.
1031
1032   @return The parameter of Size.
1033
1034 **/
1035 UINTN
1036 EFIAPI
1037 PciSegmentWriteBuffer (
1038   IN UINT64                    StartAddress,
1039   IN UINTN                     Size,
1040   IN VOID                      *Buffer
1041   );
1042
1043 #endif