MdePkg/Include/Library/PciSegmentLib.h

   1 /** @file
   2   Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
   3
   4   The PCI Segment Library function provide services to read, write, and modify the PCI configuration
   5   registers on PCI root bridges on any supported PCI segment.  These library services take a single
   6   address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.
   7   The layout of this address parameter is as follows:
   8
   9             PCI Register:       Bits 0..11
  10             PCI Function        Bits 12..14
  11             PCI Device  Bits 15..19
  12             PCI Bus     Bits 20..27
  13             Reserved    Bits 28..31.  Must be 0.
  14             PCI Segment Bits 32..47
  15             Reserved    Bits 48..63.  Must be 0.
  16
  17   | Reserved (MBZ) | Segment | Reserved (MBZ) |     Bus     | Device | Function | Register |
  18   63             48  47    32  31           28 27         20 19    15 14      12 11         0
  19
  20   These functions perform PCI configuration cycles using the default PCI configuration access
  21   method.  This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
  22   may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate
  23   access method.  Modules will typically use the PCI Segment Library for its PCI configuration
  24   accesses when PCI Segments other than Segment #0 must be accessed.
  25
  26 Copyright (c) 2006 - 2008, Intel Corporation
  27 All rights reserved. This program and the accompanying materials
  28 are licensed and made available under the terms and conditions of the BSD License
  29 which accompanies this distribution.  The full text of the license may be found at
  30 http://opensource.org/licenses/bsd-license.php
  31
  32 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  33 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  34
  35 **/
  36
  37 #ifndef __PCI_SEGMENT_LIB__
  38 #define __PCI_SEGMENT_LIB__
  39
  40
  41 /**
  42   Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
  43   and PCI Register to an address that can be passed to the PCI Segment Library functions.
  44
  45   Computes an address that is compatible with the PCI Segment Library functions.
  46   The unused upper bits of Segment, Bus, Device, Function,
  47   and Register are stripped prior to the generation of the address.
  48
  49   @param  Segment   PCI Segment number.  Range 0..65535.
  50   @param  Bus       PCI Bus number.  Range 0..255.
  51   @param  Device    PCI Device number.  Range 0..31.
  52   @param  Function  PCI Function number.  Range 0..7.
  53   @param  Register  PCI Register number.  Range 0..255 for PCI.  Range 0..4095 for PCI Express.
  54
  55   @return The address that is compatible with the PCI Segment Library functions.
  56
  57 **/
  58 #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \
  59   ( ((Register) & 0xfff)              | \
  60     (((Function) & 0x07) << 12)       | \
  61     (((Device) & 0x1f) << 15)         | \
  62     (((Bus) & 0xff) << 20)            | \
  63     (LShiftU64((Segment) & 0xffff, 32)) \
  64   )
  65
  66 /**
  67   Reads an 8-bit PCI configuration register.
  68
  69   Reads and returns the 8-bit PCI configuration register specified by Address.
  70   This function must guarantee that all PCI read and write operations are serialized.
  71
  72   If any reserved bits in Address are set, then ASSERT().
  73
  74   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
  75
  76   @return The 8-bit PCI configuration register specified by Address.
  77
  78 **/
  79 UINT8
  80 EFIAPI
  81 PciSegmentRead8 (
  82   IN UINT64                    Address
  83   );
  84
  85 /**
  86   Writes an 8-bit PCI configuration register.
  87
  88   Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
  89   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
  90
  91   If Address > 0x0FFFFFFF, then ASSERT().
  92
  93   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
  94   @param  Value       The value to write.
  95
  96   @return The parameter of Value.
  97
  98 **/
  99 UINT8
 100 EFIAPI
 101 PciSegmentWrite8 (
 102   IN UINT64                    Address,
 103   IN UINT8                     Value
 104   );
 105
 106 /**
 107   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with an 8-bit value.
 108
 109   Reads the 8-bit PCI configuration register specified by Address,
 110   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 111   and writes the result to the 8-bit PCI configuration register specified by Address.
 112   The value written to the PCI configuration register is returned.
 113   This function must guarantee that all PCI read and write operations are serialized.
 114
 115   If any reserved bits in Address are set, then ASSERT().
 116
 117   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 118   @param  OrData    The value to OR with the PCI configuration register.
 119
 120   @return The value written to the PCI configuration register.
 121
 122 **/
 123 UINT8
 124 EFIAPI
 125 PciSegmentOr8 (
 126   IN UINT64                    Address,
 127   IN UINT8                     OrData
 128   );
 129
 130 /**
 131   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
 132
 133   Reads the 8-bit PCI configuration register specified by Address,
 134   performs a bitwise AND between the read result and the value specified by AndData,
 135   and writes the result to the 8-bit PCI configuration register specified by Address.
 136   The value written to the PCI configuration register is returned.
 137   This function must guarantee that all PCI read and write operations are serialized.
 138   If any reserved bits in Address are set, then ASSERT().
 139
 140   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 141   @param  AndData   The value to AND with the PCI configuration register.
 142
 143   @return The value written to the PCI configuration register.
 144
 145 **/
 146 UINT8
 147 EFIAPI
 148 PciSegmentAnd8 (
 149   IN UINT64                    Address,
 150   IN UINT8                     AndData
 151   );
 152
 153 /**
 154   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
 155   followed a  bitwise inclusive OR with another 8-bit value.
 156
 157   Reads the 8-bit PCI configuration register specified by Address,
 158   performs a bitwise AND between the read result and the value specified by AndData,
 159   performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,
 160   and writes the result to the 8-bit PCI configuration register specified by Address.
 161   The value written to the PCI configuration register is returned.
 162   This function must guarantee that all PCI read and write operations are serialized.
 163
 164   If any reserved bits in Address are set, then ASSERT().
 165
 166   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 167   @param  AndData    The value to AND with the PCI configuration register.
 168   @param  OrData    The value to OR with the PCI configuration register.
 169
 170   @return The value written to the PCI configuration register.
 171
 172 **/
 173 UINT8
 174 EFIAPI
 175 PciSegmentAndThenOr8 (
 176   IN UINT64                    Address,
 177   IN UINT8                     AndData,
 178   IN UINT8                     OrData
 179   );
 180
 181 /**
 182   Reads a bit field of a PCI configuration register.
 183
 184   Reads the bit field in an 8-bit PCI configuration register.
 185   The bit field is specified by the StartBit and the EndBit.
 186   The value of the bit field is returned.
 187
 188   If any reserved bits in Address are set, then ASSERT().
 189   If StartBit is greater than 7, then ASSERT().
 190   If EndBit is greater than 7, then ASSERT().
 191   If EndBit is less than StartBit, then ASSERT().
 192
 193   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 194   @param  StartBit  The ordinal of the least significant bit in the bit field.
 195                     The ordinal of the least significant bit in a byte is bit 0.
 196   @param  EndBit    The ordinal of the most significant bit in the bit field.
 197                     The ordinal of the most significant bit in a byte is bit 7.
 198
 199   @return The value of the bit field.
 200
 201 **/
 202 UINT8
 203 EFIAPI
 204 PciSegmentBitFieldRead8 (
 205   IN UINT64                    Address,
 206   IN UINTN                     StartBit,
 207   IN UINTN                     EndBit
 208   );
 209
 210 /**
 211   Writes a bit field to a PCI configuration register.
 212
 213   Writes Value to the bit field of the PCI configuration register.
 214   The bit field is specified by the StartBit and the EndBit.
 215   All other bits in the destination PCI configuration register are preserved.
 216   The new value of the 8-bit register is returned.
 217   If any reserved bits in Address are set, then ASSERT().
 218   If StartBit is greater than 7, then ASSERT().
 219   If EndBit is greater than 7, then ASSERT().
 220   If EndBit is less than StartBit, then ASSERT().
 221
 222   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 223   @param  StartBit  The ordinal of the least significant bit in the bit field.
 224                     The ordinal of the least significant bit in a byte is bit 0.
 225   @param  EndBit    The ordinal of the most significant bit in the bit field.
 226                     The ordinal of the most significant bit in a byte is bit 7.
 227   @param  Value     New value of the bit field.
 228
 229   @return The new value of the 8-bit register.
 230
 231 **/
 232 UINT8
 233 EFIAPI
 234 PciSegmentBitFieldWrite8 (
 235   IN UINT64                    Address,
 236   IN UINTN                     StartBit,
 237   IN UINTN                     EndBit,
 238   IN UINT8                     Value
 239   );
 240
 241 /**
 242   Reads the 8-bit PCI configuration register specified by Address,
 243   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 244   and writes the result to the 8-bit PCI configuration register specified by Address.
 245
 246   If any reserved bits in Address are set, then ASSERT().
 247   If StartBit is greater than 7, then ASSERT().
 248   If EndBit is greater than 7, then ASSERT().
 249   If EndBit is less than StartBit, then ASSERT().
 250
 251   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 252   @param  StartBit  The ordinal of the least significant bit in the bit field.
 253                     The ordinal of the least significant bit in a byte is bit 0.
 254   @param  EndBit    The ordinal of the most significant bit in the bit field.
 255                     The ordinal of the most significant bit in a byte is bit 7.
 256   @param  OrData    The value to OR with the read value from the PCI configuration register.
 257
 258   @return The value written to the PCI configuration register.
 259
 260 **/
 261 UINT8
 262 EFIAPI
 263 PciSegmentBitFieldOr8 (
 264   IN UINT64                    Address,
 265   IN UINTN                     StartBit,
 266   IN UINTN                     EndBit,
 267   IN UINT8                     OrData
 268   );
 269
 270 /**
 271   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR,
 272   and writes the result back to the bit field in the 8-bit port.
 273
 274   Reads the 8-bit PCI configuration register specified by Address,
 275   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 276   and writes the result to the 8-bit PCI configuration register specified by Address.
 277   The value written to the PCI configuration register is returned.
 278   This function must guarantee that all PCI read and write operations are serialized.
 279   Extra left bits in OrData are stripped.
 280
 281   If any reserved bits in Address are set, then ASSERT().
 282   If StartBit is greater than 7, then ASSERT().
 283   If EndBit is greater than 7, then ASSERT().
 284   If EndBit is less than StartBit, then ASSERT().
 285
 286   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 287   @param  StartBit  The ordinal of the least significant bit in the bit field.
 288                     The ordinal of the least significant bit in a byte is bit 0.
 289   @param  EndBit    The ordinal of the most significant bit in the bit field.
 290                     The ordinal of the most significant bit in a byte is bit 7.
 291   @param  AndData   The value to AND with the read value from the PCI configuration register.
 292
 293   @return The value written to the PCI configuration register.
 294
 295 **/
 296 UINT8
 297 EFIAPI
 298 PciSegmentBitFieldAnd8 (
 299   IN UINT64                    Address,
 300   IN UINTN                     StartBit,
 301   IN UINTN                     EndBit,
 302   IN UINT8                     AndData
 303   );
 304
 305 /**
 306   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND,
 307   and writes the result back to the bit field in the 8-bit register.
 308
 309   Reads the 8-bit PCI configuration register specified by Address,
 310   performs a bitwise AND between the read result and the value specified by AndData,
 311   and writes the result to the 8-bit PCI configuration register specified by Address.
 312   The value written to the PCI configuration register is returned.
 313   This function must guarantee that all PCI read and write operations are serialized.
 314   Extra left bits in AndData are stripped.
 315
 316   If any reserved bits in Address are set, then ASSERT().
 317   If StartBit is greater than 7, then ASSERT().
 318   If EndBit is greater than 7, then ASSERT().
 319   If EndBit is less than StartBit, then ASSERT().
 320
 321   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 322   @param  StartBit  The ordinal of the least significant bit in the bit field.
 323                     The ordinal of the least significant bit in a byte is bit 0.
 324   @param  EndBit    The ordinal of the most significant bit in the bit field.
 325                     The ordinal of the most significant bit in a byte is bit 7.
 326   @param  AndData   The value to AND with the read value from the PCI configuration register.
 327   @param  OrData    The value to OR with the read value from the PCI configuration register.
 328
 329   @return The value written to the PCI configuration register.
 330
 331 **/
 332 UINT8
 333 EFIAPI
 334 PciSegmentBitFieldAndThenOr8 (
 335   IN UINT64                    Address,
 336   IN UINTN                     StartBit,
 337   IN UINTN                     EndBit,
 338   IN UINT8                     AndData,
 339   IN UINT8                     OrData
 340   );
 341
 342 /**
 343   Reads a 16-bit PCI configuration register.
 344
 345   Reads and returns the 16-bit PCI configuration register specified by Address.
 346   This function must guarantee that all PCI read and write operations are serialized.
 347
 348   If any reserved bits in Address are set, then ASSERT().
 349   If Address is not aligned on a 16-bit boundary, then ASSERT().
 350
 351   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 352
 353   @return The 16-bit PCI configuration register specified by Address.
 354
 355 **/
 356 UINT16
 357 EFIAPI
 358 PciSegmentRead16 (
 359   IN UINT64                    Address
 360   );
 361
 362 /**
 363   Writes a 16-bit PCI configuration register.
 364
 365   Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
 366   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 367
 368   If any reserved bits in Address are set, then ASSERT().
 369   If Address is not aligned on a 16-bit boundary, then ASSERT().
 370
 371   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 372   @param  Value       The value to write.
 373
 374   @return The parameter of Value.
 375
 376 **/
 377 UINT16
 378 EFIAPI
 379 PciSegmentWrite16 (
 380   IN UINT64                    Address,
 381   IN UINT16                    Value
 382   );
 383
 384 /**
 385   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with a 16-bit value.
 386
 387   Reads the 16-bit PCI configuration register specified by Address,
 388   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 389   and writes the result to the 16-bit PCI configuration register specified by Address.
 390   The value written to the PCI configuration register is returned.
 391   This function must guarantee that all PCI read and write operations are serialized.
 392
 393   If any reserved bits in Address are set, then ASSERT().
 394   If Address is not aligned on a 16-bit boundary, then ASSERT().
 395
 396   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 397   @param  OrData    The value to OR with the PCI configuration register.
 398
 399   @return The value written to the PCI configuration register.
 400
 401 **/
 402 UINT16
 403 EFIAPI
 404 PciSegmentOr16 (
 405   IN UINT64                    Address,
 406   IN UINT16                    OrData
 407   );
 408
 409 /**
 410   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
 411
 412   Reads the 16-bit PCI configuration register specified by Address,
 413   performs a bitwise AND between the read result and the value specified by AndData,
 414   and writes the result to the 16-bit PCI configuration register specified by Address.
 415   The value written to the PCI configuration register is returned.
 416   This function must guarantee that all PCI read and write operations are serialized.
 417
 418   If any reserved bits in Address are set, then ASSERT().
 419   If Address is not aligned on a 16-bit boundary, then ASSERT().
 420
 421   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 422   @param  AndData   The value to AND with the PCI configuration register.
 423
 424   @return The value written to the PCI configuration register.
 425
 426 **/
 427 UINT16
 428 EFIAPI
 429 PciSegmentAnd16 (
 430   IN UINT64                    Address,
 431   IN UINT16                    AndData
 432   );
 433
 434 /**
 435   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
 436   followed a  bitwise inclusive OR with another 16-bit value.
 437
 438   Reads the 16-bit PCI configuration register specified by Address,
 439   performs a bitwise AND between the read result and the value specified by AndData,
 440   performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,
 441   and writes the result to the 16-bit PCI configuration register specified by Address.
 442   The value written to the PCI configuration register is returned.
 443   This function must guarantee that all PCI read and write operations are serialized.
 444
 445   If any reserved bits in Address are set, then ASSERT().
 446   If Address is not aligned on a 16-bit boundary, then ASSERT().
 447
 448   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 449   @param  AndData    The value to AND with the PCI configuration register.
 450   @param  OrData    The value to OR with the PCI configuration register.
 451
 452   @return The value written to the PCI configuration register.
 453
 454 **/
 455 UINT16
 456 EFIAPI
 457 PciSegmentAndThenOr16 (
 458   IN UINT64                    Address,
 459   IN UINT16                    AndData,
 460   IN UINT16                    OrData
 461   );
 462
 463 /**
 464   Reads a bit field of a PCI configuration register.
 465
 466   Reads the bit field in a 16-bit PCI configuration register.
 467   The bit field is specified by the StartBit and the EndBit.
 468   The value of the bit field is returned.
 469
 470   If any reserved bits in Address are set, then ASSERT().
 471   If Address is not aligned on a 16-bit boundary, then ASSERT().
 472   If StartBit is greater than 7, then ASSERT().
 473   If EndBit is greater than 7, then ASSERT().
 474   If EndBit is less than StartBit, then ASSERT().
 475
 476   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 477   @param  StartBit  The ordinal of the least significant bit in the bit field.
 478                     The ordinal of the least significant bit in a byte is bit 0.
 479   @param  EndBit    The ordinal of the most significant bit in the bit field.
 480                     The ordinal of the most significant bit in a byte is bit 7.
 481
 482   @return The value of the bit field.
 483
 484 **/
 485 UINT16
 486 EFIAPI
 487 PciSegmentBitFieldRead16 (
 488   IN UINT64                    Address,
 489   IN UINTN                     StartBit,
 490   IN UINTN                     EndBit
 491   );
 492
 493 /**
 494   Writes a bit field to a PCI configuration register.
 495
 496   Writes Value to the bit field of the PCI configuration register.
 497   The bit field is specified by the StartBit and the EndBit.
 498   All other bits in the destination PCI configuration register are preserved.
 499   The new value of the 16-bit register is returned.
 500
 501   If any reserved bits in Address are set, then ASSERT().
 502   If Address is not aligned on a 16-bit boundary, then ASSERT().
 503   If StartBit is greater than 7, then ASSERT().
 504   If EndBit is greater than 7, then ASSERT().
 505   If EndBit is less than StartBit, then ASSERT().
 506
 507   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 508   @param  StartBit  The ordinal of the least significant bit in the bit field.
 509                     The ordinal of the least significant bit in a byte is bit 0.
 510   @param  EndBit    The ordinal of the most significant bit in the bit field.
 511                     The ordinal of the most significant bit in a byte is bit 7.
 512   @param  Value     New value of the bit field.
 513
 514   @return The new value of the 16-bit register.
 515
 516 **/
 517 UINT16
 518 EFIAPI
 519 PciSegmentBitFieldWrite16 (
 520   IN UINT64                    Address,
 521   IN UINTN                     StartBit,
 522   IN UINTN                     EndBit,
 523   IN UINT16                    Value
 524   );
 525
 526 /**
 527   Reads the 16-bit PCI configuration register specified by Address,
 528   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 529   and writes the result to the 16-bit PCI configuration register specified by Address.
 530
 531   If any reserved bits in Address are set, then ASSERT().
 532   If Address is not aligned on a 16-bit boundary, then ASSERT().
 533   If StartBit is greater than 15, then ASSERT().
 534   If EndBit is greater than 15, then ASSERT().
 535   If EndBit is less than StartBit, then ASSERT().
 536
 537   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 538   @param  StartBit  The ordinal of the least significant bit in the bit field.
 539                     The ordinal of the least significant bit in a byte is bit 0.
 540   @param  EndBit    The ordinal of the most significant bit in the bit field.
 541                     The ordinal of the most significant bit in a byte is bit 7.
 542   @param  OrData    The value to OR with the read value from the PCI configuration register.
 543
 544   @return The value written to the PCI configuration register.
 545
 546 **/
 547 UINT16
 548 EFIAPI
 549 PciSegmentBitFieldOr16 (
 550   IN UINT64                    Address,
 551   IN UINTN                     StartBit,
 552   IN UINTN                     EndBit,
 553   IN UINT16                    OrData
 554   );
 555
 556 /**
 557   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
 558   and writes the result back to the bit field in the 16-bit port.
 559
 560   Reads the 16-bit PCI configuration register specified by Address,
 561   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 562   and writes the result to the 16-bit PCI configuration register specified by Address.
 563   The value written to the PCI configuration register is returned.
 564   This function must guarantee that all PCI read and write operations are serialized.
 565   Extra left bits in OrData are stripped.
 566
 567   If any reserved bits in Address are set, then ASSERT().
 568   If Address is not aligned on a 16-bit boundary, then ASSERT().
 569   If StartBit is greater than 7, then ASSERT().
 570   If EndBit is greater than 7, then ASSERT().
 571   If EndBit is less than StartBit, then ASSERT().
 572
 573   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 574   @param  StartBit  The ordinal of the least significant bit in the bit field.
 575                     The ordinal of the least significant bit in a byte is bit 0.
 576   @param  EndBit    The ordinal of the most significant bit in the bit field.
 577                     The ordinal of the most significant bit in a byte is bit 7.
 578   @param  AndData   The value to AND with the read value from the PCI configuration register.
 579
 580   @return The value written to the PCI configuration register.
 581
 582 **/
 583 UINT16
 584 EFIAPI
 585 PciSegmentBitFieldAnd16 (
 586   IN UINT64                    Address,
 587   IN UINTN                     StartBit,
 588   IN UINTN                     EndBit,
 589   IN UINT16                    AndData
 590   );
 591
 592 /**
 593   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND,
 594   and writes the result back to the bit field in the 16-bit register.
 595
 596   Reads the 16-bit PCI configuration register specified by Address,
 597   performs a bitwise AND between the read result and the value specified by AndData,
 598   and writes the result to the 16-bit PCI configuration register specified by Address.
 599   The value written to the PCI configuration register is returned.
 600   This function must guarantee that all PCI read and write operations are serialized.
 601   Extra left bits in AndData are stripped.
 602
 603   If any reserved bits in Address are set, then ASSERT().
 604   If Address is not aligned on a 16-bit boundary, then ASSERT()..
 605   If StartBit is greater than 7, then ASSERT().
 606   If EndBit is greater than 7, then ASSERT().
 607   If EndBit is less than StartBit, then ASSERT().
 608
 609   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 610   @param  StartBit  The ordinal of the least significant bit in the bit field.
 611                     The ordinal of the least significant bit in a byte is bit 0.
 612   @param  EndBit    The ordinal of the most significant bit in the bit field.
 613                     The ordinal of the most significant bit in a byte is bit 7.
 614   @param  AndData   The value to AND with the read value from the PCI configuration register.
 615   @param  OrData    The value to OR with the read value from the PCI configuration register.
 616
 617   @return The value written to the PCI configuration register.
 618
 619 **/
 620 UINT16
 621 EFIAPI
 622 PciSegmentBitFieldAndThenOr16 (
 623   IN UINT64                    Address,
 624   IN UINTN                     StartBit,
 625   IN UINTN                     EndBit,
 626   IN UINT16                    AndData,
 627   IN UINT16                    OrData
 628   );
 629
 630 /**
 631   Reads a 32-bit PCI configuration register.
 632
 633   Reads and returns the 32-bit PCI configuration register specified by Address.
 634   This function must guarantee that all PCI read and write operations are serialized.
 635
 636   If any reserved bits in Address are set, then ASSERT().
 637   If Address is not aligned on a 32-bit boundary, then ASSERT().
 638
 639   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 640
 641   @return The 32-bit PCI configuration register specified by Address.
 642
 643 **/
 644 UINT32
 645 EFIAPI
 646 PciSegmentRead32 (
 647   IN UINT64                    Address
 648   );
 649
 650 /**
 651   Writes a 32-bit PCI configuration register.
 652
 653   Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
 654   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 655
 656   If any reserved bits in Address are set, then ASSERT().
 657   If Address is not aligned on a 32-bit boundary, then ASSERT().
 658
 659   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 660   @param  Value       The value to write.
 661
 662   @return The parameter of Value.
 663
 664 **/
 665 UINT32
 666 EFIAPI
 667 PciSegmentWrite32 (
 668   IN UINT64                    Address,
 669   IN UINT32                    Value
 670   );
 671
 672 /**
 673   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with a 32-bit value.
 674
 675   Reads the 32-bit PCI configuration register specified by Address,
 676   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 677   and writes the result to the 32-bit PCI configuration register specified by Address.
 678   The value written to the PCI configuration register is returned.
 679   This function must guarantee that all PCI read and write operations are serialized.
 680
 681   If any reserved bits in Address are set, then ASSERT().
 682   If Address is not aligned on a 32-bit boundary, then ASSERT().
 683
 684   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 685   @param  OrData    The value to OR with the PCI configuration register.
 686
 687   @return The value written to the PCI configuration register.
 688
 689 **/
 690 UINT32
 691 EFIAPI
 692 PciSegmentOr32 (
 693   IN UINT64                    Address,
 694   IN UINT32                    OrData
 695   );
 696
 697 /**
 698   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
 699
 700   Reads the 32-bit PCI configuration register specified by Address,
 701   performs a bitwise AND between the read result and the value specified by AndData,
 702   and writes the result to the 32-bit PCI configuration register specified by Address.
 703   The value written to the PCI configuration register is returned.
 704   This function must guarantee that all PCI read and write operations are serialized.
 705
 706   If any reserved bits in Address are set, then ASSERT().
 707   If Address is not aligned on a 32-bit boundary, then ASSERT().
 708
 709   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 710   @param  AndData   The value to AND with the PCI configuration register.
 711
 712   @return The value written to the PCI configuration register.
 713
 714 **/
 715 UINT32
 716 EFIAPI
 717 PciSegmentAnd32 (
 718   IN UINT64                    Address,
 719   IN UINT32                    AndData
 720   );
 721
 722 /**
 723   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
 724   followed a  bitwise inclusive OR with another 32-bit value.
 725
 726   Reads the 32-bit PCI configuration register specified by Address,
 727   performs a bitwise AND between the read result and the value specified by AndData,
 728   performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,
 729   and writes the result to the 32-bit PCI configuration register specified by Address.
 730   The value written to the PCI configuration register is returned.
 731   This function must guarantee that all PCI read and write operations are serialized.
 732
 733   If any reserved bits in Address are set, then ASSERT().
 734   If Address is not aligned on a 32-bit boundary, then ASSERT().
 735
 736   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 737   @param  AndData   The value to AND with the PCI configuration register.
 738   @param  OrData    The value to OR with the PCI configuration register.
 739
 740   @return The value written to the PCI configuration register.
 741
 742 **/
 743 UINT32
 744 EFIAPI
 745 PciSegmentAndThenOr32 (
 746   IN UINT64                    Address,
 747   IN UINT32                    AndData,
 748   IN UINT32                    OrData
 749   );
 750
 751 /**
 752   Reads a bit field of a PCI configuration register.
 753
 754   Reads the bit field in a 32-bit PCI configuration register.
 755   The bit field is specified by the StartBit and the EndBit.
 756   The value of the bit field is returned.
 757
 758   If any reserved bits in Address are set, then ASSERT().
 759   If Address is not aligned on a 32-bit boundary, then ASSERT().
 760   If StartBit is greater than 7, then ASSERT().
 761   If EndBit is greater than 7, then ASSERT().
 762   If EndBit is less than StartBit, then ASSERT().
 763
 764   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 765   @param  StartBit  The ordinal of the least significant bit in the bit field.
 766                     The ordinal of the least significant bit in a byte is bit 0.
 767   @param  EndBit    The ordinal of the most significant bit in the bit field.
 768                     The ordinal of the most significant bit in a byte is bit 7.
 769
 770   @return The value of the bit field.
 771
 772 **/
 773 UINT32
 774 EFIAPI
 775 PciSegmentBitFieldRead32 (
 776   IN UINT64                    Address,
 777   IN UINTN                     StartBit,
 778   IN UINTN                     EndBit
 779   );
 780
 781 /**
 782   Writes a bit field to a PCI configuration register.
 783
 784   Writes Value to the bit field of the PCI configuration register.
 785   The bit field is specified by the StartBit and the EndBit.
 786   All other bits in the destination PCI configuration register are preserved.
 787   The new value of the 32-bit register is returned.
 788
 789   If any reserved bits in Address are set, then ASSERT().
 790   If Address is not aligned on a 32-bit boundary, then ASSERT().
 791   If StartBit is greater than 7, then ASSERT().
 792   If EndBit is greater than 7, then ASSERT().
 793   If EndBit is less than StartBit, then ASSERT().
 794
 795   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 796   @param  StartBit  The ordinal of the least significant bit in the bit field.
 797                     The ordinal of the least significant bit in a byte is bit 0.
 798   @param  EndBit    The ordinal of the most significant bit in the bit field.
 799                     The ordinal of the most significant bit in a byte is bit 7.
 800   @param  Value     New value of the bit field.
 801
 802   @return The new value of the 32-bit register.
 803
 804 **/
 805 UINT32
 806 EFIAPI
 807 PciSegmentBitFieldWrite32 (
 808   IN UINT64                    Address,
 809   IN UINTN                     StartBit,
 810   IN UINTN                     EndBit,
 811   IN UINT32                    Value
 812   );
 813
 814 /**
 815   Reads the 32-bit PCI configuration register specified by Address,
 816   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 817   and writes the result to the 32-bit PCI configuration register specified by Address.
 818
 819   If any reserved bits in Address are set, then ASSERT().
 820   If Address is not aligned on a 32-bit boundary, then ASSERT().
 821   If StartBit is greater than 7, then ASSERT().
 822   If EndBit is greater than 7, then ASSERT().
 823   If EndBit is less than StartBit, then ASSERT().
 824
 825   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 826   @param  StartBit  The ordinal of the least significant bit in the bit field.
 827                     The ordinal of the least significant bit in a byte is bit 0.
 828   @param  EndBit    The ordinal of the most significant bit in the bit field.
 829                     The ordinal of the most significant bit in a byte is bit 7.
 830   @param  OrData    The value to OR with the read value from the PCI configuration register.
 831
 832   @return The value written to the PCI configuration register.
 833
 834 **/
 835 UINT32
 836 EFIAPI
 837 PciSegmentBitFieldOr32 (
 838   IN UINT64                    Address,
 839   IN UINTN                     StartBit,
 840   IN UINTN                     EndBit,
 841   IN UINT32                    OrData
 842   );
 843
 844 /**
 845   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR,
 846   and writes the result back to the bit field in the 32-bit port.
 847
 848   Reads the 32-bit PCI configuration register specified by Address,
 849   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 850   and writes the result to the 32-bit PCI configuration register specified by Address.
 851   The value written to the PCI configuration register is returned.
 852   This function must guarantee that all PCI read and write operations are serialized.
 853   Extra left bits in OrData are stripped.
 854
 855   If any reserved bits in Address are set, then ASSERT().
 856   If Address is not aligned on a 32-bit boundary, then ASSERT().
 857   If StartBit is greater than 7, then ASSERT().
 858   If EndBit is greater than 7, then ASSERT().
 859   If EndBit is less than StartBit, then ASSERT().
 860
 861   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 862   @param  StartBit  The ordinal of the least significant bit in the bit field.
 863                     The ordinal of the least significant bit in a byte is bit 0.
 864   @param  EndBit    The ordinal of the most significant bit in the bit field.
 865                     The ordinal of the most significant bit in a byte is bit 7.
 866   @param  AndData   The value to AND with the read value from the PCI configuration register.
 867
 868   @return The value written to the PCI configuration register.
 869
 870 **/
 871 UINT32
 872 EFIAPI
 873 PciSegmentBitFieldAnd32 (
 874   IN UINT64                    Address,
 875   IN UINTN                     StartBit,
 876   IN UINTN                     EndBit,
 877   IN UINT32                    AndData
 878   );
 879
 880 /**
 881   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND,
 882   and writes the result back to the bit field in the 32-bit register.
 883
 884   Reads the 32-bit PCI configuration register specified by Address,
 885   performs a bitwise AND between the read result and the value specified by AndData,
 886   and writes the result to the 32-bit PCI configuration register specified by Address.
 887   The value written to the PCI configuration register is returned.
 888   This function must guarantee that all PCI read and write operations are serialized.
 889   Extra left bits in AndData are stripped.
 890
 891   If any reserved bits in Address are set, then ASSERT().
 892   If Address is not aligned on a 32-bit boundary, then ASSERT().
 893   If StartBit is greater than 7, then ASSERT().
 894   If EndBit is greater than 7, then ASSERT().
 895   If EndBit is less than StartBit, then ASSERT().
 896
 897   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 898   @param  StartBit  The ordinal of the least significant bit in the bit field.
 899                     The ordinal of the least significant bit in a byte is bit 0.
 900   @param  EndBit    The ordinal of the most significant bit in the bit field.
 901                     The ordinal of the most significant bit in a byte is bit 7.
 902   @param  AndData   The value to AND with the read value from the PCI configuration register.
 903   @param  OrData    The value to OR with the read value from the PCI configuration register.
 904
 905   @return The value written to the PCI configuration register.
 906
 907 **/
 908 UINT32
 909 EFIAPI
 910 PciSegmentBitFieldAndThenOr32 (
 911   IN UINT64                    Address,
 912   IN UINTN                     StartBit,
 913   IN UINTN                     EndBit,
 914   IN UINT32                    AndData,
 915   IN UINT32                    OrData
 916   );
 917
 918 /**
 919   Reads a range of PCI configuration registers into a caller supplied buffer.
 920
 921   Reads the range of PCI configuration registers specified by StartAddress
 922   and Size into the buffer specified by Buffer.
 923   This function only allows the PCI configuration registers from a single PCI function to be read.
 924   Size is returned.
 925
 926   If any reserved bits in StartAddress are set, then ASSERT().
 927   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 928   If (StartAddress + Size - 1)  > 0x0FFFFFFF, then ASSERT().
 929   If Size > 0 and Buffer is NULL, then ASSERT().
 930
 931   @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.
 932   @param  Size          Size in bytes of the transfer.
 933   @param  Buffer        Pointer to a buffer receiving the data read.
 934
 935   @return The parameter of Size.
 936
 937 **/
 938 UINTN
 939 EFIAPI
 940 PciSegmentReadBuffer (
 941   IN  UINT64                   StartAddress,
 942   IN  UINTN                    Size,
 943   OUT VOID                     *Buffer
 944   );
 945
 946 /**
 947   Copies the data in a caller supplied buffer to a specified range of PCI configuration space.
 948
 949   Writes the range of PCI configuration registers specified by StartAddress
 950   and Size from the buffer specified by Buffer.
 951   This function only allows the PCI configuration registers from a single PCI function to be written.
 952   Size is returned.
 953
 954   If any reserved bits in StartAddress are set, then ASSERT().
 955   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 956   If (StartAddress + Size - 1)  > 0x0FFFFFFF, then ASSERT().
 957   If Buffer is NULL, then ASSERT().
 958
 959   @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.
 960   @param  Size          Size in bytes of the transfer.
 961   @param  Buffer        Pointer to a buffer containing the data to write.
 962
 963   @return The parameter of Size.
 964
 965 **/
 966 UINTN
 967 EFIAPI
 968 PciSegmentWriteBuffer (
 969   IN UINT64                    StartAddress,
 970   IN UINTN                     Size,
 971   IN VOID                      *Buffer
 972   );
 973
 974 #endif