MdePkg/Include/Ppi/PciCfg2.h

   1 /** @file
   2   This file declares PciCfg2 PPI.
   3
   4   This ppi Provides platform or chipset-specific access to
   5   the PCI configuration space for a specific PCI segment.
   6
   7   Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   8   SPDX-License-Identifier: BSD-2-Clause-Patent
   9
  10   @par Revision Reference:
  11   This PPI is introduced in PI Version 1.0.
  12
  13 **/
  14
  15 #ifndef __PEI_PCI_CFG2_H__
  16 #define __PEI_PCI_CFG2_H__
  17
  18 #include <Library/BaseLib.h>
  19
  20 #define EFI_PEI_PCI_CFG2_PPI_GUID \
  21   { 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }
  22
  23 typedef struct _EFI_PEI_PCI_CFG2_PPI   EFI_PEI_PCI_CFG2_PPI;
  24
  25 #define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \
  26   (UINT64) ( \
  27   (((UINTN) bus) << 24) | \
  28   (((UINTN) dev) << 16) | \
  29   (((UINTN) func) << 8) | \
  30   (((UINTN) (reg)) < 256 ? ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))))
  31
  32 ///
  33 /// EFI_PEI_PCI_CFG_PPI_WIDTH
  34 ///
  35 typedef enum {
  36   ///
  37   ///  8-bit access
  38   ///
  39   EfiPeiPciCfgWidthUint8  = 0,
  40   ///
  41   /// 16-bit access
  42   ///
  43   EfiPeiPciCfgWidthUint16 = 1,
  44   ///
  45   /// 32-bit access
  46   ///
  47   EfiPeiPciCfgWidthUint32 = 2,
  48   ///
  49   /// 64-bit access
  50   ///
  51   EfiPeiPciCfgWidthUint64 = 3,
  52   EfiPeiPciCfgWidthMaximum
  53 } EFI_PEI_PCI_CFG_PPI_WIDTH;
  54
  55 ///
  56 /// EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS
  57 ///
  58 typedef struct {
  59   ///
  60   /// 8-bit register offset within the PCI configuration space for a given device's function
  61   /// space.
  62   ///
  63   UINT8   Register;
  64   ///
  65   /// Only the 3 least-significant bits are used to encode one of 8 possible functions within a
  66   /// given device.
  67   ///
  68   UINT8   Function;
  69   ///
  70   /// Only the 5 least-significant bits are used to encode one of 32 possible devices.
  71   ///
  72   UINT8   Device;
  73   ///
  74   /// 8-bit value to encode between 0 and 255 buses.
  75   ///
  76   UINT8   Bus;
  77   ///
  78   /// Register number in PCI configuration space. If this field is zero, then Register is used
  79   /// for the register number. If this field is non-zero, then Register is ignored and this field
  80   /// is used for the register number.
  81   ///
  82   UINT32  ExtendedRegister;
  83 } EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;
  84
  85 /**
  86   Reads from or write to a given location in the PCI configuration space.
  87
  88   @param  PeiServices     An indirect pointer to the PEI Services Table published by the PEI Foundation.
  89
  90   @param  This            Pointer to local data for the interface.
  91
  92   @param  Width           The width of the access. Enumerated in bytes.
  93                           See EFI_PEI_PCI_CFG_PPI_WIDTH above.
  94
  95   @param  Address         The physical address of the access. The format of
  96                           the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.
  97
  98   @param  Buffer          A pointer to the buffer of data..
  99
 100
 101   @retval EFI_SUCCESS           The function completed successfully.
 102
 103   @retval EFI_DEVICE_ERROR      There was a problem with the transaction.
 104
 105   @retval EFI_DEVICE_NOT_READY  The device is not capable of supporting the operation at this
 106                                 time.
 107
 108 **/
 109 typedef
 110 EFI_STATUS
 111 (EFIAPI *EFI_PEI_PCI_CFG2_PPI_IO)(
 112   IN CONST  EFI_PEI_SERVICES          **PeiServices,
 113   IN CONST  EFI_PEI_PCI_CFG2_PPI      *This,
 114   IN        EFI_PEI_PCI_CFG_PPI_WIDTH Width,
 115   IN        UINT64                    Address,
 116   IN OUT    VOID                      *Buffer
 117 );
 118
 119
 120 /**
 121   Performs a read-modify-write operation on the contents
 122   from a given location in the PCI configuration space.
 123
 124   @param  PeiServices     An indirect pointer to the PEI Services Table
 125                           published by the PEI Foundation.
 126
 127   @param  This            Pointer to local data for the interface.
 128
 129   @param  Width           The width of the access. Enumerated in bytes. Type
 130                           EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().
 131
 132   @param  Address         The physical address of the access.
 133
 134   @param  SetBits         Points to value to bitwise-OR with the read configuration value.
 135
 136                           The size of the value is determined by Width.
 137
 138   @param  ClearBits       Points to the value to negate and bitwise-AND with the read configuration value.
 139                           The size of the value is determined by Width.
 140
 141
 142   @retval EFI_SUCCESS           The function completed successfully.
 143
 144   @retval EFI_DEVICE_ERROR      There was a problem with the transaction.
 145
 146   @retval EFI_DEVICE_NOT_READY  The device is not capable of supporting
 147                                 the operation at this time.
 148
 149 **/
 150 typedef
 151 EFI_STATUS
 152 (EFIAPI *EFI_PEI_PCI_CFG2_PPI_RW)(
 153   IN CONST  EFI_PEI_SERVICES          **PeiServices,
 154   IN CONST  EFI_PEI_PCI_CFG2_PPI      *This,
 155   IN        EFI_PEI_PCI_CFG_PPI_WIDTH Width,
 156   IN        UINT64                    Address,
 157   IN        VOID                      *SetBits,
 158   IN        VOID                      *ClearBits
 159 );
 160
 161 ///
 162 /// The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI
 163 /// controllers behind a PCI root bridge controller.
 164 ///
 165 struct _EFI_PEI_PCI_CFG2_PPI {
 166   EFI_PEI_PCI_CFG2_PPI_IO  Read;
 167   EFI_PEI_PCI_CFG2_PPI_IO  Write;
 168   EFI_PEI_PCI_CFG2_PPI_RW  Modify;
 169   ///
 170   /// The PCI bus segment which the specified functions will access.
 171   ///
 172   UINT16                  Segment;
 173 };
 174
 175
 176 extern EFI_GUID gEfiPciCfg2PpiGuid;
 177
 178 #endif