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1 /** @file
2 This file declares Sec Platform Information PPI.
3
4 This service is the primary handoff state into the PEI Foundation.
5 The Security (SEC) component creates the early, transitory memory
6 environment and also encapsulates knowledge of at least the
7 location of the Boot Firmware Volume (BFV).
8
9 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
11
12 @par Revision Reference:
13 This PPI is introduced in PI Version 1.0.
14
15 **/
16
17 #ifndef __SEC_PLATFORM_INFORMATION_PPI_H__
18 #define __SEC_PLATFORM_INFORMATION_PPI_H__
19
20 #include <Pi/PiPeiCis.h>
21
22 #define EFI_SEC_PLATFORM_INFORMATION_GUID \
23 { \
24 0x6f8c2b35, 0xfef4, 0x448d, {0x82, 0x56, 0xe1, 0x1b, 0x19, 0xd6, 0x10, 0x77 } \
25 }
26
27 typedef struct _EFI_SEC_PLATFORM_INFORMATION_PPI EFI_SEC_PLATFORM_INFORMATION_PPI;
28
29 ///
30 /// EFI_HEALTH_FLAGS
31 /// Contains information generated by microcode, hardware, and/or the Itanium
32 /// processor PAL code about the state of the processor upon reset.
33 ///
34 typedef union {
35 struct {
36 ///
37 /// A 2-bit field indicating self-test state after reset.
38 ///
39 UINT32 Status : 2;
40 ///
41 /// A 1-bit field indicating whether testing has occurred.
42 /// If this field is zero, the processor has not been tested,
43 /// and no further fields in the self-test State parameter are valid.
44 ///
45 UINT32 Tested : 1;
46 ///
47 /// Reserved 13 bits.
48 ///
49 UINT32 Reserved1 : 13;
50 ///
51 /// A 1-bit field. If set to 1, this indicates that virtual
52 /// memory features are not available.
53 ///
54 UINT32 VirtualMemoryUnavailable : 1;
55 ///
56 /// A 1-bit field. If set to 1, this indicates that IA-32 execution
57 /// is not available.
58 ///
59 UINT32 Ia32ExecutionUnavailable : 1;
60 ///
61 /// A 1-bit field. If set to 1, this indicates that the floating
62 /// point unit is not available.
63 ///
64 UINT32 FloatingPointUnavailable : 1;
65 ///
66 /// A 1-bit field. If set to 1, this indicates miscellaneous
67 /// functional failure other than vm, ia, or fp.
68 /// The test status field provides additional information on
69 /// test failures when the State field returns a value of
70 /// performance restricted or functionally restricted.
71 /// The value returned is implementation dependent.
72 ///
73 UINT32 MiscFeaturesUnavailable : 1;
74 ///
75 /// Reserved 12 bits.
76 ///
77 UINT32 Reserved2 : 12;
78 } Bits;
79 UINT32 Uint32;
80 } EFI_HEALTH_FLAGS;
81
82 #define NORMAL_BOOT_CALL 0x0
83 #define RECOVERY_CHECK_CALL 0x3
84
85 typedef EFI_HEALTH_FLAGS X64_HANDOFF_STATUS;
86 typedef EFI_HEALTH_FLAGS IA32_HANDOFF_STATUS;
87 ///
88 /// The hand-off status structure for Itanium architecture.
89 ///
90 typedef struct {
91 ///
92 /// SALE_ENTRY state : 3 = Recovery_Check
93 /// and 0 = RESET or Normal_Boot phase.
94 ///
95 UINT8 BootPhase;
96 ///
97 /// Firmware status on entry to SALE.
98 ///
99 UINT8 FWStatus;
100 UINT16 Reserved1;
101 UINT32 Reserved2;
102 ///
103 /// Geographically significant unique processor ID assigned by PAL.
104 ///
105 UINT16 ProcId;
106 UINT16 Reserved3;
107 UINT8 IdMask;
108 UINT8 EidMask;
109 UINT16 Reserved4;
110 ///
111 /// Address to make PAL calls.
112 ///
113 UINT64 PalCallAddress;
114 ///
115 /// If the entry state is RECOVERY_CHECK, this contains the PAL_RESET
116 /// return address, and if entry state is RESET, this contains
117 /// address for PAL_authentication call.
118 ///
119 UINT64 PalSpecialAddress;
120 ///
121 /// GR35 from PALE_EXIT state.
122 ///
123 UINT64 SelfTestStatus;
124 ///
125 /// GR37 from PALE_EXIT state.
126 ///
127 UINT64 SelfTestControl;
128 UINT64 MemoryBufferRequired;
129 } ITANIUM_HANDOFF_STATUS;
130
131 ///
132 /// EFI_SEC_PLATFORM_INFORMATION_RECORD.
133 ///
134 typedef union {
135 IA32_HANDOFF_STATUS IA32HealthFlags;
136 X64_HANDOFF_STATUS x64HealthFlags;
137 ITANIUM_HANDOFF_STATUS ItaniumHealthFlags;
138 } EFI_SEC_PLATFORM_INFORMATION_RECORD;
139
140 /**
141 This interface conveys state information out of the Security (SEC) phase into PEI.
142
143 This service is published by the SEC phase. The SEC phase handoff has an optional
144 EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
145 PEI Foundation. As such, if the platform supports the built-in self test (BIST) on IA-32 Intel
146 architecture or the PAL-A handoff state for Itanium architecture, this information is encapsulated
147 into the data structure abstracted by this service. This information is collected for the boot-strap
148 processor (BSP) on IA-32. For Itanium architecture, it is available on all processors that execute
149 the PEI Foundation.
150
151 @param PeiServices The pointer to the PEI Services Table.
152 @param StructureSize The pointer to the variable describing size of the input buffer.
153 @param PlatformInformationRecord The pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
154
155 @retval EFI_SUCCESS The data was successfully returned.
156 @retval EFI_BUFFER_TOO_SMALL The buffer was too small. The current buffer size needed to
157 hold the record is returned in StructureSize.
158
159 **/
160 typedef
161 EFI_STATUS
162 (EFIAPI *EFI_SEC_PLATFORM_INFORMATION)(
163 IN CONST EFI_PEI_SERVICES **PeiServices,
164 IN OUT UINT64 *StructureSize,
165 OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
166 );
167
168 ///
169 /// This service abstracts platform-specific information. It is necessary
170 /// to convey this information to the PEI Foundation so that it can
171 /// discover where to begin dispatching PEIMs.
172 ///
173 struct _EFI_SEC_PLATFORM_INFORMATION_PPI {
174 EFI_SEC_PLATFORM_INFORMATION PlatformInformation;
175 };
176
177 extern EFI_GUID gEfiSecPlatformInformationPpiGuid;
178
179 #endif