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1 /** @file
2 This header file contains all of the PXE type definitions,
3 structure prototypes, global variables and constants that
4 are needed for porting PXE to EFI.
5
6 Copyright (c) 2006 - 2008, Intel Corporation
7 All rights reserved. This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 @par Revision Reference:
16 32/64-bit PXE specification:
17 alpha-4, 99-Dec-17
18
19 **/
20
21 #ifndef __EFI_PXE_H__
22 #define __EFI_PXE_H__
23
24 #pragma pack(1)
25
26 #define PXE_BUSTYPE(a, b, c, d) \
27 ( \
28 (((PXE_UINT32) (d) & 0xFF) << 24) | (((PXE_UINT32) (c) & 0xFF) << 16) | (((PXE_UINT32) (b) & 0xFF) << 8) | \
29 ((PXE_UINT32) (a) & 0xFF) \
30 )
31
32 ///
33 /// UNDI ROM ID and devive ID signature
34 ///
35 #define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E')
36
37 ///
38 /// BUS ROM ID signatures
39 ///
40 #define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R')
41 #define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R')
42 #define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R')
43 #define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4')
44
45 #define PXE_SWAP_UINT16(n) ((((PXE_UINT16) (n) & 0x00FF) << 8) | (((PXE_UINT16) (n) & 0xFF00) >> 8))
46
47 #define PXE_SWAP_UINT32(n) \
48 ((((PXE_UINT32)(n) & 0x000000FF) << 24) | \
49 (((PXE_UINT32)(n) & 0x0000FF00) << 8) | \
50 (((PXE_UINT32)(n) & 0x00FF0000) >> 8) | \
51 (((PXE_UINT32)(n) & 0xFF000000) >> 24))
52
53 #define PXE_SWAP_UINT64(n) \
54 ((((PXE_UINT64)(n) & 0x00000000000000FFULL) << 56) | \
55 (((PXE_UINT64)(n) & 0x000000000000FF00ULL) << 40) | \
56 (((PXE_UINT64)(n) & 0x0000000000FF0000ULL) << 24) | \
57 (((PXE_UINT64)(n) & 0x00000000FF000000ULL) << 8) | \
58 (((PXE_UINT64)(n) & 0x000000FF00000000ULL) >> 8) | \
59 (((PXE_UINT64)(n) & 0x0000FF0000000000ULL) >> 24) | \
60 (((PXE_UINT64)(n) & 0x00FF000000000000ULL) >> 40) | \
61 (((PXE_UINT64)(n) & 0xFF00000000000000ULL) >> 56))
62
63
64 #define PXE_CPBSIZE_NOT_USED 0 ///< zero
65 #define PXE_DBSIZE_NOT_USED 0 ///< zero
66 #define PXE_CPBADDR_NOT_USED (PXE_UINT64) 0 ///< zero
67 #define PXE_DBADDR_NOT_USED (PXE_UINT64) 0 ///< zero
68 #define PXE_CONST CONST
69
70 #define PXE_VOLATILE volatile
71
72 typedef VOID PXE_VOID;
73 typedef UINT8 PXE_UINT8;
74 typedef UINT16 PXE_UINT16;
75 typedef UINT32 PXE_UINT32;
76 typedef UINTN PXE_UINTN;
77
78 ///
79 /// typedef unsigned long PXE_UINT64;
80 ///
81 typedef UINT64 PXE_UINT64;
82
83 typedef PXE_UINT8 PXE_BOOL;
84 #define PXE_FALSE 0 ///< zero
85 #define PXE_TRUE (!PXE_FALSE)
86
87 typedef PXE_UINT16 PXE_OPCODE;
88
89 ///
90 /// Return UNDI operational state.
91 ///
92 #define PXE_OPCODE_GET_STATE 0x0000
93
94 ///
95 /// Change UNDI operational state from Stopped to Started.
96 ///
97 #define PXE_OPCODE_START 0x0001
98
99 ///
100 /// Change UNDI operational state from Started to Stopped.
101 ///
102 #define PXE_OPCODE_STOP 0x0002
103
104 ///
105 /// Get UNDI initialization information.
106 ///
107 #define PXE_OPCODE_GET_INIT_INFO 0x0003
108
109 ///
110 /// Get NIC configuration information.
111 ///
112 #define PXE_OPCODE_GET_CONFIG_INFO 0x0004
113
114 ///
115 /// Changed UNDI operational state from Started to Initialized.
116 ///
117 #define PXE_OPCODE_INITIALIZE 0x0005
118
119 ///
120 /// Re-initialize the NIC H/W.
121 ///
122 #define PXE_OPCODE_RESET 0x0006
123
124 ///
125 /// Change the UNDI operational state from Initialized to Started.
126 ///
127 #define PXE_OPCODE_SHUTDOWN 0x0007
128
129 ///
130 /// Read & change state of external interrupt enables.
131 ///
132 #define PXE_OPCODE_INTERRUPT_ENABLES 0x0008
133
134 ///
135 /// Read & change state of packet receive filters.
136 ///
137 #define PXE_OPCODE_RECEIVE_FILTERS 0x0009
138
139 ///
140 /// Read & change station MAC address.
141 ///
142 #define PXE_OPCODE_STATION_ADDRESS 0x000A
143
144 ///
145 /// Read traffic statistics.
146 ///
147 #define PXE_OPCODE_STATISTICS 0x000B
148
149 ///
150 /// Convert multicast IP address to multicast MAC address.
151 ///
152 #define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C
153
154 ///
155 /// Read or change non-volatile storage on the NIC.
156 ///
157 #define PXE_OPCODE_NVDATA 0x000D
158
159 ///
160 /// Get & clear interrupt status.
161 ///
162 #define PXE_OPCODE_GET_STATUS 0x000E
163
164 ///
165 /// Fill media header in packet for transmit.
166 ///
167 #define PXE_OPCODE_FILL_HEADER 0x000F
168
169 ///
170 /// Transmit packet(s).
171 ///
172 #define PXE_OPCODE_TRANSMIT 0x0010
173
174 ///
175 /// Receive packet.
176 ///
177 #define PXE_OPCODE_RECEIVE 0x0011
178
179 ///
180 /// Last valid PXE UNDI OpCode number.
181 ///
182 #define PXE_OPCODE_LAST_VALID 0x0011
183
184 typedef PXE_UINT16 PXE_OPFLAGS;
185
186 #define PXE_OPFLAGS_NOT_USED 0x0000
187
188 //
189 // //////////////////////////////////////
190 // UNDI Get State
191 //
192 // No OpFlags
193
194 ////////////////////////////////////////
195 // UNDI Start
196 //
197 // No OpFlags
198
199 ////////////////////////////////////////
200 // UNDI Stop
201 //
202 // No OpFlags
203
204 ////////////////////////////////////////
205 // UNDI Get Init Info
206 //
207 // No Opflags
208
209 ////////////////////////////////////////
210 // UNDI Get Config Info
211 //
212 // No Opflags
213
214 ///
215 /// UNDI Initialize
216 ///
217 #define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001
218 #define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000
219 #define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001
220
221 ///
222 ///
223 /// UNDI Reset
224 ///
225 #define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001
226 #define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002
227
228 ///
229 /// UNDI Shutdown
230 ///
231 /// No OpFlags
232
233 ///
234 /// UNDI Interrupt Enables
235 ///
236 ///
237 /// Select whether to enable or disable external interrupt signals.
238 /// Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS.
239 ///
240 #define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000
241 #define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000
242 #define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000
243 #define PXE_OPFLAGS_INTERRUPT_READ 0x0000
244
245 ///
246 /// Enable receive interrupts. An external interrupt will be generated
247 /// after a complete non-error packet has been received.
248 ///
249 #define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001
250
251 ///
252 /// Enable transmit interrupts. An external interrupt will be generated
253 /// after a complete non-error packet has been transmitted.
254 ///
255 #define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002
256
257 ///
258 /// Enable command interrupts. An external interrupt will be generated
259 /// when command execution stops.
260 ///
261 #define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004
262
263 ///
264 /// Generate software interrupt. Setting this bit generates an external
265 /// interrupt, if it is supported by the hardware.
266 ///
267 #define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008
268
269 ///
270 /// UNDI Receive Filters
271 ///
272 ///
273 /// Select whether to enable or disable receive filters.
274 /// Setting both enable and disable will return PXE_STATCODE_INVALID_OPCODE.
275 ///
276 #define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000
277 #define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000
278 #define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000
279 #define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000
280
281 ///
282 /// To reset the contents of the multicast MAC address filter list,
283 /// set this OpFlag:
284 ///
285 #define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000
286
287 ///
288 /// Enable unicast packet receiving. Packets sent to the current station
289 /// MAC address will be received.
290 ///
291 #define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001
292
293 ///
294 /// Enable broadcast packet receiving. Packets sent to the broadcast
295 /// MAC address will be received.
296 ///
297 #define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
298
299 ///
300 /// Enable filtered multicast packet receiving. Packets sent to any
301 /// of the multicast MAC addresses in the multicast MAC address filter
302 /// list will be received. If the filter list is empty, no multicast
303 ///
304 #define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
305
306 ///
307 /// Enable promiscuous packet receiving. All packets will be received.
308 ///
309 #define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
310
311 ///
312 /// Enable promiscuous multicast packet receiving. All multicast
313 /// packets will be received.
314 ///
315 #define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
316
317 ///
318 /// UNDI Station Address
319 ///
320 #define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000
321 #define PXE_OPFLAGS_STATION_ADDRESS_WRITE 0x0000
322 #define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001
323
324 ///
325 /// UNDI Statistics
326 ///
327 #define PXE_OPFLAGS_STATISTICS_READ 0x0000
328 #define PXE_OPFLAGS_STATISTICS_RESET 0x0001
329
330 ///
331 /// UNDI MCast IP to MAC
332 ///
333 ///
334 /// Identify the type of IP address in the CPB.
335 ///
336 #define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003
337 #define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000
338 #define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001
339
340 ///
341 /// UNDI NvData
342 ///
343 ///
344 /// Select the type of non-volatile data operation.
345 ///
346 #define PXE_OPFLAGS_NVDATA_OPMASK 0x0001
347 #define PXE_OPFLAGS_NVDATA_READ 0x0000
348 #define PXE_OPFLAGS_NVDATA_WRITE 0x0001
349
350 ///
351 /// UNDI Get Status
352 ///
353 ///
354 /// Return current interrupt status. This will also clear any interrupts
355 /// that are currently set. This can be used in a polling routine. The
356 /// interrupt flags are still set and cleared even when the interrupts
357 /// are disabled.
358 ///
359 #define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001
360
361 ///
362 /// Return list of transmitted buffers for recycling. Transmit buffers
363 /// must not be changed or unallocated until they have recycled. After
364 /// issuing a transmit command, wait for a transmit complete interrupt.
365 /// When a transmit complete interrupt is received, read the transmitted
366 /// buffers. Do not plan on getting one buffer per interrupt. Some
367 /// NICs and UNDIs may transmit multiple buffers per interrupt.
368 ///
369 #define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002
370
371 ///
372 /// UNDI Fill Header
373 ///
374 #define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001
375 #define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001
376 #define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000
377
378 ///
379 /// UNDI Transmit
380 ///
381 ///
382 /// S/W UNDI only. Return after the packet has been transmitted. A
383 /// transmit complete interrupt will still be generated and the transmit
384 /// buffer will have to be recycled.
385 ///
386 #define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001
387 #define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001
388 #define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000
389
390 #define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002
391 #define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002
392 #define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000
393
394 ///
395 /// UNDI Receive
396 ///
397 /// No OpFlags
398 ///
399
400 ///
401 /// PXE STATFLAGS
402 ///
403 typedef PXE_UINT16 PXE_STATFLAGS;
404
405 #define PXE_STATFLAGS_INITIALIZE 0x0000
406
407 ///
408 /// Common StatFlags that can be returned by all commands.
409 ///
410 ///
411 /// The COMMAND_COMPLETE and COMMAND_FAILED status flags must be
412 /// implemented by all UNDIs. COMMAND_QUEUED is only needed by UNDIs
413 /// that support command queuing.
414 ///
415 #define PXE_STATFLAGS_STATUS_MASK 0xC000
416 #define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000
417 #define PXE_STATFLAGS_COMMAND_FAILED 0x8000
418 #define PXE_STATFLAGS_COMMAND_QUEUED 0x4000
419
420 ///
421 /// UNDI Get State
422 ///
423 #define PXE_STATFLAGS_GET_STATE_MASK 0x0003
424 #define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002
425 #define PXE_STATFLAGS_GET_STATE_STARTED 0x0001
426 #define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000
427
428 ///
429 /// UNDI Start
430 ///
431 /// No additional StatFlags
432 ///
433
434 ///
435 /// UNDI Get Init Info
436 ///
437 #define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001
438 #define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000
439 #define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001
440
441 ///
442 /// UNDI Initialize
443 ///
444 #define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001
445
446 ///
447 /// UNDI Reset
448 ///
449 #define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001
450
451 ///
452 /// UNDI Shutdown
453 ///
454 /// No additional StatFlags
455
456 ///
457 /// UNDI Interrupt Enables
458 ///
459 ///
460 /// If set, receive interrupts are enabled.
461 ///
462 #define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001
463
464 ///
465 /// If set, transmit interrupts are enabled.
466 ///
467 #define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002
468
469 ///
470 /// If set, command interrupts are enabled.
471 ///
472 #define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004
473
474 ///
475 /// UNDI Receive Filters
476 ///
477
478 ///
479 /// If set, unicast packets will be received.
480 ///
481 #define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001
482
483 ///
484 /// If set, broadcast packets will be received.
485 ///
486 #define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
487
488 ///
489 /// If set, multicast packets that match up with the multicast address
490 /// filter list will be received.
491 ///
492 #define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
493
494 ///
495 /// If set, all packets will be received.
496 ///
497 #define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
498
499 ///
500 /// If set, all multicast packets will be received.
501 ///
502 #define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
503
504 ///
505 /// UNDI Station Address
506 ///
507 /// No additional StatFlags
508 ///
509
510 ///
511 /// UNDI Statistics
512 ///
513 /// No additional StatFlags
514 ///
515
516 ///
517 //// UNDI MCast IP to MAC
518 ////
519 //// No additional StatFlags
520
521 ///
522 /// UNDI NvData
523 ///
524 /// No additional StatFlags
525 ///
526
527 ///
528 /// UNDI Get Status
529 ///
530
531 ///
532 /// Use to determine if an interrupt has occurred.
533 ///
534 #define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F
535 #define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000
536
537 ///
538 /// If set, at least one receive interrupt occurred.
539 ///
540 #define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001
541
542 ///
543 /// If set, at least one transmit interrupt occurred.
544 ///
545 #define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002
546
547 ///
548 /// If set, at least one command interrupt occurred.
549 ///
550 #define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004
551
552 ///
553 /// If set, at least one software interrupt occurred.
554 ///
555 #define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008
556
557 ///
558 /// This flag is set if the transmitted buffer queue is empty. This flag
559 /// will be set if all transmitted buffer addresses get written into the DB.
560 ///
561 #define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010
562
563 ///
564 /// This flag is set if no transmitted buffer addresses were written
565 /// into the DB. (This could be because DBsize was too small.)
566 ///
567 #define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020
568
569 ///
570 /// UNDI Fill Header
571 ///
572 /// No additional StatFlags
573 ///
574
575 ///
576 /// UNDI Transmit
577 ///
578 /// No additional StatFlags.
579
580 ///
581 /// UNDI Receive
582 ///
583
584 ///
585 /// No additional StatFlags.
586 ///
587 typedef PXE_UINT16 PXE_STATCODE;
588
589 #define PXE_STATCODE_INITIALIZE 0x0000
590
591 ///
592 /// Common StatCodes returned by all UNDI commands, UNDI protocol functions
593 /// and BC protocol functions.
594 ///
595 #define PXE_STATCODE_SUCCESS 0x0000
596
597 #define PXE_STATCODE_INVALID_CDB 0x0001
598 #define PXE_STATCODE_INVALID_CPB 0x0002
599 #define PXE_STATCODE_BUSY 0x0003
600 #define PXE_STATCODE_QUEUE_FULL 0x0004
601 #define PXE_STATCODE_ALREADY_STARTED 0x0005
602 #define PXE_STATCODE_NOT_STARTED 0x0006
603 #define PXE_STATCODE_NOT_SHUTDOWN 0x0007
604 #define PXE_STATCODE_ALREADY_INITIALIZED 0x0008
605 #define PXE_STATCODE_NOT_INITIALIZED 0x0009
606 #define PXE_STATCODE_DEVICE_FAILURE 0x000A
607 #define PXE_STATCODE_NVDATA_FAILURE 0x000B
608 #define PXE_STATCODE_UNSUPPORTED 0x000C
609 #define PXE_STATCODE_BUFFER_FULL 0x000D
610 #define PXE_STATCODE_INVALID_PARAMETER 0x000E
611 #define PXE_STATCODE_INVALID_UNDI 0x000F
612 #define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010
613 #define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011
614 #define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012
615 #define PXE_STATCODE_NO_DATA 0x0013
616
617 typedef PXE_UINT16 PXE_IFNUM;
618
619 ///
620 /// This interface number must be passed to the S/W UNDI Start command.
621 ///
622 #define PXE_IFNUM_START 0x0000
623
624 ///
625 /// This interface number is returned by the S/W UNDI Get State and
626 /// Start commands if information in the CDB, CPB or DB is invalid.
627 ///
628 #define PXE_IFNUM_INVALID 0x0000
629
630 typedef PXE_UINT16 PXE_CONTROL;
631
632 ///
633 /// Setting this flag directs the UNDI to queue this command for later
634 /// execution if the UNDI is busy and it supports command queuing.
635 /// If queuing is not supported, a PXE_STATCODE_INVALID_CONTROL error
636 /// is returned. If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL
637 /// error is returned.
638 ///
639 #define PXE_CONTROL_QUEUE_IF_BUSY 0x0002
640
641 ///
642 /// These two bit values are used to determine if there are more UNDI
643 /// CDB structures following this one. If the link bit is set, there
644 /// must be a CDB structure following this one. Execution will start
645 /// on the next CDB structure as soon as this one completes successfully.
646 /// If an error is generated by this command, execution will stop.
647 ///
648 #define PXE_CONTROL_LINK 0x0001
649 #define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000
650
651 typedef PXE_UINT8 PXE_FRAME_TYPE;
652
653 #define PXE_FRAME_TYPE_NONE 0x00
654 #define PXE_FRAME_TYPE_UNICAST 0x01
655 #define PXE_FRAME_TYPE_BROADCAST 0x02
656 #define PXE_FRAME_TYPE_FILTERED_MULTICAST 0x03
657 #define PXE_FRAME_TYPE_PROMISCUOUS 0x04
658 #define PXE_FRAME_TYPE_PROMISCUOUS_MULTICAST 0x05
659
660 #define PXE_FRAME_TYPE_MULTICAST PXE_FRAME_TYPE_FILTERED_MULTICAST
661
662 typedef PXE_UINT32 PXE_IPV4;
663
664 typedef PXE_UINT32 PXE_IPV6[4];
665 #define PXE_MAC_LENGTH 32
666
667 typedef PXE_UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH];
668
669 typedef PXE_UINT8 PXE_IFTYPE;
670 typedef UINT16 PXE_MEDIA_PROTOCOL;
671
672 ///
673 /// This information is from the ARP section of RFC 1700.
674 ///
675 /// 1 Ethernet (10Mb) [JBP]
676 /// 2 Experimental Ethernet (3Mb) [JBP]
677 /// 3 Amateur Radio AX.25 [PXK]
678 /// 4 Proteon ProNET Token Ring [JBP]
679 /// 5 Chaos [GXP]
680 /// 6 IEEE 802 Networks [JBP]
681 /// 7 ARCNET [JBP]
682 /// 8 Hyperchannel [JBP]
683 /// 9 Lanstar [TU]
684 /// 10 Autonet Short Address [MXB1]
685 /// 11 LocalTalk [JKR1]
686 /// 12 LocalNet (IBM* PCNet or SYTEK* LocalNET) [JXM]
687 /// 13 Ultra link [RXD2]
688 /// 14 SMDS [GXC1]
689 /// 15 Frame Relay [AGM]
690 /// 16 Asynchronous Transmission Mode (ATM) [JXB2]
691 /// 17 HDLC [JBP]
692 /// 18 Fibre Channel [Yakov Rekhter]
693 /// 19 Asynchronous Transmission Mode (ATM) [Mark Laubach]
694 /// 20 Serial Line [JBP]
695 /// 21 Asynchronous Transmission Mode (ATM) [MXB1]
696 ///
697 /// * Other names and brands may be claimed as the property of others.
698 ///
699 #define PXE_IFTYPE_ETHERNET 0x01
700 #define PXE_IFTYPE_TOKENRING 0x04
701 #define PXE_IFTYPE_FIBRE_CHANNEL 0x12
702
703 typedef struct s_pxe_hw_undi {
704 PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE
705 PXE_UINT8 Len; ///< sizeof(PXE_HW_UNDI)
706 PXE_UINT8 Fudge; ///< makes 8-bit cksum equal zero
707 PXE_UINT8 Rev; ///< PXE_ROMID_REV
708 PXE_UINT8 IFcnt; ///< physical connector count
709 PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER
710 PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER
711 PXE_UINT16 reserved; ///< zero, not used
712 PXE_UINT32 Implementation; ///< implementation flags
713 ///< reserved ///< vendor use
714 ///< UINT32 Status; ///< status port
715 ///< UINT32 Command; ///< command port
716 ///< UINT64 CDBaddr; ///< CDB address port
717 ///<
718 } PXE_HW_UNDI;
719
720 ///
721 /// Status port bit definitions
722 ///
723
724 ///
725 /// UNDI operation state
726 ///
727 #define PXE_HWSTAT_STATE_MASK 0xC0000000
728 #define PXE_HWSTAT_BUSY 0xC0000000
729 #define PXE_HWSTAT_INITIALIZED 0x80000000
730 #define PXE_HWSTAT_STARTED 0x40000000
731 #define PXE_HWSTAT_STOPPED 0x00000000
732
733 ///
734 /// If set, last command failed
735 ///
736 #define PXE_HWSTAT_COMMAND_FAILED 0x20000000
737
738 ///
739 /// If set, identifies enabled receive filters
740 ///
741 #define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000
742 #define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800
743 #define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400
744 #define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200
745 #define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100
746
747 ///
748 /// If set, identifies enabled external interrupts
749 ///
750 #define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080
751 #define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040
752 #define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020
753 #define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010
754
755 ///
756 /// If set, identifies pending interrupts
757 ///
758 #define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008
759 #define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004
760 #define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002
761 #define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001
762
763 ///
764 /// Command port definitions
765 ///
766
767 ///
768 /// If set, CDB identified in CDBaddr port is given to UNDI.
769 /// If not set, other bits in this word will be processed.
770 ///
771 #define PXE_HWCMD_ISSUE_COMMAND 0x80000000
772 #define PXE_HWCMD_INTS_AND_FILTS 0x00000000
773
774 ///
775 /// Use these to enable/disable receive filters.
776 ///
777 #define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000
778 #define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800
779 #define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400
780 #define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200
781 #define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100
782
783 ///
784 /// Use these to enable/disable external interrupts
785 ///
786 #define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080
787 #define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040
788 #define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020
789 #define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010
790
791 ///
792 /// Use these to clear pending external interrupts
793 ///
794 #define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008
795 #define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004
796 #define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002
797 #define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001
798
799 typedef struct s_pxe_sw_undi {
800 PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE
801 PXE_UINT8 Len; ///< sizeof(PXE_SW_UNDI)
802 PXE_UINT8 Fudge; ///< makes 8-bit cksum zero
803 PXE_UINT8 Rev; ///< PXE_ROMID_REV
804 PXE_UINT8 IFcnt; ///< physical connector count
805 PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER
806 PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER
807 PXE_UINT16 reserved1; ///< zero, not used
808 PXE_UINT32 Implementation; ///< Implementation flags
809 PXE_UINT64 EntryPoint; ///< API entry point
810 PXE_UINT8 reserved2[3]; ///< zero, not used
811 PXE_UINT8 BusCnt; ///< number of bustypes supported
812 PXE_UINT32 BusType[1]; ///< list of supported bustypes
813 } PXE_SW_UNDI;
814
815 typedef union u_pxe_undi {
816 PXE_HW_UNDI hw;
817 PXE_SW_UNDI sw;
818 } PXE_UNDI;
819
820 ///
821 /// Signature of !PXE structure
822 ///
823 #define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')
824
825 ///
826 /// !PXE structure format revision
827 ///
828 #define PXE_ROMID_REV 0x02
829
830 ///
831 /// UNDI command interface revision. These are the values that get sent
832 /// in option 94 (Client Network Interface Identifier) in the DHCP Discover
833 /// and PXE Boot Server Request packets.
834 ///
835 #define PXE_ROMID_MAJORVER 0x03
836 #define PXE_ROMID_MINORVER 0x01
837
838 ///
839 /// Implementation flags
840 ///
841 #define PXE_ROMID_IMP_HW_UNDI 0x80000000
842 #define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000
843 #define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000
844 #define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000
845 #define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000
846 #define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000
847 #define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000
848 #define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00
849 #define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00
850 #define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800
851 #define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400
852 #define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000
853 #define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200
854 #define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100
855 #define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080
856 #define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040
857 #define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020
858 #define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010
859 #define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008
860 #define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004
861 #define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002
862 #define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001
863
864 typedef struct s_pxe_cdb {
865 PXE_OPCODE OpCode;
866 PXE_OPFLAGS OpFlags;
867 PXE_UINT16 CPBsize;
868 PXE_UINT16 DBsize;
869 PXE_UINT64 CPBaddr;
870 PXE_UINT64 DBaddr;
871 PXE_STATCODE StatCode;
872 PXE_STATFLAGS StatFlags;
873 PXE_UINT16 IFnum;
874 PXE_CONTROL Control;
875 } PXE_CDB;
876
877 typedef union u_pxe_ip_addr {
878 PXE_IPV6 IPv6;
879 PXE_IPV4 IPv4;
880 } PXE_IP_ADDR;
881
882 typedef union pxe_device {
883 ///
884 /// PCI and PC Card NICs are both identified using bus, device
885 /// and function numbers. For PC Card, this may require PC
886 /// Card services to be loaded in the BIOS or preboot
887 /// environment.
888 ///
889 struct {
890 ///
891 /// See S/W UNDI ROMID structure definition for PCI and
892 /// PCC BusType definitions.
893 ///
894 PXE_UINT32 BusType;
895
896 ///
897 /// Bus, device & function numbers that locate this device.
898 ///
899 PXE_UINT16 Bus;
900 PXE_UINT8 Device;
901 PXE_UINT8 Function;
902 }
903 PCI, PCC;
904
905 } PXE_DEVICE;
906
907 ///
908 /// cpb and db definitions
909 ///
910 #define MAX_PCI_CONFIG_LEN 64 ///< # of dwords
911 #define MAX_EEPROM_LEN 128 ///< # of dwords
912 #define MAX_XMIT_BUFFERS 32 ///< recycling Q length for xmit_done
913 #define MAX_MCAST_ADDRESS_CNT 8
914
915 typedef struct s_pxe_cpb_start_30 {
916 ///
917 /// PXE_VOID Delay(UINTN microseconds);
918 ///
919 /// UNDI will never request a delay smaller than 10 microseconds
920 /// and will always request delays in increments of 10 microseconds.
921 /// The Delay() CallBack routine must delay between n and n + 10
922 /// microseconds before returning control to the UNDI.
923 ///
924 /// This field cannot be set to zero.
925 ///
926 UINT64 Delay;
927
928 ///
929 /// PXE_VOID Block(UINT32 enable);
930 ///
931 /// UNDI may need to block multi-threaded/multi-processor access to
932 /// critical code sections when programming or accessing the network
933 /// device. To this end, a blocking service is needed by the UNDI.
934 /// When UNDI needs a block, it will call Block() passing a non-zero
935 /// value. When UNDI no longer needs a block, it will call Block()
936 /// with a zero value. When called, if the Block() is already enabled,
937 /// do not return control to the UNDI until the previous Block() is
938 /// disabled.
939 ///
940 /// This field cannot be set to zero.
941 ///
942 UINT64 Block;
943
944 ///
945 /// PXE_VOID Virt2Phys(UINT64 virtual, UINT64 physical_ptr);
946 ///
947 /// UNDI will pass the virtual address of a buffer and the virtual
948 /// address of a 64-bit physical buffer. Convert the virtual address
949 /// to a physical address and write the result to the physical address
950 /// buffer. If virtual and physical addresses are the same, just
951 /// copy the virtual address to the physical address buffer.
952 ///
953 /// This field can be set to zero if virtual and physical addresses
954 /// are equal.
955 ///
956 UINT64 Virt2Phys;
957 ///
958 /// PXE_VOID Mem_IO(UINT8 read_write, UINT8 len, UINT64 port,
959 /// UINT64 buf_addr);
960 ///
961 /// UNDI will read or write the device io space using this call back
962 /// function. It passes the number of bytes as the len parameter and it
963 /// will be either 1,2,4 or 8.
964 ///
965 /// This field can not be set to zero.
966 ///
967 UINT64 Mem_IO;
968 } PXE_CPB_START_30;
969
970 typedef struct s_pxe_cpb_start_31 {
971 ///
972 /// PXE_VOID Delay(UINT64 UnqId, UINTN microseconds);
973 ///
974 /// UNDI will never request a delay smaller than 10 microseconds
975 /// and will always request delays in increments of 10 microseconds.
976 /// The Delay() CallBack routine must delay between n and n + 10
977 /// microseconds before returning control to the UNDI.
978 ///
979 /// This field cannot be set to zero.
980 ///
981 UINT64 Delay;
982
983 ///
984 /// PXE_VOID Block(UINT64 unq_id, UINT32 enable);
985 ///
986 /// UNDI may need to block multi-threaded/multi-processor access to
987 /// critical code sections when programming or accessing the network
988 /// device. To this end, a blocking service is needed by the UNDI.
989 /// When UNDI needs a block, it will call Block() passing a non-zero
990 /// value. When UNDI no longer needs a block, it will call Block()
991 /// with a zero value. When called, if the Block() is already enabled,
992 /// do not return control to the UNDI until the previous Block() is
993 /// disabled.
994 ///
995 /// This field cannot be set to zero.
996 ///
997 UINT64 Block;
998
999 ///
1000 /// PXE_VOID Virt2Phys(UINT64 UnqId, UINT64 virtual, UINT64 physical_ptr);
1001 ///
1002 /// UNDI will pass the virtual address of a buffer and the virtual
1003 /// address of a 64-bit physical buffer. Convert the virtual address
1004 /// to a physical address and write the result to the physical address
1005 /// buffer. If virtual and physical addresses are the same, just
1006 /// copy the virtual address to the physical address buffer.
1007 ///
1008 /// This field can be set to zero if virtual and physical addresses
1009 /// are equal.
1010 ///
1011 UINT64 Virt2Phys;
1012 ///
1013 /// PXE_VOID Mem_IO(UINT64 UnqId, UINT8 read_write, UINT8 len, UINT64 port,
1014 /// UINT64 buf_addr);
1015 ///
1016 /// UNDI will read or write the device io space using this call back
1017 /// function. It passes the number of bytes as the len parameter and it
1018 /// will be either 1,2,4 or 8.
1019 ///
1020 /// This field can not be set to zero.
1021 ///
1022 UINT64 Mem_IO;
1023 ///
1024 /// PXE_VOID Map_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
1025 /// UINT32 Direction, UINT64 mapped_addr);
1026 ///
1027 /// UNDI will pass the virtual address of a buffer, direction of the data
1028 /// flow from/to the mapped buffer (the constants are defined below)
1029 /// and a place holder (pointer) for the mapped address.
1030 /// This call will Map the given address to a physical DMA address and write
1031 /// the result to the mapped_addr pointer. If there is no need to
1032 /// map the given address to a lower address (i.e. the given address is
1033 /// associated with a physical address that is already compatible to be
1034 /// used with the DMA, it converts the given virtual address to it's
1035 /// physical address and write that in the mapped address pointer.
1036 ///
1037 /// This field can be set to zero if there is no mapping service available
1038 ///
1039 UINT64 Map_Mem;
1040
1041 ///
1042 /// PXE_VOID UnMap_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
1043 /// UINT32 Direction, UINT64 mapped_addr);
1044 ///
1045 /// UNDI will pass the virtual and mapped addresses of a buffer
1046 /// This call will un map the given address
1047 ///
1048 /// This field can be set to zero if there is no unmapping service available
1049 ///
1050 UINT64 UnMap_Mem;
1051
1052 ///
1053 /// PXE_VOID Sync_Mem(UINT64 unq_id, UINT64 virtual,
1054 /// UINT32 size, UINT32 Direction, UINT64 mapped_addr);
1055 ///
1056 /// UNDI will pass the virtual and mapped addresses of a buffer
1057 /// This call will synchronize the contents of both the virtual and mapped
1058 /// buffers for the given Direction.
1059 ///
1060 /// This field can be set to zero if there is no service available
1061 ///
1062 UINT64 Sync_Mem;
1063
1064 ///
1065 /// protocol driver can provide anything for this Unique_ID, UNDI remembers
1066 /// that as just a 64bit value assocaited to the interface specified by
1067 /// the ifnum and gives it back as a parameter to all the call-back routines
1068 /// when calling for that interface!
1069 ///
1070 UINT64 Unique_ID;
1071 } PXE_CPB_START_31;
1072
1073 #define TO_AND_FROM_DEVICE 0
1074 #define FROM_DEVICE 1
1075 #define TO_DEVICE 2
1076
1077 #define PXE_DELAY_MILLISECOND 1000
1078 #define PXE_DELAY_SECOND 1000000
1079 #define PXE_IO_READ 0
1080 #define PXE_IO_WRITE 1
1081 #define PXE_MEM_READ 2
1082 #define PXE_MEM_WRITE 4
1083
1084 typedef struct s_pxe_db_get_init_info {
1085 ///
1086 /// Minimum length of locked memory buffer that must be given to
1087 /// the Initialize command. Giving UNDI more memory will generally
1088 /// give better performance.
1089 ///
1090 /// If MemoryRequired is zero, the UNDI does not need and will not
1091 /// use system memory to receive and transmit packets.
1092 ///
1093 PXE_UINT32 MemoryRequired;
1094
1095 ///
1096 /// Maximum frame data length for Tx/Rx excluding the media header.
1097 ///
1098 PXE_UINT32 FrameDataLen;
1099
1100 ///
1101 /// Supported link speeds are in units of mega bits. Common ethernet
1102 /// values are 10, 100 and 1000. Unused LinkSpeeds[] entries are zero
1103 /// filled.
1104 ///
1105 PXE_UINT32 LinkSpeeds[4];
1106
1107 ///
1108 /// Number of non-volatile storage items.
1109 ///
1110 PXE_UINT32 NvCount;
1111
1112 ///
1113 /// Width of non-volatile storage item in bytes. 0, 1, 2 or 4
1114 ///
1115 PXE_UINT16 NvWidth;
1116
1117 ///
1118 /// Media header length. This is the typical media header length for
1119 /// this UNDI. This information is needed when allocating receive
1120 /// and transmit buffers.
1121 ///
1122 PXE_UINT16 MediaHeaderLen;
1123
1124 ///
1125 /// Number of bytes in the NIC hardware (MAC) address.
1126 ///
1127 PXE_UINT16 HWaddrLen;
1128
1129 ///
1130 /// Maximum number of multicast MAC addresses in the multicast
1131 /// MAC address filter list.
1132 ///
1133 PXE_UINT16 MCastFilterCnt;
1134
1135 ///
1136 /// Default number and size of transmit and receive buffers that will
1137 /// be allocated by the UNDI. If MemoryRequired is non-zero, this
1138 /// allocation will come out of the memory buffer given to the Initialize
1139 /// command. If MemoryRequired is zero, this allocation will come out of
1140 /// memory on the NIC.
1141 ///
1142 PXE_UINT16 TxBufCnt;
1143 PXE_UINT16 TxBufSize;
1144 PXE_UINT16 RxBufCnt;
1145 PXE_UINT16 RxBufSize;
1146
1147 ///
1148 /// Hardware interface types defined in the Assigned Numbers RFC
1149 /// and used in DHCP and ARP packets.
1150 /// See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros.
1151 ///
1152 PXE_UINT8 IFtype;
1153
1154 ///
1155 /// Supported duplex. See PXE_DUPLEX_xxxxx #defines below.
1156 ///
1157 PXE_UINT8 SupportedDuplexModes;
1158
1159 ///
1160 /// Supported loopback options. See PXE_LOOPBACK_xxxxx #defines below.
1161 ///
1162 PXE_UINT8 SupportedLoopBackModes;
1163 } PXE_DB_GET_INIT_INFO;
1164
1165 #define PXE_MAX_TXRX_UNIT_ETHER 1500
1166
1167 #define PXE_HWADDR_LEN_ETHER 0x0006
1168 #define PXE_MAC_HEADER_LEN_ETHER 0x000E
1169
1170 #define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1
1171 #define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2
1172
1173 #define PXE_LOOPBACK_INTERNAL_SUPPORTED 1
1174 #define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2
1175
1176 typedef struct s_pxe_pci_config_info {
1177 ///
1178 /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
1179 /// For PCI bus devices, this field is set to PXE_BUSTYPE_PCI.
1180 ///
1181 UINT32 BusType;
1182
1183 ///
1184 /// This identifies the PCI network device that this UNDI interface
1185 /// is bound to.
1186 ///
1187 UINT16 Bus;
1188 UINT8 Device;
1189 UINT8 Function;
1190
1191 ///
1192 /// This is a copy of the PCI configuration space for this
1193 /// network device.
1194 ///
1195 union {
1196 UINT8 Byte[256];
1197 UINT16 Word[128];
1198 UINT32 Dword[64];
1199 } Config;
1200 } PXE_PCI_CONFIG_INFO;
1201
1202 typedef struct s_pxe_pcc_config_info {
1203 ///
1204 /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
1205 /// For PCC bus devices, this field is set to PXE_BUSTYPE_PCC.
1206 ///
1207 PXE_UINT32 BusType;
1208
1209 ///
1210 /// This identifies the PCC network device that this UNDI interface
1211 /// is bound to.
1212 ///
1213 PXE_UINT16 Bus;
1214 PXE_UINT8 Device;
1215 PXE_UINT8 Function;
1216
1217 ///
1218 /// This is a copy of the PCC configuration space for this
1219 /// network device.
1220 ///
1221 union {
1222 PXE_UINT8 Byte[256];
1223 PXE_UINT16 Word[128];
1224 PXE_UINT32 Dword[64];
1225 } Config;
1226 } PXE_PCC_CONFIG_INFO;
1227
1228 typedef union u_pxe_db_get_config_info {
1229 PXE_PCI_CONFIG_INFO pci;
1230 PXE_PCC_CONFIG_INFO pcc;
1231 } PXE_DB_GET_CONFIG_INFO;
1232
1233 typedef struct s_pxe_cpb_initialize {
1234 ///
1235 /// Address of first (lowest) byte of the memory buffer. This buffer must
1236 /// be in contiguous physical memory and cannot be swapped out. The UNDI
1237 /// will be using this for transmit and receive buffering.
1238 ///
1239 PXE_UINT64 MemoryAddr;
1240
1241 ///
1242 /// MemoryLength must be greater than or equal to MemoryRequired
1243 /// returned by the Get Init Info command.
1244 ///
1245 PXE_UINT32 MemoryLength;
1246
1247 ///
1248 /// Desired link speed in Mbit/sec. Common ethernet values are 10, 100
1249 /// and 1000. Setting a value of zero will auto-detect and/or use the
1250 /// default link speed (operation depends on UNDI/NIC functionality).
1251 ///
1252 PXE_UINT32 LinkSpeed;
1253
1254 ///
1255 /// Suggested number and size of receive and transmit buffers to
1256 /// allocate. If MemoryAddr and MemoryLength are non-zero, this
1257 /// allocation comes out of the supplied memory buffer. If MemoryAddr
1258 /// and MemoryLength are zero, this allocation comes out of memory
1259 /// on the NIC.
1260 ///
1261 /// If these fields are set to zero, the UNDI will allocate buffer
1262 /// counts and sizes as it sees fit.
1263 ///
1264 PXE_UINT16 TxBufCnt;
1265 PXE_UINT16 TxBufSize;
1266 PXE_UINT16 RxBufCnt;
1267 PXE_UINT16 RxBufSize;
1268
1269 ///
1270 /// The following configuration parameters are optional and must be zero
1271 /// to use the default values.
1272 ///
1273 PXE_UINT8 DuplexMode;
1274
1275 PXE_UINT8 LoopBackMode;
1276 } PXE_CPB_INITIALIZE;
1277
1278 #define PXE_DUPLEX_DEFAULT 0x00
1279 #define PXE_FORCE_FULL_DUPLEX 0x01
1280 #define PXE_ENABLE_FULL_DUPLEX 0x02
1281 #define PXE_FORCE_HALF_DUPLEX 0x04
1282 #define PXE_DISABLE_FULL_DUPLEX 0x08
1283
1284 #define LOOPBACK_NORMAL 0
1285 #define LOOPBACK_INTERNAL 1
1286 #define LOOPBACK_EXTERNAL 2
1287
1288 typedef struct s_pxe_db_initialize {
1289 ///
1290 /// Actual amount of memory used from the supplied memory buffer. This
1291 /// may be less that the amount of memory suppllied and may be zero if
1292 /// the UNDI and network device do not use external memory buffers.
1293 ///
1294 /// Memory used by the UNDI and network device is allocated from the
1295 /// lowest memory buffer address.
1296 ///
1297 PXE_UINT32 MemoryUsed;
1298
1299 ///
1300 /// Actual number and size of receive and transmit buffers that were
1301 /// allocated.
1302 ///
1303 PXE_UINT16 TxBufCnt;
1304 PXE_UINT16 TxBufSize;
1305 PXE_UINT16 RxBufCnt;
1306 PXE_UINT16 RxBufSize;
1307 } PXE_DB_INITIALIZE;
1308
1309 typedef struct s_pxe_cpb_receive_filters {
1310 ///
1311 /// List of multicast MAC addresses. This list, if present, will
1312 /// replace the existing multicast MAC address filter list.
1313 ///
1314 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
1315 } PXE_CPB_RECEIVE_FILTERS;
1316
1317 typedef struct s_pxe_db_receive_filters {
1318 ///
1319 /// Filtered multicast MAC address list.
1320 ///
1321 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
1322 } PXE_DB_RECEIVE_FILTERS;
1323
1324 typedef struct s_pxe_cpb_station_address {
1325 ///
1326 /// If supplied and supported, the current station MAC address
1327 /// will be changed.
1328 ///
1329 PXE_MAC_ADDR StationAddr;
1330 } PXE_CPB_STATION_ADDRESS;
1331
1332 typedef struct s_pxe_dpb_station_address {
1333 ///
1334 /// Current station MAC address.
1335 ///
1336 PXE_MAC_ADDR StationAddr;
1337
1338 ///
1339 /// Station broadcast MAC address.
1340 ///
1341 PXE_MAC_ADDR BroadcastAddr;
1342
1343 ///
1344 /// Permanent station MAC address.
1345 ///
1346 PXE_MAC_ADDR PermanentAddr;
1347 } PXE_DB_STATION_ADDRESS;
1348
1349 typedef struct s_pxe_db_statistics {
1350 ///
1351 /// Bit field identifying what statistic data is collected by the
1352 /// UNDI/NIC.
1353 /// If bit 0x00 is set, Data[0x00] is collected.
1354 /// If bit 0x01 is set, Data[0x01] is collected.
1355 /// If bit 0x20 is set, Data[0x20] is collected.
1356 /// If bit 0x21 is set, Data[0x21] is collected.
1357 /// Etc.
1358 ///
1359 PXE_UINT64 Supported;
1360
1361 ///
1362 /// Statistic data.
1363 ///
1364 PXE_UINT64 Data[64];
1365 } PXE_DB_STATISTICS;
1366
1367 ///
1368 /// Total number of frames received. Includes frames with errors and
1369 /// dropped frames.
1370 ///
1371 #define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00
1372
1373 ///
1374 /// Number of valid frames received and copied into receive buffers.
1375 ///
1376 #define PXE_STATISTICS_RX_GOOD_FRAMES 0x01
1377
1378 ///
1379 /// Number of frames below the minimum length for the media.
1380 /// This would be <64 for ethernet.
1381 ///
1382 #define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02
1383
1384 ///
1385 /// Number of frames longer than the maxminum length for the
1386 /// media. This would be >1500 for ethernet.
1387 ///
1388 #define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03
1389
1390 ///
1391 /// Valid frames that were dropped because receive buffers were full.
1392 ///
1393 #define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04
1394
1395 ///
1396 /// Number of valid unicast frames received and not dropped.
1397 ///
1398 #define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05
1399
1400 ///
1401 /// Number of valid broadcast frames received and not dropped.
1402 ///
1403 #define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06
1404
1405 ///
1406 /// Number of valid mutlicast frames received and not dropped.
1407 ///
1408 #define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07
1409
1410 ///
1411 /// Number of frames w/ CRC or alignment errors.
1412 ///
1413 #define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08
1414
1415 ///
1416 /// Total number of bytes received. Includes frames with errors
1417 /// and dropped frames.
1418 ///
1419 #define PXE_STATISTICS_RX_TOTAL_BYTES 0x09
1420
1421 ///
1422 /// Transmit statistics.
1423 ///
1424 #define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A
1425 #define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B
1426 #define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C
1427 #define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D
1428 #define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E
1429 #define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F
1430 #define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10
1431 #define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11
1432 #define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12
1433 #define PXE_STATISTICS_TX_TOTAL_BYTES 0x13
1434
1435 ///
1436 /// Number of collisions detection on this subnet.
1437 ///
1438 #define PXE_STATISTICS_COLLISIONS 0x14
1439
1440 ///
1441 /// Number of frames destined for unsupported protocol.
1442 ///
1443 #define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15
1444
1445 typedef struct s_pxe_cpb_mcast_ip_to_mac {
1446 ///
1447 /// Multicast IP address to be converted to multicast MAC address.
1448 ///
1449 PXE_IP_ADDR IP;
1450 } PXE_CPB_MCAST_IP_TO_MAC;
1451
1452 typedef struct s_pxe_db_mcast_ip_to_mac {
1453 ///
1454 /// Multicast MAC address.
1455 ///
1456 PXE_MAC_ADDR MAC;
1457 } PXE_DB_MCAST_IP_TO_MAC;
1458
1459 typedef struct s_pxe_cpb_nvdata_sparse {
1460 ///
1461 /// NvData item list. Only items in this list will be updated.
1462 ///
1463 struct {
1464 ///
1465 /// Non-volatile storage address to be changed.
1466 ///
1467 PXE_UINT32 Addr;
1468
1469 ///
1470 /// Data item to write into above storage address.
1471 ///
1472 union {
1473 PXE_UINT8 Byte;
1474 PXE_UINT16 Word;
1475 PXE_UINT32 Dword;
1476 } Data;
1477 } Item[MAX_EEPROM_LEN];
1478 } PXE_CPB_NVDATA_SPARSE;
1479
1480 ///
1481 /// When using bulk update, the size of the CPB structure must be
1482 /// the same size as the non-volatile NIC storage.
1483 ///
1484 typedef union u_pxe_cpb_nvdata_bulk {
1485 ///
1486 /// Array of byte-wide data items.
1487 ///
1488 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];
1489
1490 ///
1491 /// Array of word-wide data items.
1492 ///
1493 PXE_UINT16 Word[MAX_EEPROM_LEN << 1];
1494
1495 ///
1496 /// Array of dword-wide data items.
1497 ///
1498 PXE_UINT32 Dword[MAX_EEPROM_LEN];
1499 } PXE_CPB_NVDATA_BULK;
1500
1501 typedef struct s_pxe_db_nvdata {
1502 ///
1503 /// Arrays of data items from non-volatile storage.
1504 ///
1505 union {
1506 ///
1507 /// Array of byte-wide data items.
1508 ///
1509 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];
1510
1511 ///
1512 /// Array of word-wide data items.
1513 ///
1514 PXE_UINT16 Word[MAX_EEPROM_LEN << 1];
1515
1516 ///
1517 /// Array of dword-wide data items.
1518 ///
1519 PXE_UINT32 Dword[MAX_EEPROM_LEN];
1520 } Data;
1521 } PXE_DB_NVDATA;
1522
1523 typedef struct s_pxe_db_get_status {
1524 ///
1525 /// Length of next receive frame (header + data). If this is zero,
1526 /// there is no next receive frame available.
1527 ///
1528 PXE_UINT32 RxFrameLen;
1529
1530 ///
1531 /// Reserved, set to zero.
1532 ///
1533 PXE_UINT32 reserved;
1534
1535 ///
1536 /// Addresses of transmitted buffers that need to be recycled.
1537 ///
1538 PXE_UINT64 TxBuffer[MAX_XMIT_BUFFERS];
1539 } PXE_DB_GET_STATUS;
1540
1541 typedef struct s_pxe_cpb_fill_header {
1542 ///
1543 /// Source and destination MAC addresses. These will be copied into
1544 /// the media header without doing byte swapping.
1545 ///
1546 PXE_MAC_ADDR SrcAddr;
1547 PXE_MAC_ADDR DestAddr;
1548
1549 ///
1550 /// Address of first byte of media header. The first byte of packet data
1551 /// follows the last byte of the media header.
1552 ///
1553 PXE_UINT64 MediaHeader;
1554
1555 ///
1556 /// Length of packet data in bytes (not including the media header).
1557 ///
1558 PXE_UINT32 PacketLen;
1559
1560 ///
1561 /// Protocol type. This will be copied into the media header without
1562 /// doing byte swapping. Protocol type numbers can be obtained from
1563 /// the Assigned Numbers RFC 1700.
1564 ///
1565 PXE_UINT16 Protocol;
1566
1567 ///
1568 /// Length of the media header in bytes.
1569 ///
1570 PXE_UINT16 MediaHeaderLen;
1571 } PXE_CPB_FILL_HEADER;
1572
1573 #define PXE_PROTOCOL_ETHERNET_IP 0x0800
1574 #define PXE_PROTOCOL_ETHERNET_ARP 0x0806
1575 #define MAX_XMIT_FRAGMENTS 16
1576
1577 typedef struct s_pxe_cpb_fill_header_fragmented {
1578 ///
1579 /// Source and destination MAC addresses. These will be copied into
1580 /// the media header without doing byte swapping.
1581 ///
1582 PXE_MAC_ADDR SrcAddr;
1583 PXE_MAC_ADDR DestAddr;
1584
1585 ///
1586 /// Length of packet data in bytes (not including the media header).
1587 ///
1588 PXE_UINT32 PacketLen;
1589
1590 ///
1591 /// Protocol type. This will be copied into the media header without
1592 /// doing byte swapping. Protocol type numbers can be obtained from
1593 /// the Assigned Numbers RFC 1700.
1594 ///
1595 PXE_MEDIA_PROTOCOL Protocol;
1596
1597 ///
1598 /// Length of the media header in bytes.
1599 ///
1600 PXE_UINT16 MediaHeaderLen;
1601
1602 ///
1603 /// Number of packet fragment descriptors.
1604 ///
1605 PXE_UINT16 FragCnt;
1606
1607 ///
1608 /// Reserved, must be set to zero.
1609 ///
1610 PXE_UINT16 reserved;
1611
1612 ///
1613 /// Array of packet fragment descriptors. The first byte of the media
1614 /// header is the first byte of the first fragment.
1615 ///
1616 struct {
1617 ///
1618 /// Address of this packet fragment.
1619 ///
1620 PXE_UINT64 FragAddr;
1621
1622 ///
1623 /// Length of this packet fragment.
1624 ///
1625 PXE_UINT32 FragLen;
1626
1627 ///
1628 /// Reserved, must be set to zero.
1629 ///
1630 PXE_UINT32 reserved;
1631 } FragDesc[MAX_XMIT_FRAGMENTS];
1632 }
1633 PXE_CPB_FILL_HEADER_FRAGMENTED;
1634
1635 typedef struct s_pxe_cpb_transmit {
1636 ///
1637 /// Address of first byte of frame buffer. This is also the first byte
1638 /// of the media header.
1639 ///
1640 PXE_UINT64 FrameAddr;
1641
1642 ///
1643 /// Length of the data portion of the frame buffer in bytes. Do not
1644 /// include the length of the media header.
1645 ///
1646 PXE_UINT32 DataLen;
1647
1648 ///
1649 /// Length of the media header in bytes.
1650 ///
1651 PXE_UINT16 MediaheaderLen;
1652
1653 ///
1654 /// Reserved, must be zero.
1655 ///
1656 PXE_UINT16 reserved;
1657 } PXE_CPB_TRANSMIT;
1658
1659 typedef struct s_pxe_cpb_transmit_fragments {
1660 ///
1661 /// Length of packet data in bytes (not including the media header).
1662 ///
1663 PXE_UINT32 FrameLen;
1664
1665 ///
1666 /// Length of the media header in bytes.
1667 ///
1668 PXE_UINT16 MediaheaderLen;
1669
1670 ///
1671 /// Number of packet fragment descriptors.
1672 ///
1673 PXE_UINT16 FragCnt;
1674
1675 ///
1676 /// Array of frame fragment descriptors. The first byte of the first
1677 /// fragment is also the first byte of the media header.
1678 ///
1679 struct {
1680 ///
1681 /// Address of this frame fragment.
1682 ///
1683 PXE_UINT64 FragAddr;
1684
1685 ///
1686 /// Length of this frame fragment.
1687 ///
1688 PXE_UINT32 FragLen;
1689
1690 ///
1691 /// Reserved, must be set to zero.
1692 ///
1693 PXE_UINT32 reserved;
1694 } FragDesc[MAX_XMIT_FRAGMENTS];
1695 }
1696 PXE_CPB_TRANSMIT_FRAGMENTS;
1697
1698 typedef struct s_pxe_cpb_receive {
1699 ///
1700 /// Address of first byte of receive buffer. This is also the first byte
1701 /// of the frame header.
1702 ///
1703 PXE_UINT64 BufferAddr;
1704
1705 ///
1706 /// Length of receive buffer. This must be large enough to hold the
1707 /// received frame (media header + data). If the length of smaller than
1708 /// the received frame, data will be lost.
1709 ///
1710 PXE_UINT32 BufferLen;
1711
1712 ///
1713 /// Reserved, must be set to zero.
1714 ///
1715 PXE_UINT32 reserved;
1716 } PXE_CPB_RECEIVE;
1717
1718 typedef struct s_pxe_db_receive {
1719 ///
1720 /// Source and destination MAC addresses from media header.
1721 ///
1722 PXE_MAC_ADDR SrcAddr;
1723 PXE_MAC_ADDR DestAddr;
1724
1725 ///
1726 /// Length of received frame. May be larger than receive buffer size.
1727 /// The receive buffer will not be overwritten. This is how to tell
1728 /// if data was lost because the receive buffer was too small.
1729 ///
1730 PXE_UINT32 FrameLen;
1731
1732 ///
1733 /// Protocol type from media header.
1734 ///
1735 PXE_MEDIA_PROTOCOL Protocol;
1736
1737 ///
1738 /// Length of media header in received frame.
1739 ///
1740 PXE_UINT16 MediaHeaderLen;
1741
1742 ///
1743 /// Type of receive frame.
1744 ///
1745 PXE_FRAME_TYPE Type;
1746
1747 ///
1748 /// Reserved, must be zero.
1749 ///
1750 PXE_UINT8 reserved[7];
1751
1752 } PXE_DB_RECEIVE;
1753
1754 #pragma pack()
1755
1756 #endif