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1 /** @file
2 This header file contains all of the PXE type definitions,
3 structure prototypes, global variables and constants that
4 are needed for porting PXE to EFI.
5
6 Copyright (c) 2006, Intel Corporation
7 All rights reserved. This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 @par Revision Reference:
16 32/64-bit PXE specification:
17 alpha-4, 99-Dec-17
18
19 **/
20
21 #ifndef __EFI_PXE_H__
22 #define __EFI_PXE_H__
23
24 #pragma pack(1)
25
26
27
28 #define PXE_BUSTYPE(a, b, c, d) \
29 ( \
30 (((PXE_UINT32) (d) & 0xFF) << 24) | (((PXE_UINT32) (c) & 0xFF) << 16) | (((PXE_UINT32) (b) & 0xFF) << 8) | \
31 ((PXE_UINT32) (a) & 0xFF) \
32 )
33
34 ///
35 /// UNDI ROM ID and devive ID signature
36 ///
37 #define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E')
38
39 ///
40 /// BUS ROM ID signatures
41 ///
42 #define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R')
43 #define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R')
44 #define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R')
45 #define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4')
46
47 #define PXE_SWAP_UINT16(n) ((((PXE_UINT16) (n) & 0x00FF) << 8) | (((PXE_UINT16) (n) & 0xFF00) >> 8))
48
49 #define PXE_SWAP_UINT32(n) \
50 ((((PXE_UINT32)(n) & 0x000000FF) << 24) | \
51 (((PXE_UINT32)(n) & 0x0000FF00) << 8) | \
52 (((PXE_UINT32)(n) & 0x00FF0000) >> 8) | \
53 (((PXE_UINT32)(n) & 0xFF000000) >> 24))
54
55 #define PXE_SWAP_UINT64(n) \
56 ((((PXE_UINT64)(n) & 0x00000000000000FFULL) << 56) | \
57 (((PXE_UINT64)(n) & 0x000000000000FF00ULL) << 40) | \
58 (((PXE_UINT64)(n) & 0x0000000000FF0000ULL) << 24) | \
59 (((PXE_UINT64)(n) & 0x00000000FF000000ULL) << 8) | \
60 (((PXE_UINT64)(n) & 0x000000FF00000000ULL) >> 8) | \
61 (((PXE_UINT64)(n) & 0x0000FF0000000000ULL) >> 24) | \
62 (((PXE_UINT64)(n) & 0x00FF000000000000ULL) >> 40) | \
63 (((PXE_UINT64)(n) & 0xFF00000000000000ULL) >> 56))
64
65
66 #define PXE_CPBSIZE_NOT_USED 0 // zero
67 #define PXE_DBSIZE_NOT_USED 0 // zero
68 #define PXE_CPBADDR_NOT_USED (PXE_UINT64) 0 // zero
69 #define PXE_DBADDR_NOT_USED (PXE_UINT64) 0 // zero
70 #define PXE_CONST const
71
72 #define PXE_VOLATILE volatile
73
74 typedef VOID PXE_VOID;
75 typedef UINT8 PXE_UINT8;
76 typedef UINT16 PXE_UINT16;
77 typedef UINT32 PXE_UINT32;
78 typedef UINTN PXE_UINTN;
79
80 ///
81 /// typedef unsigned long PXE_UINT64;
82 ///
83 typedef UINT64 PXE_UINT64;
84
85 typedef PXE_UINT8 PXE_BOOL;
86 #define PXE_FALSE 0 // zero
87 #define PXE_TRUE (!PXE_FALSE)
88
89 typedef PXE_UINT16 PXE_OPCODE;
90
91 ///
92 /// Return UNDI operational state.
93 ///
94 #define PXE_OPCODE_GET_STATE 0x0000
95
96 ///
97 /// Change UNDI operational state from Stopped to Started.
98 ///
99 #define PXE_OPCODE_START 0x0001
100
101 ///
102 /// Change UNDI operational state from Started to Stopped.
103 ///
104 #define PXE_OPCODE_STOP 0x0002
105
106 ///
107 /// Get UNDI initialization information.
108 ///
109 #define PXE_OPCODE_GET_INIT_INFO 0x0003
110
111 ///
112 /// Get NIC configuration information.
113 ///
114 #define PXE_OPCODE_GET_CONFIG_INFO 0x0004
115
116 ///
117 /// Changed UNDI operational state from Started to Initialized.
118 ///
119 #define PXE_OPCODE_INITIALIZE 0x0005
120
121 ///
122 /// Re-initialize the NIC H/W.
123 ///
124 #define PXE_OPCODE_RESET 0x0006
125
126 ///
127 /// Change the UNDI operational state from Initialized to Started.
128 ///
129 #define PXE_OPCODE_SHUTDOWN 0x0007
130
131 ///
132 /// Read & change state of external interrupt enables.
133 ///
134 #define PXE_OPCODE_INTERRUPT_ENABLES 0x0008
135
136 ///
137 /// Read & change state of packet receive filters.
138 ///
139 #define PXE_OPCODE_RECEIVE_FILTERS 0x0009
140
141 ///
142 /// Read & change station MAC address.
143 ///
144 #define PXE_OPCODE_STATION_ADDRESS 0x000A
145
146 ///
147 /// Read traffic statistics.
148 ///
149 #define PXE_OPCODE_STATISTICS 0x000B
150
151 ///
152 /// Convert multicast IP address to multicast MAC address.
153 ///
154 #define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C
155
156 ///
157 /// Read or change non-volatile storage on the NIC.
158 ///
159 #define PXE_OPCODE_NVDATA 0x000D
160
161 ///
162 /// Get & clear interrupt status.
163 ///
164 #define PXE_OPCODE_GET_STATUS 0x000E
165
166 ///
167 /// Fill media header in packet for transmit.
168 ///
169 #define PXE_OPCODE_FILL_HEADER 0x000F
170
171 ///
172 /// Transmit packet(s).
173 ///
174 #define PXE_OPCODE_TRANSMIT 0x0010
175
176 ///
177 /// Receive packet.
178 ///
179 #define PXE_OPCODE_RECEIVE 0x0011
180
181 ///
182 /// Last valid PXE UNDI OpCode number.
183 ///
184 #define PXE_OPCODE_LAST_VALID 0x0011
185
186 typedef PXE_UINT16 PXE_OPFLAGS;
187
188 #define PXE_OPFLAGS_NOT_USED 0x0000
189
190 //
191 // //////////////////////////////////////
192 // UNDI Get State
193 //
194 // No OpFlags
195
196 ////////////////////////////////////////
197 // UNDI Start
198 //
199 // No OpFlags
200
201 ////////////////////////////////////////
202 // UNDI Stop
203 //
204 // No OpFlags
205
206 ////////////////////////////////////////
207 // UNDI Get Init Info
208 //
209 // No Opflags
210
211 ////////////////////////////////////////
212 // UNDI Get Config Info
213 //
214 // No Opflags
215
216 ////////////////////////////////////////
217 // UNDI Initialize
218 //
219 #define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001
220 #define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000
221 #define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001
222
223 //
224 // //////////////////////////////////////
225 // UNDI Reset
226 //
227 #define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001
228 #define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002
229
230 //
231 // //////////////////////////////////////
232 // UNDI Shutdown
233 //
234 // No OpFlags
235
236 ////////////////////////////////////////
237 // UNDI Interrupt Enables
238 //
239 //
240 // Select whether to enable or disable external interrupt signals.
241 // Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS.
242 //
243 #define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000
244 #define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000
245 #define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000
246 #define PXE_OPFLAGS_INTERRUPT_READ 0x0000
247
248 ///
249 /// Enable receive interrupts. An external interrupt will be generated
250 /// after a complete non-error packet has been received.
251 ///
252 #define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001
253
254 ///
255 /// Enable transmit interrupts. An external interrupt will be generated
256 /// after a complete non-error packet has been transmitted.
257 ///
258 #define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002
259
260 ///
261 /// Enable command interrupts. An external interrupt will be generated
262 /// when command execution stops.
263 ///
264 #define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004
265
266 ///
267 /// Generate software interrupt. Setting this bit generates an external
268 /// interrupt, if it is supported by the hardware.
269 ///
270 #define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008
271
272 //
273 // //////////////////////////////////////
274 // UNDI Receive Filters
275 //
276 //
277 // Select whether to enable or disable receive filters.
278 // Setting both enable and disable will return PXE_STATCODE_INVALID_OPCODE.
279 //
280 #define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000
281 #define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000
282 #define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000
283 #define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000
284
285 ///
286 /// To reset the contents of the multicast MAC address filter list,
287 /// set this OpFlag:
288 ///
289 #define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000
290
291 ///
292 /// Enable unicast packet receiving. Packets sent to the current station
293 /// MAC address will be received.
294 ///
295 #define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001
296
297 ///
298 /// Enable broadcast packet receiving. Packets sent to the broadcast
299 /// MAC address will be received.
300 ///
301 #define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
302
303 ///
304 /// Enable filtered multicast packet receiving. Packets sent to any
305 /// of the multicast MAC addresses in the multicast MAC address filter
306 /// list will be received. If the filter list is empty, no multicast
307 ///
308 #define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
309
310 ///
311 /// Enable promiscuous packet receiving. All packets will be received.
312 ///
313 #define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
314
315 ///
316 /// Enable promiscuous multicast packet receiving. All multicast
317 /// packets will be received.
318 ///
319 #define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
320
321 //
322 // //////////////////////////////////////
323 // UNDI Station Address
324 //
325 #define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000
326 #define PXE_OPFLAGS_STATION_ADDRESS_WRITE 0x0000
327 #define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001
328
329 //
330 // //////////////////////////////////////
331 // UNDI Statistics
332 //
333 #define PXE_OPFLAGS_STATISTICS_READ 0x0000
334 #define PXE_OPFLAGS_STATISTICS_RESET 0x0001
335
336 //
337 // //////////////////////////////////////
338 // UNDI MCast IP to MAC
339 //
340 //
341 // Identify the type of IP address in the CPB.
342 //
343 #define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003
344 #define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000
345 #define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001
346
347 //
348 // //////////////////////////////////////
349 // UNDI NvData
350 //
351 //
352 // Select the type of non-volatile data operation.
353 //
354 #define PXE_OPFLAGS_NVDATA_OPMASK 0x0001
355 #define PXE_OPFLAGS_NVDATA_READ 0x0000
356 #define PXE_OPFLAGS_NVDATA_WRITE 0x0001
357
358 //
359 // //////////////////////////////////////
360 // UNDI Get Status
361 //
362 //
363 // Return current interrupt status. This will also clear any interrupts
364 // that are currently set. This can be used in a polling routine. The
365 // interrupt flags are still set and cleared even when the interrupts
366 // are disabled.
367 //
368 #define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001
369
370 //
371 // Return list of transmitted buffers for recycling. Transmit buffers
372 // must not be changed or unallocated until they have recycled. After
373 // issuing a transmit command, wait for a transmit complete interrupt.
374 // When a transmit complete interrupt is received, read the transmitted
375 // buffers. Do not plan on getting one buffer per interrupt. Some
376 // NICs and UNDIs may transmit multiple buffers per interrupt.
377 //
378 #define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002
379
380 //
381 // //////////////////////////////////////
382 // UNDI Fill Header
383 //
384 #define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001
385 #define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001
386 #define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000
387
388 //
389 // //////////////////////////////////////
390 // UNDI Transmit
391 //
392 //
393 // S/W UNDI only. Return after the packet has been transmitted. A
394 // transmit complete interrupt will still be generated and the transmit
395 // buffer will have to be recycled.
396 //
397 #define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001
398 #define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001
399 #define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000
400
401 //
402 //
403 //
404 #define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002
405 #define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002
406 #define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000
407
408 //
409 // //////////////////////////////////////
410 // UNDI Receive
411 //
412 // No OpFlags
413 //
414 typedef PXE_UINT16 PXE_STATFLAGS;
415
416 #define PXE_STATFLAGS_INITIALIZE 0x0000
417
418 //
419 // //////////////////////////////////////
420 // Common StatFlags that can be returned by all commands.
421 //
422 //
423 // The COMMAND_COMPLETE and COMMAND_FAILED status flags must be
424 // implemented by all UNDIs. COMMAND_QUEUED is only needed by UNDIs
425 // that support command queuing.
426 //
427 #define PXE_STATFLAGS_STATUS_MASK 0xC000
428 #define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000
429 #define PXE_STATFLAGS_COMMAND_FAILED 0x8000
430 #define PXE_STATFLAGS_COMMAND_QUEUED 0x4000
431
432 //
433 // //////////////////////////////////////
434 // UNDI Get State
435 //
436 #define PXE_STATFLAGS_GET_STATE_MASK 0x0003
437 #define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002
438 #define PXE_STATFLAGS_GET_STATE_STARTED 0x0001
439 #define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000
440
441 //
442 // //////////////////////////////////////
443 // UNDI Start
444 //
445 // No additional StatFlags
446
447 ////////////////////////////////////////
448 // UNDI Get Init Info
449 //
450 #define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001
451 #define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000
452 #define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001
453
454 //
455 // //////////////////////////////////////
456 // UNDI Initialize
457 //
458 #define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001
459
460 //
461 // //////////////////////////////////////
462 // UNDI Reset
463 //
464 #define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001
465
466 //
467 // //////////////////////////////////////
468 // UNDI Shutdown
469 //
470 // No additional StatFlags
471
472 ////////////////////////////////////////
473 // UNDI Interrupt Enables
474 //
475 //
476 // If set, receive interrupts are enabled.
477 //
478 #define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001
479
480 //
481 // If set, transmit interrupts are enabled.
482 //
483 #define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002
484
485 //
486 // If set, command interrupts are enabled.
487 //
488 #define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004
489
490 //
491 // //////////////////////////////////////
492 // UNDI Receive Filters
493 //
494 //
495 // If set, unicast packets will be received.
496 //
497 #define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001
498
499 //
500 // If set, broadcast packets will be received.
501 //
502 #define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
503
504 //
505 // If set, multicast packets that match up with the multicast address
506 // filter list will be received.
507 //
508 #define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
509
510 //
511 // If set, all packets will be received.
512 //
513 #define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
514
515 //
516 // If set, all multicast packets will be received.
517 //
518 #define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
519
520 //
521 // //////////////////////////////////////
522 // UNDI Station Address
523 //
524 // No additional StatFlags
525
526 ////////////////////////////////////////
527 // UNDI Statistics
528 //
529 // No additional StatFlags
530
531 ////////////////////////////////////////
532 // UNDI MCast IP to MAC
533 //
534 // No additional StatFlags
535
536 ////////////////////////////////////////
537 // UNDI NvData
538 //
539 // No additional StatFlags
540
541
542 ////////////////////////////////////////
543 // UNDI Get Status
544 //
545 //
546 // Use to determine if an interrupt has occurred.
547 //
548 #define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F
549 #define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000
550
551 //
552 // If set, at least one receive interrupt occurred.
553 //
554 #define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001
555
556 //
557 // If set, at least one transmit interrupt occurred.
558 //
559 #define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002
560
561 //
562 // If set, at least one command interrupt occurred.
563 //
564 #define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004
565
566 //
567 // If set, at least one software interrupt occurred.
568 //
569 #define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008
570
571 //
572 // This flag is set if the transmitted buffer queue is empty. This flag
573 // will be set if all transmitted buffer addresses get written into the DB.
574 //
575 #define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010
576
577 //
578 // This flag is set if no transmitted buffer addresses were written
579 // into the DB. (This could be because DBsize was too small.)
580 //
581 #define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020
582
583 //
584 // //////////////////////////////////////
585 // UNDI Fill Header
586 //
587 // No additional StatFlags
588
589 ////////////////////////////////////////
590 // UNDI Transmit
591 //
592 // No additional StatFlags.
593
594 ////////////////////////////////////////
595 // UNDI Receive
596 //
597 // No additional StatFlags.
598 //
599 typedef PXE_UINT16 PXE_STATCODE;
600
601 #define PXE_STATCODE_INITIALIZE 0x0000
602
603 //
604 // //////////////////////////////////////
605 // Common StatCodes returned by all UNDI commands, UNDI protocol functions
606 // and BC protocol functions.
607 //
608 #define PXE_STATCODE_SUCCESS 0x0000
609
610 #define PXE_STATCODE_INVALID_CDB 0x0001
611 #define PXE_STATCODE_INVALID_CPB 0x0002
612 #define PXE_STATCODE_BUSY 0x0003
613 #define PXE_STATCODE_QUEUE_FULL 0x0004
614 #define PXE_STATCODE_ALREADY_STARTED 0x0005
615 #define PXE_STATCODE_NOT_STARTED 0x0006
616 #define PXE_STATCODE_NOT_SHUTDOWN 0x0007
617 #define PXE_STATCODE_ALREADY_INITIALIZED 0x0008
618 #define PXE_STATCODE_NOT_INITIALIZED 0x0009
619 #define PXE_STATCODE_DEVICE_FAILURE 0x000A
620 #define PXE_STATCODE_NVDATA_FAILURE 0x000B
621 #define PXE_STATCODE_UNSUPPORTED 0x000C
622 #define PXE_STATCODE_BUFFER_FULL 0x000D
623 #define PXE_STATCODE_INVALID_PARAMETER 0x000E
624 #define PXE_STATCODE_INVALID_UNDI 0x000F
625 #define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010
626 #define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011
627 #define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012
628 #define PXE_STATCODE_NO_DATA 0x0013
629
630 typedef PXE_UINT16 PXE_IFNUM;
631
632 //
633 // This interface number must be passed to the S/W UNDI Start command.
634 //
635 #define PXE_IFNUM_START 0x0000
636
637 //
638 // This interface number is returned by the S/W UNDI Get State and
639 // Start commands if information in the CDB, CPB or DB is invalid.
640 //
641 #define PXE_IFNUM_INVALID 0x0000
642
643 typedef PXE_UINT16 PXE_CONTROL;
644
645 //
646 // Setting this flag directs the UNDI to queue this command for later
647 // execution if the UNDI is busy and it supports command queuing.
648 // If queuing is not supported, a PXE_STATCODE_INVALID_CONTROL error
649 // is returned. If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL
650 // error is returned.
651 //
652 #define PXE_CONTROL_QUEUE_IF_BUSY 0x0002
653
654 //
655 // These two bit values are used to determine if there are more UNDI
656 // CDB structures following this one. If the link bit is set, there
657 // must be a CDB structure following this one. Execution will start
658 // on the next CDB structure as soon as this one completes successfully.
659 // If an error is generated by this command, execution will stop.
660 //
661 #define PXE_CONTROL_LINK 0x0001
662 #define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000
663
664 typedef PXE_UINT8 PXE_FRAME_TYPE;
665
666 #define PXE_FRAME_TYPE_NONE 0x00
667 #define PXE_FRAME_TYPE_UNICAST 0x01
668 #define PXE_FRAME_TYPE_BROADCAST 0x02
669 #define PXE_FRAME_TYPE_FILTERED_MULTICAST 0x03
670 #define PXE_FRAME_TYPE_PROMISCUOUS 0x04
671 #define PXE_FRAME_TYPE_PROMISCUOUS_MULTICAST 0x05
672
673 #define PXE_FRAME_TYPE_MULTICAST PXE_FRAME_TYPE_FILTERED_MULTICAST
674
675 typedef PXE_UINT32 PXE_IPV4;
676
677 typedef PXE_UINT32 PXE_IPV6[4];
678 #define PXE_MAC_LENGTH 32
679
680 typedef PXE_UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH];
681
682 typedef PXE_UINT8 PXE_IFTYPE;
683 typedef UINT16 PXE_MEDIA_PROTOCOL;
684
685 //
686 // This information is from the ARP section of RFC 1700.
687 //
688 // 1 Ethernet (10Mb) [JBP]
689 // 2 Experimental Ethernet (3Mb) [JBP]
690 // 3 Amateur Radio AX.25 [PXK]
691 // 4 Proteon ProNET Token Ring [JBP]
692 // 5 Chaos [GXP]
693 // 6 IEEE 802 Networks [JBP]
694 // 7 ARCNET [JBP]
695 // 8 Hyperchannel [JBP]
696 // 9 Lanstar [TU]
697 // 10 Autonet Short Address [MXB1]
698 // 11 LocalTalk [JKR1]
699 // 12 LocalNet (IBM* PCNet or SYTEK* LocalNET) [JXM]
700 // 13 Ultra link [RXD2]
701 // 14 SMDS [GXC1]
702 // 15 Frame Relay [AGM]
703 // 16 Asynchronous Transmission Mode (ATM) [JXB2]
704 // 17 HDLC [JBP]
705 // 18 Fibre Channel [Yakov Rekhter]
706 // 19 Asynchronous Transmission Mode (ATM) [Mark Laubach]
707 // 20 Serial Line [JBP]
708 // 21 Asynchronous Transmission Mode (ATM) [MXB1]
709 //
710 // * Other names and brands may be claimed as the property of others.
711 //
712 #define PXE_IFTYPE_ETHERNET 0x01
713 #define PXE_IFTYPE_TOKENRING 0x04
714 #define PXE_IFTYPE_FIBRE_CHANNEL 0x12
715
716 typedef struct s_pxe_hw_undi {
717 PXE_UINT32 Signature; // PXE_ROMID_SIGNATURE
718 PXE_UINT8 Len; // sizeof(PXE_HW_UNDI)
719 PXE_UINT8 Fudge; // makes 8-bit cksum equal zero
720 PXE_UINT8 Rev; // PXE_ROMID_REV
721 PXE_UINT8 IFcnt; // physical connector count
722 PXE_UINT8 MajorVer; // PXE_ROMID_MAJORVER
723 PXE_UINT8 MinorVer; // PXE_ROMID_MINORVER
724 PXE_UINT16 reserved; // zero, not used
725 PXE_UINT32 Implementation; // implementation flags
726 // reserved // vendor use
727 // UINT32 Status; // status port
728 // UINT32 Command; // command port
729 // UINT64 CDBaddr; // CDB address port
730 //
731 } PXE_HW_UNDI;
732
733 //
734 // Status port bit definitions
735 //
736 //
737 // UNDI operation state
738 //
739 #define PXE_HWSTAT_STATE_MASK 0xC0000000
740 #define PXE_HWSTAT_BUSY 0xC0000000
741 #define PXE_HWSTAT_INITIALIZED 0x80000000
742 #define PXE_HWSTAT_STARTED 0x40000000
743 #define PXE_HWSTAT_STOPPED 0x00000000
744
745 //
746 // If set, last command failed
747 //
748 #define PXE_HWSTAT_COMMAND_FAILED 0x20000000
749
750 //
751 // If set, identifies enabled receive filters
752 //
753 #define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000
754 #define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800
755 #define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400
756 #define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200
757 #define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100
758
759 //
760 // If set, identifies enabled external interrupts
761 //
762 #define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080
763 #define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040
764 #define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020
765 #define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010
766
767 //
768 // If set, identifies pending interrupts
769 //
770 #define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008
771 #define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004
772 #define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002
773 #define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001
774
775 //
776 // Command port definitions
777 //
778 //
779 // If set, CDB identified in CDBaddr port is given to UNDI.
780 // If not set, other bits in this word will be processed.
781 //
782 #define PXE_HWCMD_ISSUE_COMMAND 0x80000000
783 #define PXE_HWCMD_INTS_AND_FILTS 0x00000000
784
785 //
786 // Use these to enable/disable receive filters.
787 //
788 #define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000
789 #define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800
790 #define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400
791 #define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200
792 #define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100
793
794 //
795 // Use these to enable/disable external interrupts
796 //
797 #define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080
798 #define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040
799 #define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020
800 #define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010
801
802 //
803 // Use these to clear pending external interrupts
804 //
805 #define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008
806 #define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004
807 #define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002
808 #define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001
809
810 typedef struct s_pxe_sw_undi {
811 PXE_UINT32 Signature; // PXE_ROMID_SIGNATURE
812 PXE_UINT8 Len; // sizeof(PXE_SW_UNDI)
813 PXE_UINT8 Fudge; // makes 8-bit cksum zero
814 PXE_UINT8 Rev; // PXE_ROMID_REV
815 PXE_UINT8 IFcnt; // physical connector count
816 PXE_UINT8 MajorVer; // PXE_ROMID_MAJORVER
817 PXE_UINT8 MinorVer; // PXE_ROMID_MINORVER
818 PXE_UINT16 reserved1; // zero, not used
819 PXE_UINT32 Implementation; // Implementation flags
820 PXE_UINT64 EntryPoint; // API entry point
821 PXE_UINT8 reserved2[3]; // zero, not used
822 PXE_UINT8 BusCnt; // number of bustypes supported
823 PXE_UINT32 BusType[1]; // list of supported bustypes
824 } PXE_SW_UNDI;
825
826 typedef union u_pxe_undi {
827 PXE_HW_UNDI hw;
828 PXE_SW_UNDI sw;
829 } PXE_UNDI;
830
831 //
832 // Signature of !PXE structure
833 //
834 #define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')
835
836 //
837 // !PXE structure format revision
838 //
839 #define PXE_ROMID_REV 0x02
840
841 //
842 // UNDI command interface revision. These are the values that get sent
843 // in option 94 (Client Network Interface Identifier) in the DHCP Discover
844 // and PXE Boot Server Request packets.
845 //
846 #define PXE_ROMID_MAJORVER 0x03
847 #define PXE_ROMID_MINORVER 0x01
848
849 //
850 // Implementation flags
851 //
852 #define PXE_ROMID_IMP_HW_UNDI 0x80000000
853 #define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000
854 #define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000
855 #define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000
856 #define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000
857 #define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000
858 #define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000
859 #define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00
860 #define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00
861 #define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800
862 #define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400
863 #define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000
864 #define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200
865 #define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100
866 #define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080
867 #define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040
868 #define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020
869 #define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010
870 #define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008
871 #define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004
872 #define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002
873 #define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001
874
875 typedef struct s_pxe_cdb {
876 PXE_OPCODE OpCode;
877 PXE_OPFLAGS OpFlags;
878 PXE_UINT16 CPBsize;
879 PXE_UINT16 DBsize;
880 PXE_UINT64 CPBaddr;
881 PXE_UINT64 DBaddr;
882 PXE_STATCODE StatCode;
883 PXE_STATFLAGS StatFlags;
884 PXE_UINT16 IFnum;
885 PXE_CONTROL Control;
886 } PXE_CDB;
887
888 typedef union u_pxe_ip_addr {
889 PXE_IPV6 IPv6;
890 PXE_IPV4 IPv4;
891 } PXE_IP_ADDR;
892
893 typedef union pxe_device {
894 //
895 // PCI and PC Card NICs are both identified using bus, device
896 // and function numbers. For PC Card, this may require PC
897 // Card services to be loaded in the BIOS or preboot
898 // environment.
899 //
900 struct {
901 //
902 // See S/W UNDI ROMID structure definition for PCI and
903 // PCC BusType definitions.
904 //
905 PXE_UINT32 BusType;
906
907 //
908 // Bus, device & function numbers that locate this device.
909 //
910 PXE_UINT16 Bus;
911 PXE_UINT8 Device;
912 PXE_UINT8 Function;
913 }
914 PCI, PCC;
915
916 //
917 // %%TBD - More information is needed about enumerating
918 // USB and 1394 devices.
919 //
920 struct {
921 PXE_UINT32 BusType;
922 PXE_UINT32 tdb;
923 }
924 USB, _1394;
925 } PXE_DEVICE;
926
927 //
928 // cpb and db definitions
929 //
930 #define MAX_PCI_CONFIG_LEN 64 // # of dwords
931 #define MAX_EEPROM_LEN 128 // #of dwords
932 #define MAX_XMIT_BUFFERS 32 // recycling Q length for xmit_done
933 #define MAX_MCAST_ADDRESS_CNT 8
934
935 typedef struct s_pxe_cpb_start_30 {
936 //
937 // PXE_VOID Delay(UINTN microseconds);
938 //
939 // UNDI will never request a delay smaller than 10 microseconds
940 // and will always request delays in increments of 10 microseconds.
941 // The Delay() CallBack routine must delay between n and n + 10
942 // microseconds before returning control to the UNDI.
943 //
944 // This field cannot be set to zero.
945 //
946 UINT64 Delay;
947
948 //
949 // PXE_VOID Block(UINT32 enable);
950 //
951 // UNDI may need to block multi-threaded/multi-processor access to
952 // critical code sections when programming or accessing the network
953 // device. To this end, a blocking service is needed by the UNDI.
954 // When UNDI needs a block, it will call Block() passing a non-zero
955 // value. When UNDI no longer needs a block, it will call Block()
956 // with a zero value. When called, if the Block() is already enabled,
957 // do not return control to the UNDI until the previous Block() is
958 // disabled.
959 //
960 // This field cannot be set to zero.
961 //
962 UINT64 Block;
963
964 //
965 // PXE_VOID Virt2Phys(UINT64 virtual, UINT64 physical_ptr);
966 //
967 // UNDI will pass the virtual address of a buffer and the virtual
968 // address of a 64-bit physical buffer. Convert the virtual address
969 // to a physical address and write the result to the physical address
970 // buffer. If virtual and physical addresses are the same, just
971 // copy the virtual address to the physical address buffer.
972 //
973 // This field can be set to zero if virtual and physical addresses
974 // are equal.
975 //
976 UINT64 Virt2Phys;
977 //
978 // PXE_VOID Mem_IO(UINT8 read_write, UINT8 len, UINT64 port,
979 // UINT64 buf_addr);
980 //
981 // UNDI will read or write the device io space using this call back
982 // function. It passes the number of bytes as the len parameter and it
983 // will be either 1,2,4 or 8.
984 //
985 // This field can not be set to zero.
986 //
987 UINT64 Mem_IO;
988 } PXE_CPB_START_30;
989
990 typedef struct s_pxe_cpb_start_31 {
991 //
992 // PXE_VOID Delay(UINT64 UnqId, UINTN microseconds);
993 //
994 // UNDI will never request a delay smaller than 10 microseconds
995 // and will always request delays in increments of 10 microseconds.
996 // The Delay() CallBack routine must delay between n and n + 10
997 // microseconds before returning control to the UNDI.
998 //
999 // This field cannot be set to zero.
1000 //
1001 UINT64 Delay;
1002
1003 //
1004 // PXE_VOID Block(UINT64 unq_id, UINT32 enable);
1005 //
1006 // UNDI may need to block multi-threaded/multi-processor access to
1007 // critical code sections when programming or accessing the network
1008 // device. To this end, a blocking service is needed by the UNDI.
1009 // When UNDI needs a block, it will call Block() passing a non-zero
1010 // value. When UNDI no longer needs a block, it will call Block()
1011 // with a zero value. When called, if the Block() is already enabled,
1012 // do not return control to the UNDI until the previous Block() is
1013 // disabled.
1014 //
1015 // This field cannot be set to zero.
1016 //
1017 UINT64 Block;
1018
1019 //
1020 // PXE_VOID Virt2Phys(UINT64 UnqId, UINT64 virtual, UINT64 physical_ptr);
1021 //
1022 // UNDI will pass the virtual address of a buffer and the virtual
1023 // address of a 64-bit physical buffer. Convert the virtual address
1024 // to a physical address and write the result to the physical address
1025 // buffer. If virtual and physical addresses are the same, just
1026 // copy the virtual address to the physical address buffer.
1027 //
1028 // This field can be set to zero if virtual and physical addresses
1029 // are equal.
1030 //
1031 UINT64 Virt2Phys;
1032 //
1033 // PXE_VOID Mem_IO(UINT64 UnqId, UINT8 read_write, UINT8 len, UINT64 port,
1034 // UINT64 buf_addr);
1035 //
1036 // UNDI will read or write the device io space using this call back
1037 // function. It passes the number of bytes as the len parameter and it
1038 // will be either 1,2,4 or 8.
1039 //
1040 // This field can not be set to zero.
1041 //
1042 UINT64 Mem_IO;
1043 //
1044 // PXE_VOID Map_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
1045 // UINT32 Direction, UINT64 mapped_addr);
1046 //
1047 // UNDI will pass the virtual address of a buffer, direction of the data
1048 // flow from/to the mapped buffer (the constants are defined below)
1049 // and a place holder (pointer) for the mapped address.
1050 // This call will Map the given address to a physical DMA address and write
1051 // the result to the mapped_addr pointer. If there is no need to
1052 // map the given address to a lower address (i.e. the given address is
1053 // associated with a physical address that is already compatible to be
1054 // used with the DMA, it converts the given virtual address to it's
1055 // physical address and write that in the mapped address pointer.
1056 //
1057 // This field can be set to zero if there is no mapping service available
1058 //
1059 UINT64 Map_Mem;
1060
1061 //
1062 // PXE_VOID UnMap_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
1063 // UINT32 Direction, UINT64 mapped_addr);
1064 //
1065 // UNDI will pass the virtual and mapped addresses of a buffer
1066 // This call will un map the given address
1067 //
1068 // This field can be set to zero if there is no unmapping service available
1069 //
1070 UINT64 UnMap_Mem;
1071
1072 //
1073 // PXE_VOID Sync_Mem(UINT64 unq_id, UINT64 virtual,
1074 // UINT32 size, UINT32 Direction, UINT64 mapped_addr);
1075 //
1076 // UNDI will pass the virtual and mapped addresses of a buffer
1077 // This call will synchronize the contents of both the virtual and mapped
1078 // buffers for the given Direction.
1079 //
1080 // This field can be set to zero if there is no service available
1081 //
1082 UINT64 Sync_Mem;
1083
1084 //
1085 // protocol driver can provide anything for this Unique_ID, UNDI remembers
1086 // that as just a 64bit value assocaited to the interface specified by
1087 // the ifnum and gives it back as a parameter to all the call-back routines
1088 // when calling for that interface!
1089 //
1090 UINT64 Unique_ID;
1091 //
1092 } PXE_CPB_START_31;
1093
1094 #define TO_AND_FROM_DEVICE 0
1095 #define FROM_DEVICE 1
1096 #define TO_DEVICE 2
1097
1098 #define PXE_DELAY_MILLISECOND 1000
1099 #define PXE_DELAY_SECOND 1000000
1100 #define PXE_IO_READ 0
1101 #define PXE_IO_WRITE 1
1102 #define PXE_MEM_READ 2
1103 #define PXE_MEM_WRITE 4
1104
1105 typedef struct s_pxe_db_get_init_info {
1106 //
1107 // Minimum length of locked memory buffer that must be given to
1108 // the Initialize command. Giving UNDI more memory will generally
1109 // give better performance.
1110 //
1111 // If MemoryRequired is zero, the UNDI does not need and will not
1112 // use system memory to receive and transmit packets.
1113 //
1114 PXE_UINT32 MemoryRequired;
1115
1116 //
1117 // Maximum frame data length for Tx/Rx excluding the media header.
1118 //
1119 PXE_UINT32 FrameDataLen;
1120
1121 //
1122 // Supported link speeds are in units of mega bits. Common ethernet
1123 // values are 10, 100 and 1000. Unused LinkSpeeds[] entries are zero
1124 // filled.
1125 //
1126 PXE_UINT32 LinkSpeeds[4];
1127
1128 //
1129 // Number of non-volatile storage items.
1130 //
1131 PXE_UINT32 NvCount;
1132
1133 //
1134 // Width of non-volatile storage item in bytes. 0, 1, 2 or 4
1135 //
1136 PXE_UINT16 NvWidth;
1137
1138 //
1139 // Media header length. This is the typical media header length for
1140 // this UNDI. This information is needed when allocating receive
1141 // and transmit buffers.
1142 //
1143 PXE_UINT16 MediaHeaderLen;
1144
1145 //
1146 // Number of bytes in the NIC hardware (MAC) address.
1147 //
1148 PXE_UINT16 HWaddrLen;
1149
1150 //
1151 // Maximum number of multicast MAC addresses in the multicast
1152 // MAC address filter list.
1153 //
1154 PXE_UINT16 MCastFilterCnt;
1155
1156 //
1157 // Default number and size of transmit and receive buffers that will
1158 // be allocated by the UNDI. If MemoryRequired is non-zero, this
1159 // allocation will come out of the memory buffer given to the Initialize
1160 // command. If MemoryRequired is zero, this allocation will come out of
1161 // memory on the NIC.
1162 //
1163 PXE_UINT16 TxBufCnt;
1164 PXE_UINT16 TxBufSize;
1165 PXE_UINT16 RxBufCnt;
1166 PXE_UINT16 RxBufSize;
1167
1168 //
1169 // Hardware interface types defined in the Assigned Numbers RFC
1170 // and used in DHCP and ARP packets.
1171 // See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros.
1172 //
1173 PXE_UINT8 IFtype;
1174
1175 //
1176 // Supported duplex. See PXE_DUPLEX_xxxxx #defines below.
1177 //
1178 PXE_UINT8 SupportedDuplexModes;
1179
1180 //
1181 // Supported loopback options. See PXE_LOOPBACK_xxxxx #defines below.
1182 //
1183 PXE_UINT8 SupportedLoopBackModes;
1184 } PXE_DB_GET_INIT_INFO;
1185
1186 #define PXE_MAX_TXRX_UNIT_ETHER 1500
1187
1188 #define PXE_HWADDR_LEN_ETHER 0x0006
1189 #define PXE_MAC_HEADER_LEN_ETHER 0x000E
1190
1191 #define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1
1192 #define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2
1193
1194 #define PXE_LOOPBACK_INTERNAL_SUPPORTED 1
1195 #define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2
1196
1197 typedef struct s_pxe_pci_config_info {
1198 //
1199 // This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
1200 // For PCI bus devices, this field is set to PXE_BUSTYPE_PCI.
1201 //
1202 UINT32 BusType;
1203
1204 //
1205 // This identifies the PCI network device that this UNDI interface
1206 // is bound to.
1207 //
1208 UINT16 Bus;
1209 UINT8 Device;
1210 UINT8 Function;
1211
1212 //
1213 // This is a copy of the PCI configuration space for this
1214 // network device.
1215 //
1216 union {
1217 UINT8 Byte[256];
1218 UINT16 Word[128];
1219 UINT32 Dword[64];
1220 } Config;
1221 } PXE_PCI_CONFIG_INFO;
1222
1223 typedef struct s_pxe_pcc_config_info {
1224 //
1225 // This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
1226 // For PCC bus devices, this field is set to PXE_BUSTYPE_PCC.
1227 //
1228 PXE_UINT32 BusType;
1229
1230 //
1231 // This identifies the PCC network device that this UNDI interface
1232 // is bound to.
1233 //
1234 PXE_UINT16 Bus;
1235 PXE_UINT8 Device;
1236 PXE_UINT8 Function;
1237
1238 //
1239 // This is a copy of the PCC configuration space for this
1240 // network device.
1241 //
1242 union {
1243 PXE_UINT8 Byte[256];
1244 PXE_UINT16 Word[128];
1245 PXE_UINT32 Dword[64];
1246 } Config;
1247 } PXE_PCC_CONFIG_INFO;
1248
1249 typedef union u_pxe_db_get_config_info {
1250 PXE_PCI_CONFIG_INFO pci;
1251 PXE_PCC_CONFIG_INFO pcc;
1252 } PXE_DB_GET_CONFIG_INFO;
1253
1254 typedef struct s_pxe_cpb_initialize {
1255 //
1256 // Address of first (lowest) byte of the memory buffer. This buffer must
1257 // be in contiguous physical memory and cannot be swapped out. The UNDI
1258 // will be using this for transmit and receive buffering.
1259 //
1260 PXE_UINT64 MemoryAddr;
1261
1262 //
1263 // MemoryLength must be greater than or equal to MemoryRequired
1264 // returned by the Get Init Info command.
1265 //
1266 PXE_UINT32 MemoryLength;
1267
1268 //
1269 // Desired link speed in Mbit/sec. Common ethernet values are 10, 100
1270 // and 1000. Setting a value of zero will auto-detect and/or use the
1271 // default link speed (operation depends on UNDI/NIC functionality).
1272 //
1273 PXE_UINT32 LinkSpeed;
1274
1275 //
1276 // Suggested number and size of receive and transmit buffers to
1277 // allocate. If MemoryAddr and MemoryLength are non-zero, this
1278 // allocation comes out of the supplied memory buffer. If MemoryAddr
1279 // and MemoryLength are zero, this allocation comes out of memory
1280 // on the NIC.
1281 //
1282 // If these fields are set to zero, the UNDI will allocate buffer
1283 // counts and sizes as it sees fit.
1284 //
1285 PXE_UINT16 TxBufCnt;
1286 PXE_UINT16 TxBufSize;
1287 PXE_UINT16 RxBufCnt;
1288 PXE_UINT16 RxBufSize;
1289
1290 //
1291 // The following configuration parameters are optional and must be zero
1292 // to use the default values.
1293 //
1294 PXE_UINT8 DuplexMode;
1295
1296 PXE_UINT8 LoopBackMode;
1297 } PXE_CPB_INITIALIZE;
1298
1299 #define PXE_DUPLEX_DEFAULT 0x00
1300 #define PXE_FORCE_FULL_DUPLEX 0x01
1301 #define PXE_ENABLE_FULL_DUPLEX 0x02
1302 #define PXE_FORCE_HALF_DUPLEX 0x04
1303 #define PXE_DISABLE_FULL_DUPLEX 0x08
1304
1305 #define LOOPBACK_NORMAL 0
1306 #define LOOPBACK_INTERNAL 1
1307 #define LOOPBACK_EXTERNAL 2
1308
1309 typedef struct s_pxe_db_initialize {
1310 //
1311 // Actual amount of memory used from the supplied memory buffer. This
1312 // may be less that the amount of memory suppllied and may be zero if
1313 // the UNDI and network device do not use external memory buffers.
1314 //
1315 // Memory used by the UNDI and network device is allocated from the
1316 // lowest memory buffer address.
1317 //
1318 PXE_UINT32 MemoryUsed;
1319
1320 //
1321 // Actual number and size of receive and transmit buffers that were
1322 // allocated.
1323 //
1324 PXE_UINT16 TxBufCnt;
1325 PXE_UINT16 TxBufSize;
1326 PXE_UINT16 RxBufCnt;
1327 PXE_UINT16 RxBufSize;
1328 } PXE_DB_INITIALIZE;
1329
1330 typedef struct s_pxe_cpb_receive_filters {
1331 //
1332 // List of multicast MAC addresses. This list, if present, will
1333 // replace the existing multicast MAC address filter list.
1334 //
1335 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
1336 } PXE_CPB_RECEIVE_FILTERS;
1337
1338 typedef struct s_pxe_db_receive_filters {
1339 //
1340 // Filtered multicast MAC address list.
1341 //
1342 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
1343 } PXE_DB_RECEIVE_FILTERS;
1344
1345 typedef struct s_pxe_cpb_station_address {
1346 //
1347 // If supplied and supported, the current station MAC address
1348 // will be changed.
1349 //
1350 PXE_MAC_ADDR StationAddr;
1351 } PXE_CPB_STATION_ADDRESS;
1352
1353 typedef struct s_pxe_dpb_station_address {
1354 //
1355 // Current station MAC address.
1356 //
1357 PXE_MAC_ADDR StationAddr;
1358
1359 //
1360 // Station broadcast MAC address.
1361 //
1362 PXE_MAC_ADDR BroadcastAddr;
1363
1364 //
1365 // Permanent station MAC address.
1366 //
1367 PXE_MAC_ADDR PermanentAddr;
1368 } PXE_DB_STATION_ADDRESS;
1369
1370 typedef struct s_pxe_db_statistics {
1371 //
1372 // Bit field identifying what statistic data is collected by the
1373 // UNDI/NIC.
1374 // If bit 0x00 is set, Data[0x00] is collected.
1375 // If bit 0x01 is set, Data[0x01] is collected.
1376 // If bit 0x20 is set, Data[0x20] is collected.
1377 // If bit 0x21 is set, Data[0x21] is collected.
1378 // Etc.
1379 //
1380 PXE_UINT64 Supported;
1381
1382 //
1383 // Statistic data.
1384 //
1385 PXE_UINT64 Data[64];
1386 } PXE_DB_STATISTICS;
1387
1388 //
1389 // Total number of frames received. Includes frames with errors and
1390 // dropped frames.
1391 //
1392 #define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00
1393
1394 //
1395 // Number of valid frames received and copied into receive buffers.
1396 //
1397 #define PXE_STATISTICS_RX_GOOD_FRAMES 0x01
1398
1399 //
1400 // Number of frames below the minimum length for the media.
1401 // This would be <64 for ethernet.
1402 //
1403 #define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02
1404
1405 //
1406 // Number of frames longer than the maxminum length for the
1407 // media. This would be >1500 for ethernet.
1408 //
1409 #define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03
1410
1411 //
1412 // Valid frames that were dropped because receive buffers were full.
1413 //
1414 #define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04
1415
1416 //
1417 // Number of valid unicast frames received and not dropped.
1418 //
1419 #define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05
1420
1421 //
1422 // Number of valid broadcast frames received and not dropped.
1423 //
1424 #define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06
1425
1426 //
1427 // Number of valid mutlicast frames received and not dropped.
1428 //
1429 #define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07
1430
1431 //
1432 // Number of frames w/ CRC or alignment errors.
1433 //
1434 #define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08
1435
1436 //
1437 // Total number of bytes received. Includes frames with errors
1438 // and dropped frames.
1439 //
1440 #define PXE_STATISTICS_RX_TOTAL_BYTES 0x09
1441
1442 //
1443 // Transmit statistics.
1444 //
1445 #define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A
1446 #define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B
1447 #define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C
1448 #define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D
1449 #define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E
1450 #define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F
1451 #define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10
1452 #define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11
1453 #define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12
1454 #define PXE_STATISTICS_TX_TOTAL_BYTES 0x13
1455
1456 //
1457 // Number of collisions detection on this subnet.
1458 //
1459 #define PXE_STATISTICS_COLLISIONS 0x14
1460
1461 //
1462 // Number of frames destined for unsupported protocol.
1463 //
1464 #define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15
1465
1466 typedef struct s_pxe_cpb_mcast_ip_to_mac {
1467 //
1468 // Multicast IP address to be converted to multicast MAC address.
1469 //
1470 PXE_IP_ADDR IP;
1471 } PXE_CPB_MCAST_IP_TO_MAC;
1472
1473 typedef struct s_pxe_db_mcast_ip_to_mac {
1474 //
1475 // Multicast MAC address.
1476 //
1477 PXE_MAC_ADDR MAC;
1478 } PXE_DB_MCAST_IP_TO_MAC;
1479
1480 typedef struct s_pxe_cpb_nvdata_sparse {
1481 //
1482 // NvData item list. Only items in this list will be updated.
1483 //
1484 struct {
1485 //
1486 // Non-volatile storage address to be changed.
1487 //
1488 PXE_UINT32 Addr;
1489
1490 //
1491 // Data item to write into above storage address.
1492 //
1493 union {
1494 PXE_UINT8 Byte;
1495 PXE_UINT16 Word;
1496 PXE_UINT32 Dword;
1497 } Data;
1498 } Item[MAX_EEPROM_LEN];
1499 }
1500 PXE_CPB_NVDATA_SPARSE;
1501
1502 //
1503 // When using bulk update, the size of the CPB structure must be
1504 // the same size as the non-volatile NIC storage.
1505 //
1506 typedef union u_pxe_cpb_nvdata_bulk {
1507 //
1508 // Array of byte-wide data items.
1509 //
1510 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];
1511
1512 //
1513 // Array of word-wide data items.
1514 //
1515 PXE_UINT16 Word[MAX_EEPROM_LEN << 1];
1516
1517 //
1518 // Array of dword-wide data items.
1519 //
1520 PXE_UINT32 Dword[MAX_EEPROM_LEN];
1521 } PXE_CPB_NVDATA_BULK;
1522
1523 typedef struct s_pxe_db_nvdata {
1524 //
1525 // Arrays of data items from non-volatile storage.
1526 //
1527 union {
1528 //
1529 // Array of byte-wide data items.
1530 //
1531 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];
1532
1533 //
1534 // Array of word-wide data items.
1535 //
1536 PXE_UINT16 Word[MAX_EEPROM_LEN << 1];
1537
1538 //
1539 // Array of dword-wide data items.
1540 //
1541 PXE_UINT32 Dword[MAX_EEPROM_LEN];
1542 } Data;
1543 } PXE_DB_NVDATA;
1544
1545 typedef struct s_pxe_db_get_status {
1546 //
1547 // Length of next receive frame (header + data). If this is zero,
1548 // there is no next receive frame available.
1549 //
1550 PXE_UINT32 RxFrameLen;
1551
1552 //
1553 // Reserved, set to zero.
1554 //
1555 PXE_UINT32 reserved;
1556
1557 //
1558 // Addresses of transmitted buffers that need to be recycled.
1559 //
1560 PXE_UINT64 TxBuffer[MAX_XMIT_BUFFERS];
1561 } PXE_DB_GET_STATUS;
1562
1563 typedef struct s_pxe_cpb_fill_header {
1564 //
1565 // Source and destination MAC addresses. These will be copied into
1566 // the media header without doing byte swapping.
1567 //
1568 PXE_MAC_ADDR SrcAddr;
1569 PXE_MAC_ADDR DestAddr;
1570
1571 //
1572 // Address of first byte of media header. The first byte of packet data
1573 // follows the last byte of the media header.
1574 //
1575 PXE_UINT64 MediaHeader;
1576
1577 //
1578 // Length of packet data in bytes (not including the media header).
1579 //
1580 PXE_UINT32 PacketLen;
1581
1582 //
1583 // Protocol type. This will be copied into the media header without
1584 // doing byte swapping. Protocol type numbers can be obtained from
1585 // the Assigned Numbers RFC 1700.
1586 //
1587 PXE_UINT16 Protocol;
1588
1589 //
1590 // Length of the media header in bytes.
1591 //
1592 PXE_UINT16 MediaHeaderLen;
1593 } PXE_CPB_FILL_HEADER;
1594
1595 #define PXE_PROTOCOL_ETHERNET_IP 0x0800
1596 #define PXE_PROTOCOL_ETHERNET_ARP 0x0806
1597 #define MAX_XMIT_FRAGMENTS 16
1598
1599 typedef struct s_pxe_cpb_fill_header_fragmented {
1600 //
1601 // Source and destination MAC addresses. These will be copied into
1602 // the media header without doing byte swapping.
1603 //
1604 PXE_MAC_ADDR SrcAddr;
1605 PXE_MAC_ADDR DestAddr;
1606
1607 //
1608 // Length of packet data in bytes (not including the media header).
1609 //
1610 PXE_UINT32 PacketLen;
1611
1612 //
1613 // Protocol type. This will be copied into the media header without
1614 // doing byte swapping. Protocol type numbers can be obtained from
1615 // the Assigned Numbers RFC 1700.
1616 //
1617 PXE_MEDIA_PROTOCOL Protocol;
1618
1619 //
1620 // Length of the media header in bytes.
1621 //
1622 PXE_UINT16 MediaHeaderLen;
1623
1624 //
1625 // Number of packet fragment descriptors.
1626 //
1627 PXE_UINT16 FragCnt;
1628
1629 //
1630 // Reserved, must be set to zero.
1631 //
1632 PXE_UINT16 reserved;
1633
1634 //
1635 // Array of packet fragment descriptors. The first byte of the media
1636 // header is the first byte of the first fragment.
1637 //
1638 struct {
1639 //
1640 // Address of this packet fragment.
1641 //
1642 PXE_UINT64 FragAddr;
1643
1644 //
1645 // Length of this packet fragment.
1646 //
1647 PXE_UINT32 FragLen;
1648
1649 //
1650 // Reserved, must be set to zero.
1651 //
1652 PXE_UINT32 reserved;
1653 } FragDesc[MAX_XMIT_FRAGMENTS];
1654 }
1655 PXE_CPB_FILL_HEADER_FRAGMENTED;
1656
1657 typedef struct s_pxe_cpb_transmit {
1658 //
1659 // Address of first byte of frame buffer. This is also the first byte
1660 // of the media header.
1661 //
1662 PXE_UINT64 FrameAddr;
1663
1664 //
1665 // Length of the data portion of the frame buffer in bytes. Do not
1666 // include the length of the media header.
1667 //
1668 PXE_UINT32 DataLen;
1669
1670 //
1671 // Length of the media header in bytes.
1672 //
1673 PXE_UINT16 MediaheaderLen;
1674
1675 //
1676 // Reserved, must be zero.
1677 //
1678 PXE_UINT16 reserved;
1679 } PXE_CPB_TRANSMIT;
1680
1681 typedef struct s_pxe_cpb_transmit_fragments {
1682 //
1683 // Length of packet data in bytes (not including the media header).
1684 //
1685 PXE_UINT32 FrameLen;
1686
1687 //
1688 // Length of the media header in bytes.
1689 //
1690 PXE_UINT16 MediaheaderLen;
1691
1692 //
1693 // Number of packet fragment descriptors.
1694 //
1695 PXE_UINT16 FragCnt;
1696
1697 //
1698 // Array of frame fragment descriptors. The first byte of the first
1699 // fragment is also the first byte of the media header.
1700 //
1701 struct {
1702 //
1703 // Address of this frame fragment.
1704 //
1705 PXE_UINT64 FragAddr;
1706
1707 //
1708 // Length of this frame fragment.
1709 //
1710 PXE_UINT32 FragLen;
1711
1712 //
1713 // Reserved, must be set to zero.
1714 //
1715 PXE_UINT32 reserved;
1716 } FragDesc[MAX_XMIT_FRAGMENTS];
1717 }
1718 PXE_CPB_TRANSMIT_FRAGMENTS;
1719
1720 typedef struct s_pxe_cpb_receive {
1721 //
1722 // Address of first byte of receive buffer. This is also the first byte
1723 // of the frame header.
1724 //
1725 PXE_UINT64 BufferAddr;
1726
1727 //
1728 // Length of receive buffer. This must be large enough to hold the
1729 // received frame (media header + data). If the length of smaller than
1730 // the received frame, data will be lost.
1731 //
1732 PXE_UINT32 BufferLen;
1733
1734 //
1735 // Reserved, must be set to zero.
1736 //
1737 PXE_UINT32 reserved;
1738 } PXE_CPB_RECEIVE;
1739
1740 typedef struct s_pxe_db_receive {
1741 //
1742 // Source and destination MAC addresses from media header.
1743 //
1744 PXE_MAC_ADDR SrcAddr;
1745 PXE_MAC_ADDR DestAddr;
1746
1747 //
1748 // Length of received frame. May be larger than receive buffer size.
1749 // The receive buffer will not be overwritten. This is how to tell
1750 // if data was lost because the receive buffer was too small.
1751 //
1752 PXE_UINT32 FrameLen;
1753
1754 //
1755 // Protocol type from media header.
1756 //
1757 PXE_MEDIA_PROTOCOL Protocol;
1758
1759 //
1760 // Length of media header in received frame.
1761 //
1762 PXE_UINT16 MediaHeaderLen;
1763
1764 //
1765 // Type of receive frame.
1766 //
1767 PXE_FRAME_TYPE Type;
1768
1769 //
1770 // Reserved, must be zero.
1771 //
1772 PXE_UINT8 reserved[7];
1773
1774 } PXE_DB_RECEIVE;
1775
1776 //
1777 // Packet definitions
1778 //
1779 typedef struct {
1780 UINT8 BootpOpcode;
1781 UINT8 BootpHwType;
1782 UINT8 BootpHwAddrLen;
1783 UINT8 BootpGateHops;
1784 UINT32 BootpIdent;
1785 UINT16 BootpSeconds;
1786 UINT16 BootpFlags;
1787 UINT8 BootpCiAddr[4];
1788 UINT8 BootpYiAddr[4];
1789 UINT8 BootpSiAddr[4];
1790 UINT8 BootpGiAddr[4];
1791 UINT8 BootpHwAddr[16];
1792 UINT8 BootpSrvName[64];
1793 UINT8 BootpBootFile[128];
1794 UINT32 DhcpMagik;
1795 UINT8 DhcpOptions[56];
1796 } EFI_PXE_BASE_CODE_DHCPV4_PACKET;
1797
1798 typedef union {
1799 UINT8 Raw[1472];
1800 EFI_PXE_BASE_CODE_DHCPV4_PACKET Dhcpv4;
1801
1802 //
1803 // EFI_PXE_BASE_CODE_DHCPV6_PACKET Dhcpv6;
1804 //
1805 } EFI_PXE_BASE_CODE_PACKET;
1806
1807
1808
1809 #pragma pack()
1810
1811 #endif