7870c2bc8bf63eb2f488f87640ee7bde40ab6000
[mirror_edk2.git] / MdePkg / Library / BaseCacheMaintenanceLib / Ipf / Cpu.s
1 //++
2 // Copyright (c) 2006, Intel Corporation
3 // All rights reserved. This program and the accompanying materials
4 // are licensed and made available under the terms and conditions of the BSD License
5 // which accompanies this distribution. The full text of the license may be found at
6 // http://opensource.org/licenses/bsd-license.php
7 //
8 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
10 //
11 // Module Name:
12 //
13 // Cpu.s
14 //
15 // Abstract:
16 //
17 //
18 // Revision History:
19 //
20 //--
21
22 .file "Cpu.s"
23 .radix D
24 .section .text, "ax", "progbits"
25 .align 32
26 .section .pdata, "a", "progbits"
27 .align 4
28 .section .xdata, "a", "progbits"
29 .align 8
30 .section .data, "wa", "progbits"
31 .align 16
32 .section .rdata, "a", "progbits"
33 .align 16
34 .section .bss, "wa", "nobits"
35 .align 16
36 .section .tls$, "was", "progbits"
37 .align 16
38 .section .sdata, "was", "progbits"
39 .align 16
40 .section .sbss, "was", "nobits"
41 .align 16
42 .section .srdata, "as", "progbits"
43 .align 16
44 .section .rdata, "a", "progbits"
45 .align 16
46 .section .rtcode, "ax", "progbits"
47 .align 32
48 .type InvalidateInstructionCacheRange# ,@function
49 .globl InvalidateInstructionCacheRange#
50 // Function compile flags: /Ogsy
51 .section .rtcode
52
53 // Begin code for function: InvalidateInstructionCacheRange:
54 .proc InvalidateInstructionCacheRange#
55 .align 32
56 InvalidateInstructionCacheRange:
57 // File e:\tmp\pioflush.c
58 { .mii //R-Addr: 0X00
59 alloc r3=2, 0, 0, 0 //11, 00000002H
60 cmp4.leu p0,p6=32, r33;; //15, 00000020H
61 (p6) mov r33=32;; //16, 00000020H
62 }
63 { .mii //R-Addr: 0X010
64 nop.m 0
65 zxt4 r29=r33;; //21
66 dep.z r30=r29, 0, 5;; //21, 00000005H
67 }
68 { .mii //R-Addr: 0X020
69 cmp4.eq p0,p7=r0, r30 //21
70 shr.u r28=r29, 5;; //19, 00000005H
71 (p7) adds r28=1, r28;; //22, 00000001H
72 }
73 { .mii //R-Addr: 0X030
74 nop.m 0
75 shl r27=r28, 5;; //25, 00000005H
76 zxt4 r26=r27;; //25
77 }
78 { .mfb //R-Addr: 0X040
79 add r31=r26, r32 //25
80 nop.f 0
81 nop.b 0
82 }
83 $L143:
84 { .mii //R-Addr: 0X050
85 fc r32 //27
86 adds r32=32, r32;; //28, 00000020H
87 cmp.ltu p14,p15=r32, r31 //29
88 }
89 { .mfb //R-Addr: 0X060
90 nop.m 0
91 nop.f 0
92 (p14) br.cond.dptk.few $L143#;; //29, 880000/120000
93 }
94 { .mmi
95 sync.i;;
96 srlz.i
97 nop.i 0;;
98 }
99 { .mfb //R-Addr: 0X070
100 nop.m 0
101 nop.f 0
102 br.ret.sptk.few b0;; //31
103 }
104 // End code for function:
105 .endp InvalidateInstructionCacheRange#
106 // END