MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c

   1 /** @file
   2   Cache Maintenance Functions.
   3
   4   Copyright (c) 2006, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15
  16 //
  17 // Include common header file for this module.
  18 //
  19 #include <Base.h>
  20 #include <Library/CacheMaintenanceLib.h>
  21 #include <Library/BaseLib.h>
  22 #include <Library/DebugLib.h>
  23
  24 /**
  25   Invalidates the entire instruction cache in cache coherency domain of the
  26   calling CPU.
  27
  28   Invalidates the entire instruction cache in cache coherency domain of the
  29   calling CPU.
  30
  31 **/
  32 VOID
  33 EFIAPI
  34 InvalidateInstructionCache (
  35   VOID
  36   )
  37 {
  38   PalCallStatic (NULL, 1, 1, 1, 0);
  39 }
  40
  41 /**
  42   Invalidates a range of instruction cache lines in the cache coherency domain
  43   of the calling CPU.
  44
  45   Invalidates the instruction cache lines specified by Address and Length. If
  46   Address is not aligned on a cache line boundary, then entire instruction
  47   cache line containing Address is invalidated. If Address + Length is not
  48   aligned on a cache line boundary, then the entire instruction cache line
  49   containing Address + Length -1 is invalidated. This function may choose to
  50   invalidate the entire instruction cache if that is more efficient than
  51   invalidating the specified range. If Length is 0, the no instruction cache
  52   lines are invalidated. Address is returned.
  53
  54   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  55
  56   @param  Address The base address of the instruction cache lines to
  57                   invalidate. If the CPU is in a physical addressing mode, then
  58                   Address is a physical address. If the CPU is in a virtual
  59                   addressing mode, then Address is a virtual address.
  60
  61   @param  Length  The number of bytes to invalidate from the instruction cache.
  62
  63   @return Address
  64
  65 **/
  66 VOID *
  67 EFIAPI
  68 InvalidateInstructionCacheRange (
  69   IN      VOID                      *Address,
  70   IN      UINTN                     Length
  71   )
  72 {
  73   return IpfFlushCacheRange (Address, Length);
  74 }
  75
  76 /**
  77   Writes Back and Invalidates the entire data cache in cache coherency domain
  78   of the calling CPU.
  79
  80   Writes Back and Invalidates the entire data cache in cache coherency domain
  81   of the calling CPU. This function guarantees that all dirty cache lines are
  82   written back to system memory, and also invalidates all the data cache lines
  83   in the cache coherency domain of the calling CPU.
  84
  85 **/
  86 VOID
  87 EFIAPI
  88 WriteBackInvalidateDataCache (
  89   VOID
  90   )
  91 {
  92   PalCallStatic (NULL, 1, 2, 1, 0);
  93 }
  94
  95 /**
  96   Writes Back and Invalidates a range of data cache lines in the cache
  97   coherency domain of the calling CPU.
  98
  99   Writes Back and Invalidate the data cache lines specified by Address and
 100   Length. If Address is not aligned on a cache line boundary, then entire data
 101   cache line containing Address is written back and invalidated. If Address +
 102   Length is not aligned on a cache line boundary, then the entire data cache
 103   line containing Address + Length -1 is written back and invalidated. This
 104   function may choose to write back and invalidate the entire data cache if
 105   that is more efficient than writing back and invalidating the specified
 106   range. If Length is 0, the no data cache lines are written back and
 107   invalidated. Address is returned.
 108
 109   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 110
 111   @param  Address The base address of the data cache lines to write back and
 112                   invalidate. If the CPU is in a physical addressing mode, then
 113                   Address is a physical address. If the CPU is in a virtual
 114                   addressing mode, then Address is a virtual address.
 115   @param  Length  The number of bytes to write back and invalidate from the
 116                   data cache.
 117
 118   @return Address
 119
 120 **/
 121 VOID *
 122 EFIAPI
 123 WriteBackInvalidateDataCacheRange (
 124   IN      VOID                      *Address,
 125   IN      UINTN                     Length
 126   )
 127 {
 128   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 129
 130   return IpfFlushCacheRange (Address, Length);
 131 }
 132
 133 /**
 134   Writes Back the entire data cache in cache coherency domain of the calling
 135   CPU.
 136
 137   Writes Back the entire data cache in cache coherency domain of the calling
 138   CPU. This function guarantees that all dirty cache lines are written back to
 139   system memory. This function may also invalidate all the data cache lines in
 140   the cache coherency domain of the calling CPU.
 141
 142 **/
 143 VOID
 144 EFIAPI
 145 WriteBackDataCache (
 146   VOID
 147   )
 148 {
 149   PalCallStatic (NULL, 1, 2, 0, 0);
 150 }
 151
 152 /**
 153   Writes Back a range of data cache lines in the cache coherency domain of the
 154   calling CPU.
 155
 156   Writes Back the data cache lines specified by Address and Length. If Address
 157   is not aligned on a cache line boundary, then entire data cache line
 158   containing Address is written back. If Address + Length is not aligned on a
 159   cache line boundary, then the entire data cache line containing Address +
 160   Length -1 is written back. This function may choose to write back the entire
 161   data cache if that is more efficient than writing back the specified range.
 162   If Length is 0, the no data cache lines are written back. This function may
 163   also invalidate all the data cache lines in the specified range of the cache
 164   coherency domain of the calling CPU. Address is returned.
 165
 166   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 167
 168   @param  Address The base address of the data cache lines to write back. If
 169                   the CPU is in a physical addressing mode, then Address is a
 170                   physical address. If the CPU is in a virtual addressing
 171                   mode, then Address is a virtual address.
 172   @param  Length  The number of bytes to write back from the data cache.
 173
 174   @return Address
 175
 176 **/
 177 VOID *
 178 EFIAPI
 179 WriteBackDataCacheRange (
 180   IN      VOID                      *Address,
 181   IN      UINTN                     Length
 182   )
 183 {
 184   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 185
 186   return IpfFlushCacheRange (Address, Length);
 187 }
 188
 189 /**
 190   Invalidates the entire data cache in cache coherency domain of the calling
 191   CPU.
 192
 193   Invalidates the entire data cache in cache coherency domain of the calling
 194   CPU. This function must be used with care because dirty cache lines are not
 195   written back to system memory. It is typically used for cache diagnostics. If
 196   the CPU does not support invalidation of the entire data cache, then a write
 197   back and invalidate operation should be performed on the entire data cache.
 198
 199 **/
 200 VOID
 201 EFIAPI
 202 InvalidateDataCache (
 203   VOID
 204   )
 205 {
 206   WriteBackInvalidateDataCache ();
 207 }
 208
 209 /**
 210   Invalidates a range of data cache lines in the cache coherency domain of the
 211   calling CPU.
 212
 213   Invalidates the data cache lines specified by Address and Length. If Address
 214   is not aligned on a cache line boundary, then entire data cache line
 215   containing Address is invalidated. If Address + Length is not aligned on a
 216   cache line boundary, then the entire data cache line containing Address +
 217   Length -1 is invalidated. This function must never invalidate any cache lines
 218   outside the specified range. If Length is 0, the no data cache lines are
 219   invalidated. Address is returned. This function must be used with care
 220   because dirty cache lines are not written back to system memory. It is
 221   typically used for cache diagnostics. If the CPU does not support
 222   invalidation of a data cache range, then a write back and invalidate
 223   operation should be performed on the data cache range.
 224
 225   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 226
 227   @param  Address The base address of the data cache lines to invalidate. If
 228                   the CPU is in a physical addressing mode, then Address is a
 229                   physical address. If the CPU is in a virtual addressing mode,
 230                   then Address is a virtual address.
 231   @param  Length  The number of bytes to invalidate from the data cache.
 232
 233   @return Address
 234
 235 **/
 236 VOID *
 237 EFIAPI
 238 InvalidateDataCacheRange (
 239   IN      VOID                      *Address,
 240   IN      UINTN                     Length
 241   )
 242 {
 243   return IpfFlushCacheRange (Address, Length);
 244 }