7e96d9b76a5d5559e66a8a57dd7d2d41259c8f21
[mirror_edk2.git] / MdePkg / Library / BaseCacheMaintenanceLib / IpfCache.c
1 /** @file
2 Cache Maintenance Functions.
3
4 Copyright (c) 2006, Intel Corporation<BR>
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 typedef struct {
16 UINT64 Status;
17 UINT64 r9;
18 UINT64 r10;
19 UINT64 r11;
20 } PAL_PROC_RETURN;
21
22 PAL_PROC_RETURN
23 PalCallStatic (
24 IN CONST VOID *PalEntryPoint,
25 IN UINT64 Arg1,
26 IN UINT64 Arg2,
27 IN UINT64 Arg3,
28 IN UINT64 Arg4
29 );
30
31 /**
32 Invalidates the entire instruction cache in cache coherency domain of the
33 calling CPU.
34
35 Invalidates the entire instruction cache in cache coherency domain of the
36 calling CPU.
37
38 **/
39 VOID
40 EFIAPI
41 InvalidateInstructionCache (
42 VOID
43 )
44 {
45 PalCallStatic (NULL, 1, 1, 1, 0);
46 }
47
48 /**
49 Writes Back and Invalidates the entire data cache in cache coherency domain
50 of the calling CPU.
51
52 Writes Back and Invalidates the entire data cache in cache coherency domain
53 of the calling CPU. This function guarantees that all dirty cache lines are
54 written back to system memory, and also invalidates all the data cache lines
55 in the cache coherency domain of the calling CPU.
56
57 **/
58 VOID
59 EFIAPI
60 WriteBackInvalidateDataCache (
61 VOID
62 )
63 {
64 PalCallStatic (NULL, 1, 2, 1, 0);
65 }
66
67 /**
68 Writes Back and Invalidates a range of data cache lines in the cache
69 coherency domain of the calling CPU.
70
71 Writes Back and Invalidate the data cache lines specified by Address and
72 Length. If Address is not aligned on a cache line boundary, then entire data
73 cache line containing Address is written back and invalidated. If Address +
74 Length is not aligned on a cache line boundary, then the entire data cache
75 line containing Address + Length -1 is written back and invalidated. This
76 function may choose to write back and invalidate the entire data cache if
77 that is more efficient than writing back and invalidating the specified
78 range. If Length is 0, the no data cache lines are written back and
79 invalidated. Address is returned.
80
81 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
82
83 @param Address The base address of the data cache lines to write back and
84 invalidate. If the CPU is in a physical addressing mode, then
85 Address is a physical address. If the CPU is in a virtual
86 addressing mode, then Address is a virtual address.
87 @param Length The number of bytes to write back and invalidate from the
88 data cache.
89
90 @return Address
91
92 **/
93 VOID *
94 EFIAPI
95 WriteBackInvalidateDataCacheRange (
96 IN VOID *Address,
97 IN UINTN Length
98 )
99 {
100 ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
101
102 if (Length > 0) {
103 WriteBackInvalidateDataCache ();
104 }
105 return Address;
106 }
107
108 /**
109 Writes Back the entire data cache in cache coherency domain of the calling
110 CPU.
111
112 Writes Back the entire data cache in cache coherency domain of the calling
113 CPU. This function guarantees that all dirty cache lines are written back to
114 system memory. This function may also invalidate all the data cache lines in
115 the cache coherency domain of the calling CPU.
116
117 **/
118 VOID
119 EFIAPI
120 WriteBackDataCache (
121 VOID
122 )
123 {
124 PalCallStatic (NULL, 1, 2, 0, 0);
125 }
126
127 /**
128 Writes Back a range of data cache lines in the cache coherency domain of the
129 calling CPU.
130
131 Writes Back the data cache lines specified by Address and Length. If Address
132 is not aligned on a cache line boundary, then entire data cache line
133 containing Address is written back. If Address + Length is not aligned on a
134 cache line boundary, then the entire data cache line containing Address +
135 Length -1 is written back. This function may choose to write back the entire
136 data cache if that is more efficient than writing back the specified range.
137 If Length is 0, the no data cache lines are written back. This function may
138 also invalidate all the data cache lines in the specified range of the cache
139 coherency domain of the calling CPU. Address is returned.
140
141 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
142
143 @param Address The base address of the data cache lines to write back. If
144 the CPU is in a physical addressing mode, then Address is a
145 physical address. If the CPU is in a virtual addressing
146 mode, then Address is a virtual address.
147 @param Length The number of bytes to write back from the data cache.
148
149 @return Address
150
151 **/
152 VOID *
153 EFIAPI
154 WriteBackDataCacheRange (
155 IN VOID *Address,
156 IN UINTN Length
157 )
158 {
159 ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
160
161 if (Length > 0) {
162 WriteBackDataCache ();
163 }
164 return Address;
165 }
166
167 /**
168 Invalidates the entire data cache in cache coherency domain of the calling
169 CPU.
170
171 Invalidates the entire data cache in cache coherency domain of the calling
172 CPU. This function must be used with care because dirty cache lines are not
173 written back to system memory. It is typically used for cache diagnostics. If
174 the CPU does not support invalidation of the entire data cache, then a write
175 back and invalidate operation should be performed on the entire data cache.
176
177 **/
178 VOID
179 EFIAPI
180 InvalidateDataCache (
181 VOID
182 )
183 {
184 WriteBackInvalidateDataCache ();
185 }
186
187 /**
188 Invalidates a range of data cache lines in the cache coherency domain of the
189 calling CPU.
190
191 Invalidates the data cache lines specified by Address and Length. If Address
192 is not aligned on a cache line boundary, then entire data cache line
193 containing Address is invalidated. If Address + Length is not aligned on a
194 cache line boundary, then the entire data cache line containing Address +
195 Length -1 is invalidated. This function must never invalidate any cache lines
196 outside the specified range. If Length is 0, the no data cache lines are
197 invalidated. Address is returned. This function must be used with care
198 because dirty cache lines are not written back to system memory. It is
199 typically used for cache diagnostics. If the CPU does not support
200 invalidation of a data cache range, then a write back and invalidate
201 operation should be performed on the data cache range.
202
203 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
204
205 @param Address The base address of the data cache lines to invalidate. If
206 the CPU is in a physical addressing mode, then Address is a
207 physical address. If the CPU is in a virtual addressing mode,
208 then Address is a virtual address.
209 @param Length The number of bytes to invalidate from the data cache.
210
211 @return Address
212
213 **/
214 VOID *
215 EFIAPI
216 InvalidateDataCacheRange (
217 IN VOID *Address,
218 IN UINTN Length
219 )
220 {
221 return WriteBackInvalidateDataCacheRange (Address, Length);
222 }