BaseCacheMaintenanceLib has now been completed on all architectures.
[mirror_edk2.git] / MdePkg / Library / BaseCacheMaintenanceLib / IpfCache.c
1 /** @file
2 Cache Maintenance Functions.
3
4 Copyright (c) 2006, Intel Corporation<BR>
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 typedef struct {
16 UINT64 Status;
17 UINT64 r9;
18 UINT64 r10;
19 UINT64 r11;
20 } PAL_PROC_RETURN;
21
22 PAL_PROC_RETURN
23 CallPalProcStatic (
24 IN UINT64 Arg1,
25 IN UINT64 Arg2,
26 IN UINT64 Arg3,
27 IN UINT64 Arg4
28 );
29
30 /**
31 Invalidates the entire instruction cache in cache coherency domain of the
32 calling CPU.
33
34 Invalidates the entire instruction cache in cache coherency domain of the
35 calling CPU.
36
37 **/
38 VOID
39 EFIAPI
40 InvalidateInstructionCache (
41 VOID
42 )
43 {
44 CallPalProcStatic (1, 1, 1, 0);
45 }
46
47 /**
48 Invalidates a range of instruction cache lines in the cache coherency domain
49 of the calling CPU.
50
51 Invalidates the instruction cache lines specified by Address and Length. If
52 Address is not aligned on a cache line boundary, then entire instruction
53 cache line containing Address is invalidated. If Address + Length is not
54 aligned on a cache line boundary, then the entire instruction cache line
55 containing Address + Length -1 is invalidated. This function may choose to
56 invalidate the entire instruction cache if that is more efficient than
57 invalidating the specified range. If Length is 0, the no instruction cache
58 lines are invalidated. Address is returned.
59
60 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
61
62 @param Address The base address of the instruction cache lines to
63 invalidate. If the CPU is in a physical addressing mode, then
64 Address is a physical address. If the CPU is in a virtual
65 addressing mode, then Address is a virtual address.
66
67 @param Length The number of bytes to invalidate from the instruction cache.
68
69 @return Address
70
71 **/
72 VOID*
73 EFIAPI
74 InvalidateInstructionCacheRange (
75 IN VOID *Address,
76 IN UINTN Length
77 )
78 {
79 ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
80
81 if (Length > 0) {
82 InvalidateInstructionCache ();
83 }
84 return Address;
85 }
86
87 /**
88 Writes Back and Invalidates the entire data cache in cache coherency domain
89 of the calling CPU.
90
91 Writes Back and Invalidates the entire data cache in cache coherency domain
92 of the calling CPU. This function guarantees that all dirty cache lines are
93 written back to system memory, and also invalidates all the data cache lines
94 in the cache coherency domain of the calling CPU.
95
96 **/
97 VOID
98 EFIAPI
99 WriteBackInvalidateDataCache (
100 VOID
101 )
102 {
103 CallPalProcStatic (1, 2, 1, 0);
104 }
105
106 /**
107 Writes Back and Invalidates a range of data cache lines in the cache
108 coherency domain of the calling CPU.
109
110 Writes Back and Invalidate the data cache lines specified by Address and
111 Length. If Address is not aligned on a cache line boundary, then entire data
112 cache line containing Address is written back and invalidated. If Address +
113 Length is not aligned on a cache line boundary, then the entire data cache
114 line containing Address + Length -1 is written back and invalidated. This
115 function may choose to write back and invalidate the entire data cache if
116 that is more efficient than writing back and invalidating the specified
117 range. If Length is 0, the no data cache lines are written back and
118 invalidated. Address is returned.
119
120 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
121
122 @param Address The base address of the data cache lines to write back and
123 invalidate. If the CPU is in a physical addressing mode, then
124 Address is a physical address. If the CPU is in a virtual
125 addressing mode, then Address is a virtual address.
126 @param Length The number of bytes to write back and invalidate from the
127 data cache.
128
129 @return Address
130
131 **/
132 VOID *
133 EFIAPI
134 WriteBackInvalidateDataCacheRange (
135 IN VOID *Address,
136 IN UINTN Length
137 )
138 {
139 ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
140
141 if (Length > 0) {
142 WriteBackInvalidateDataCache ();
143 }
144 return Address;
145 }
146
147 /**
148 Writes Back the entire data cache in cache coherency domain of the calling
149 CPU.
150
151 Writes Back the entire data cache in cache coherency domain of the calling
152 CPU. This function guarantees that all dirty cache lines are written back to
153 system memory. This function may also invalidate all the data cache lines in
154 the cache coherency domain of the calling CPU.
155
156 **/
157 VOID
158 EFIAPI
159 WriteBackDataCache (
160 VOID
161 )
162 {
163 CallPalProcStatic (1, 2, 0, 0);
164 }
165
166 /**
167 Writes Back a range of data cache lines in the cache coherency domain of the
168 calling CPU.
169
170 Writes Back the data cache lines specified by Address and Length. If Address
171 is not aligned on a cache line boundary, then entire data cache line
172 containing Address is written back. If Address + Length is not aligned on a
173 cache line boundary, then the entire data cache line containing Address +
174 Length -1 is written back. This function may choose to write back the entire
175 data cache if that is more efficient than writing back the specified range.
176 If Length is 0, the no data cache lines are written back. This function may
177 also invalidate all the data cache lines in the specified range of the cache
178 coherency domain of the calling CPU. Address is returned.
179
180 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
181
182 @param Address The base address of the data cache lines to write back. If
183 the CPU is in a physical addressing mode, then Address is a
184 physical address. If the CPU is in a virtual addressing
185 mode, then Address is a virtual address.
186 @param Length The number of bytes to write back from the data cache.
187
188 @return Address
189
190 **/
191 VOID *
192 EFIAPI
193 WriteBackDataCacheRange (
194 IN VOID *Address,
195 IN UINTN Length
196 )
197 {
198 ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
199
200 if (Length > 0) {
201 WriteBackDataCache ();
202 }
203 return Address;
204 }
205
206 /**
207 Invalidates the entire data cache in cache coherency domain of the calling
208 CPU.
209
210 Invalidates the entire data cache in cache coherency domain of the calling
211 CPU. This function must be used with care because dirty cache lines are not
212 written back to system memory. It is typically used for cache diagnostics. If
213 the CPU does not support invalidation of the entire data cache, then a write
214 back and invalidate operation should be performed on the entire data cache.
215
216 **/
217 VOID
218 EFIAPI
219 InvalidateDataCache (
220 VOID
221 )
222 {
223 WriteBackInvalidateDataCache ();
224 }
225
226 /**
227 Invalidates a range of data cache lines in the cache coherency domain of the
228 calling CPU.
229
230 Invalidates the data cache lines specified by Address and Length. If Address
231 is not aligned on a cache line boundary, then entire data cache line
232 containing Address is invalidated. If Address + Length is not aligned on a
233 cache line boundary, then the entire data cache line containing Address +
234 Length -1 is invalidated. This function must never invalidate any cache lines
235 outside the specified range. If Length is 0, the no data cache lines are
236 invalidated. Address is returned. This function must be used with care
237 because dirty cache lines are not written back to system memory. It is
238 typically used for cache diagnostics. If the CPU does not support
239 invalidation of a data cache range, then a write back and invalidate
240 operation should be performed on the data cache range.
241
242 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
243
244 @param Address The base address of the data cache lines to invalidate. If
245 the CPU is in a physical addressing mode, then Address is a
246 physical address. If the CPU is in a virtual addressing mode,
247 then Address is a virtual address.
248 @param Length The number of bytes to invalidate from the data cache.
249
250 @return Address
251
252 **/
253 VOID *
254 EFIAPI
255 InvalidateDataCacheRange (
256 IN VOID *Address,
257 IN UINTN Length
258 )
259 {
260 return WriteBackInvalidateDataCacheRange (Address, Length);
261 }