MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c

   1 /** @file
   2   Cache Maintenance Functions.
   3
   4   Copyright (c) 2006, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15
  16 //
  17 // Include common header file for this module.
  18 //
  19 #include "CommonHeader.h"
  20
  21 /**
  22   Invalidates the entire instruction cache in cache coherency domain of the
  23   calling CPU.
  24
  25   Invalidates the entire instruction cache in cache coherency domain of the
  26   calling CPU.
  27
  28 **/
  29 VOID
  30 EFIAPI
  31 InvalidateInstructionCache (
  32   VOID
  33   )
  34 {
  35   PalCallStatic (NULL, 1, 1, 1, 0);
  36 }
  37
  38 /**
  39   Invalidates a range of instruction cache lines in the cache coherency domain
  40   of the calling CPU.
  41
  42   Invalidates the instruction cache lines specified by Address and Length. If
  43   Address is not aligned on a cache line boundary, then entire instruction
  44   cache line containing Address is invalidated. If Address + Length is not
  45   aligned on a cache line boundary, then the entire instruction cache line
  46   containing Address + Length -1 is invalidated. This function may choose to
  47   invalidate the entire instruction cache if that is more efficient than
  48   invalidating the specified range. If Length is 0, the no instruction cache
  49   lines are invalidated. Address is returned.
  50
  51   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  52
  53   @param  Address The base address of the instruction cache lines to
  54                   invalidate. If the CPU is in a physical addressing mode, then
  55                   Address is a physical address. If the CPU is in a virtual
  56                   addressing mode, then Address is a virtual address.
  57
  58   @param  Length  The number of bytes to invalidate from the instruction cache.
  59
  60   @return Address
  61
  62 **/
  63 VOID *
  64 EFIAPI
  65 InvalidateInstructionCacheRange (
  66   IN      VOID                      *Address,
  67   IN      UINTN                     Length
  68   )
  69 {
  70   return IpfFlushCacheRange (Address, Length);
  71 }
  72
  73 /**
  74   Writes Back and Invalidates the entire data cache in cache coherency domain
  75   of the calling CPU.
  76
  77   Writes Back and Invalidates the entire data cache in cache coherency domain
  78   of the calling CPU. This function guarantees that all dirty cache lines are
  79   written back to system memory, and also invalidates all the data cache lines
  80   in the cache coherency domain of the calling CPU.
  81
  82 **/
  83 VOID
  84 EFIAPI
  85 WriteBackInvalidateDataCache (
  86   VOID
  87   )
  88 {
  89   PalCallStatic (NULL, 1, 2, 1, 0);
  90 }
  91
  92 /**
  93   Writes Back and Invalidates a range of data cache lines in the cache
  94   coherency domain of the calling CPU.
  95
  96   Writes Back and Invalidate the data cache lines specified by Address and
  97   Length. If Address is not aligned on a cache line boundary, then entire data
  98   cache line containing Address is written back and invalidated. If Address +
  99   Length is not aligned on a cache line boundary, then the entire data cache
 100   line containing Address + Length -1 is written back and invalidated. This
 101   function may choose to write back and invalidate the entire data cache if
 102   that is more efficient than writing back and invalidating the specified
 103   range. If Length is 0, the no data cache lines are written back and
 104   invalidated. Address is returned.
 105
 106   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 107
 108   @param  Address The base address of the data cache lines to write back and
 109                   invalidate. If the CPU is in a physical addressing mode, then
 110                   Address is a physical address. If the CPU is in a virtual
 111                   addressing mode, then Address is a virtual address.
 112   @param  Length  The number of bytes to write back and invalidate from the
 113                   data cache.
 114
 115   @return Address
 116
 117 **/
 118 VOID *
 119 EFIAPI
 120 WriteBackInvalidateDataCacheRange (
 121   IN      VOID                      *Address,
 122   IN      UINTN                     Length
 123   )
 124 {
 125   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 126
 127   return IpfFlushCacheRange (Address, Length);
 128 }
 129
 130 /**
 131   Writes Back the entire data cache in cache coherency domain of the calling
 132   CPU.
 133
 134   Writes Back the entire data cache in cache coherency domain of the calling
 135   CPU. This function guarantees that all dirty cache lines are written back to
 136   system memory. This function may also invalidate all the data cache lines in
 137   the cache coherency domain of the calling CPU.
 138
 139 **/
 140 VOID
 141 EFIAPI
 142 WriteBackDataCache (
 143   VOID
 144   )
 145 {
 146   PalCallStatic (NULL, 1, 2, 0, 0);
 147 }
 148
 149 /**
 150   Writes Back a range of data cache lines in the cache coherency domain of the
 151   calling CPU.
 152
 153   Writes Back the data cache lines specified by Address and Length. If Address
 154   is not aligned on a cache line boundary, then entire data cache line
 155   containing Address is written back. If Address + Length is not aligned on a
 156   cache line boundary, then the entire data cache line containing Address +
 157   Length -1 is written back. This function may choose to write back the entire
 158   data cache if that is more efficient than writing back the specified range.
 159   If Length is 0, the no data cache lines are written back. This function may
 160   also invalidate all the data cache lines in the specified range of the cache
 161   coherency domain of the calling CPU. Address is returned.
 162
 163   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 164
 165   @param  Address The base address of the data cache lines to write back. If
 166                   the CPU is in a physical addressing mode, then Address is a
 167                   physical address. If the CPU is in a virtual addressing
 168                   mode, then Address is a virtual address.
 169   @param  Length  The number of bytes to write back from the data cache.
 170
 171   @return Address
 172
 173 **/
 174 VOID *
 175 EFIAPI
 176 WriteBackDataCacheRange (
 177   IN      VOID                      *Address,
 178   IN      UINTN                     Length
 179   )
 180 {
 181   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 182
 183   return IpfFlushCacheRange (Address, Length);
 184 }
 185
 186 /**
 187   Invalidates the entire data cache in cache coherency domain of the calling
 188   CPU.
 189
 190   Invalidates the entire data cache in cache coherency domain of the calling
 191   CPU. This function must be used with care because dirty cache lines are not
 192   written back to system memory. It is typically used for cache diagnostics. If
 193   the CPU does not support invalidation of the entire data cache, then a write
 194   back and invalidate operation should be performed on the entire data cache.
 195
 196 **/
 197 VOID
 198 EFIAPI
 199 InvalidateDataCache (
 200   VOID
 201   )
 202 {
 203   WriteBackInvalidateDataCache ();
 204 }
 205
 206 /**
 207   Invalidates a range of data cache lines in the cache coherency domain of the
 208   calling CPU.
 209
 210   Invalidates the data cache lines specified by Address and Length. If Address
 211   is not aligned on a cache line boundary, then entire data cache line
 212   containing Address is invalidated. If Address + Length is not aligned on a
 213   cache line boundary, then the entire data cache line containing Address +
 214   Length -1 is invalidated. This function must never invalidate any cache lines
 215   outside the specified range. If Length is 0, the no data cache lines are
 216   invalidated. Address is returned. This function must be used with care
 217   because dirty cache lines are not written back to system memory. It is
 218   typically used for cache diagnostics. If the CPU does not support
 219   invalidation of a data cache range, then a write back and invalidate
 220   operation should be performed on the data cache range.
 221
 222   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 223
 224   @param  Address The base address of the data cache lines to invalidate. If
 225                   the CPU is in a physical addressing mode, then Address is a
 226                   physical address. If the CPU is in a virtual addressing mode,
 227                   then Address is a virtual address.
 228   @param  Length  The number of bytes to invalidate from the data cache.
 229
 230   @return Address
 231
 232 **/
 233 VOID *
 234 EFIAPI
 235 InvalidateDataCacheRange (
 236   IN      VOID                      *Address,
 237   IN      UINTN                     Length
 238   )
 239 {
 240   return IpfFlushCacheRange (Address, Length);
 241 }