MdePkg/Library/BaseCacheMaintenanceLib/X86Cache.c

   1 /** @file
   2   Cache Maintenance Functions.
   3
   4   Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8 **/
   9
  10 #include <Base.h>
  11 #include <Library/BaseLib.h>
  12 #include <Library/DebugLib.h>
  13
  14 /**
  15   Invalidates the entire instruction cache in cache coherency domain of the
  16   calling CPU.
  17
  18 **/
  19 VOID
  20 EFIAPI
  21 InvalidateInstructionCache (
  22   VOID
  23   )
  24 {
  25 }
  26
  27 /**
  28   Invalidates a range of instruction cache lines in the cache coherency domain
  29   of the calling CPU.
  30
  31   Invalidates the instruction cache lines specified by Address and Length. If
  32   Address is not aligned on a cache line boundary, then entire instruction
  33   cache line containing Address is invalidated. If Address + Length is not
  34   aligned on a cache line boundary, then the entire instruction cache line
  35   containing Address + Length -1 is invalidated. This function may choose to
  36   invalidate the entire instruction cache if that is more efficient than
  37   invalidating the specified range. If Length is 0, then no instruction cache
  38   lines are invalidated. Address is returned.
  39
  40   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  41
  42   @param  Address The base address of the instruction cache lines to
  43                   invalidate. If the CPU is in a physical addressing mode, then
  44                   Address is a physical address. If the CPU is in a virtual
  45                   addressing mode, then Address is a virtual address.
  46
  47   @param  Length  The number of bytes to invalidate from the instruction cache.
  48
  49   @return Address.
  50
  51 **/
  52 VOID *
  53 EFIAPI
  54 InvalidateInstructionCacheRange (
  55   IN      VOID                      *Address,
  56   IN      UINTN                     Length
  57   )
  58 {
  59   if (Length == 0) {
  60     return Address;
  61   }
  62
  63   ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
  64   return Address;
  65 }
  66
  67 /**
  68   Writes back and invalidates the entire data cache in cache coherency domain
  69   of the calling CPU.
  70
  71   Writes back and invalidates the entire data cache in cache coherency domain
  72   of the calling CPU. This function guarantees that all dirty cache lines are
  73   written back to system memory, and also invalidates all the data cache lines
  74   in the cache coherency domain of the calling CPU.
  75
  76 **/
  77 VOID
  78 EFIAPI
  79 WriteBackInvalidateDataCache (
  80   VOID
  81   )
  82 {
  83   AsmWbinvd ();
  84 }
  85
  86 /**
  87   Writes back and invalidates a range of data cache lines in the cache
  88   coherency domain of the calling CPU.
  89
  90   Writes back and invalidates the data cache lines specified by Address and
  91   Length. If Address is not aligned on a cache line boundary, then entire data
  92   cache line containing Address is written back and invalidated. If Address +
  93   Length is not aligned on a cache line boundary, then the entire data cache
  94   line containing Address + Length -1 is written back and invalidated. This
  95   function may choose to write back and invalidate the entire data cache if
  96   that is more efficient than writing back and invalidating the specified
  97   range. If Length is 0, then no data cache lines are written back and
  98   invalidated. Address is returned.
  99
 100   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 101
 102   @param  Address The base address of the data cache lines to write back and
 103                   invalidate. If the CPU is in a physical addressing mode, then
 104                   Address is a physical address. If the CPU is in a virtual
 105                   addressing mode, then Address is a virtual address.
 106   @param  Length  The number of bytes to write back and invalidate from the
 107                   data cache.
 108
 109   @return Address of cache invalidation.
 110
 111 **/
 112 VOID *
 113 EFIAPI
 114 WriteBackInvalidateDataCacheRange (
 115   IN      VOID                      *Address,
 116   IN      UINTN                     Length
 117   )
 118 {
 119   UINT32                            RegEbx;
 120   UINT32                            RegEdx;
 121   UINTN                             CacheLineSize;
 122   UINTN                             Start;
 123   UINTN                             End;
 124
 125   if (Length == 0) {
 126     return Address;
 127   }
 128
 129   ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
 130
 131   //
 132   // If the CPU does not support CLFLUSH instruction,
 133   // then promote flush range to flush entire cache.
 134   //
 135   AsmCpuid (0x01, NULL, &RegEbx, NULL, &RegEdx);
 136   if ((RegEdx & BIT19) == 0) {
 137     AsmWbinvd ();
 138     return Address;
 139   }
 140
 141   //
 142   // Cache line size is 8 * Bits 15-08 of EBX returned from CPUID 01H
 143   //
 144   CacheLineSize = (RegEbx & 0xff00) >> 5;
 145
 146   Start = (UINTN)Address;
 147   //
 148   // Calculate the cache line alignment
 149   //
 150   End = (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1);
 151   Start &= ~((UINTN)CacheLineSize - 1);
 152
 153   do {
 154     Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CacheLineSize;
 155   } while (Start != End);
 156   return Address;
 157 }
 158
 159 /**
 160   Writes back the entire data cache in cache coherency domain of the calling
 161   CPU.
 162
 163   Writes back the entire data cache in cache coherency domain of the calling
 164   CPU. This function guarantees that all dirty cache lines are written back to
 165   system memory. This function may also invalidate all the data cache lines in
 166   the cache coherency domain of the calling CPU.
 167
 168 **/
 169 VOID
 170 EFIAPI
 171 WriteBackDataCache (
 172   VOID
 173   )
 174 {
 175   WriteBackInvalidateDataCache ();
 176 }
 177
 178 /**
 179   Writes back a range of data cache lines in the cache coherency domain of the
 180   calling CPU.
 181
 182   Writes back the data cache lines specified by Address and Length. If Address
 183   is not aligned on a cache line boundary, then entire data cache line
 184   containing Address is written back. If Address + Length is not aligned on a
 185   cache line boundary, then the entire data cache line containing Address +
 186   Length -1 is written back. This function may choose to write back the entire
 187   data cache if that is more efficient than writing back the specified range.
 188   If Length is 0, then no data cache lines are written back. This function may
 189   also invalidate all the data cache lines in the specified range of the cache
 190   coherency domain of the calling CPU. Address is returned.
 191
 192   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 193
 194   @param  Address The base address of the data cache lines to write back. If
 195                   the CPU is in a physical addressing mode, then Address is a
 196                   physical address. If the CPU is in a virtual addressing
 197                   mode, then Address is a virtual address.
 198   @param  Length  The number of bytes to write back from the data cache.
 199
 200   @return Address of cache written in main memory.
 201
 202 **/
 203 VOID *
 204 EFIAPI
 205 WriteBackDataCacheRange (
 206   IN      VOID                      *Address,
 207   IN      UINTN                     Length
 208   )
 209 {
 210   return WriteBackInvalidateDataCacheRange (Address, Length);
 211 }
 212
 213 /**
 214   Invalidates the entire data cache in cache coherency domain of the calling
 215   CPU.
 216
 217   Invalidates the entire data cache in cache coherency domain of the calling
 218   CPU. This function must be used with care because dirty cache lines are not
 219   written back to system memory. It is typically used for cache diagnostics. If
 220   the CPU does not support invalidation of the entire data cache, then a write
 221   back and invalidate operation should be performed on the entire data cache.
 222
 223 **/
 224 VOID
 225 EFIAPI
 226 InvalidateDataCache (
 227   VOID
 228   )
 229 {
 230   AsmInvd ();
 231 }
 232
 233 /**
 234   Invalidates a range of data cache lines in the cache coherency domain of the
 235   calling CPU.
 236
 237   Invalidates the data cache lines specified by Address and Length. If Address
 238   is not aligned on a cache line boundary, then entire data cache line
 239   containing Address is invalidated. If Address + Length is not aligned on a
 240   cache line boundary, then the entire data cache line containing Address +
 241   Length -1 is invalidated. This function must never invalidate any cache lines
 242   outside the specified range. If Length is 0, then no data cache lines are
 243   invalidated. Address is returned. This function must be used with care
 244   because dirty cache lines are not written back to system memory. It is
 245   typically used for cache diagnostics. If the CPU does not support
 246   invalidation of a data cache range, then a write back and invalidate
 247   operation should be performed on the data cache range.
 248
 249   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 250
 251   @param  Address The base address of the data cache lines to invalidate. If
 252                   the CPU is in a physical addressing mode, then Address is a
 253                   physical address. If the CPU is in a virtual addressing mode,
 254                   then Address is a virtual address.
 255   @param  Length  The number of bytes to invalidate from the data cache.
 256
 257   @return Address.
 258
 259 **/
 260 VOID *
 261 EFIAPI
 262 InvalidateDataCacheRange (
 263   IN      VOID                      *Address,
 264   IN      UINTN                     Length
 265   )
 266 {
 267   //
 268   // Invalidation of a data cache range without writing back is not supported on
 269   // x86 architecture, so write back and invalidate operation is performed.
 270   //
 271   return WriteBackInvalidateDataCacheRange (Address, Length);
 272 }