MdePkg/Library/BaseCacheMaintenanceLib/X86Cache.c

   1 /** @file
   2   Cache Maintenance Functions.
   3
   4   Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14 **/
  15
  16 #include <Base.h>
  17 #include <Library/BaseLib.h>
  18 #include <Library/DebugLib.h>
  19
  20 //
  21 // This size must be at or below the smallest cache size possible among all
  22 // supported processors
  23 //
  24 #define CACHE_LINE_SIZE             0x20
  25
  26 /**
  27   Invalidates the entire instruction cache in cache coherency domain of the
  28   calling CPU.
  29
  30 **/
  31 VOID
  32 EFIAPI
  33 InvalidateInstructionCache (
  34   VOID
  35   )
  36 {
  37 }
  38
  39 /**
  40   Invalidates a range of instruction cache lines in the cache coherency domain
  41   of the calling CPU.
  42
  43   Invalidates the instruction cache lines specified by Address and Length. If
  44   Address is not aligned on a cache line boundary, then entire instruction
  45   cache line containing Address is invalidated. If Address + Length is not
  46   aligned on a cache line boundary, then the entire instruction cache line
  47   containing Address + Length -1 is invalidated. This function may choose to
  48   invalidate the entire instruction cache if that is more efficient than
  49   invalidating the specified range. If Length is 0, the no instruction cache
  50   lines are invalidated. Address is returned.
  51
  52   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  53
  54   @param  Address The base address of the instruction cache lines to
  55                   invalidate. If the CPU is in a physical addressing mode, then
  56                   Address is a physical address. If the CPU is in a virtual
  57                   addressing mode, then Address is a virtual address.
  58
  59   @param  Length  The number of bytes to invalidate from the instruction cache.
  60
  61   @return Address.
  62
  63 **/
  64 VOID *
  65 EFIAPI
  66 InvalidateInstructionCacheRange (
  67   IN      VOID                      *Address,
  68   IN      UINTN                     Length
  69   )
  70 {
  71   if (Length == 0) {
  72     return Address;
  73   }
  74
  75   ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
  76   return Address;
  77 }
  78
  79 /**
  80   Writes Back and Invalidates the entire data cache in cache coherency domain
  81   of the calling CPU.
  82
  83   Writes Back and Invalidates the entire data cache in cache coherency domain
  84   of the calling CPU. This function guarantees that all dirty cache lines are
  85   written back to system memory, and also invalidates all the data cache lines
  86   in the cache coherency domain of the calling CPU.
  87
  88 **/
  89 VOID
  90 EFIAPI
  91 WriteBackInvalidateDataCache (
  92   VOID
  93   )
  94 {
  95   AsmWbinvd ();
  96 }
  97
  98 /**
  99   Writes Back and Invalidates a range of data cache lines in the cache
 100   coherency domain of the calling CPU.
 101
 102   Writes Back and Invalidate the data cache lines specified by Address and
 103   Length. If Address is not aligned on a cache line boundary, then entire data
 104   cache line containing Address is written back and invalidated. If Address +
 105   Length is not aligned on a cache line boundary, then the entire data cache
 106   line containing Address + Length -1 is written back and invalidated. This
 107   function may choose to write back and invalidate the entire data cache if
 108   that is more efficient than writing back and invalidating the specified
 109   range. If Length is 0, the no data cache lines are written back and
 110   invalidated. Address is returned.
 111
 112   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 113
 114   @param  Address The base address of the data cache lines to write back and
 115                   invalidate. If the CPU is in a physical addressing mode, then
 116                   Address is a physical address. If the CPU is in a virtual
 117                   addressing mode, then Address is a virtual address.
 118   @param  Length  The number of bytes to write back and invalidate from the
 119                   data cache.
 120
 121   @return Address of cache invalidation.
 122
 123 **/
 124 VOID *
 125 EFIAPI
 126 WriteBackInvalidateDataCacheRange (
 127   IN      VOID                      *Address,
 128   IN      UINTN                     Length
 129   )
 130 {
 131   UINTN                             Start;
 132   UINTN                             End;
 133
 134   if (Length == 0) {
 135     return Address;
 136   }
 137
 138   ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
 139
 140   Start = (UINTN)Address;
 141   //
 142   // Calculate the cache line alignment
 143   //
 144   End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);
 145   Start &= ~(CACHE_LINE_SIZE - 1);
 146
 147   do {
 148     Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;
 149   } while (Start != End);
 150   return Address;
 151 }
 152
 153 /**
 154   Writes Back the entire data cache in cache coherency domain of the calling
 155   CPU.
 156
 157   Writes Back the entire data cache in cache coherency domain of the calling
 158   CPU. This function guarantees that all dirty cache lines are written back to
 159   system memory. This function may also invalidate all the data cache lines in
 160   the cache coherency domain of the calling CPU.
 161
 162 **/
 163 VOID
 164 EFIAPI
 165 WriteBackDataCache (
 166   VOID
 167   )
 168 {
 169   WriteBackInvalidateDataCache ();
 170 }
 171
 172 /**
 173   Writes Back a range of data cache lines in the cache coherency domain of the
 174   calling CPU.
 175
 176   Writes Back the data cache lines specified by Address and Length. If Address
 177   is not aligned on a cache line boundary, then entire data cache line
 178   containing Address is written back. If Address + Length is not aligned on a
 179   cache line boundary, then the entire data cache line containing Address +
 180   Length -1 is written back. This function may choose to write back the entire
 181   data cache if that is more efficient than writing back the specified range.
 182   If Length is 0, the no data cache lines are written back. This function may
 183   also invalidate all the data cache lines in the specified range of the cache
 184   coherency domain of the calling CPU. Address is returned.
 185
 186   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 187
 188   @param  Address The base address of the data cache lines to write back. If
 189                   the CPU is in a physical addressing mode, then Address is a
 190                   physical address. If the CPU is in a virtual addressing
 191                   mode, then Address is a virtual address.
 192   @param  Length  The number of bytes to write back from the data cache.
 193
 194   @return Address of cache written in main memory.
 195
 196 **/
 197 VOID *
 198 EFIAPI
 199 WriteBackDataCacheRange (
 200   IN      VOID                      *Address,
 201   IN      UINTN                     Length
 202   )
 203 {
 204   return WriteBackInvalidateDataCacheRange (Address, Length);
 205 }
 206
 207 /**
 208   Invalidates the entire data cache in cache coherency domain of the calling
 209   CPU.
 210
 211   Invalidates the entire data cache in cache coherency domain of the calling
 212   CPU. This function must be used with care because dirty cache lines are not
 213   written back to system memory. It is typically used for cache diagnostics. If
 214   the CPU does not support invalidation of the entire data cache, then a write
 215   back and invalidate operation should be performed on the entire data cache.
 216
 217 **/
 218 VOID
 219 EFIAPI
 220 InvalidateDataCache (
 221   VOID
 222   )
 223 {
 224   AsmInvd ();
 225 }
 226
 227 /**
 228   Invalidates a range of data cache lines in the cache coherency domain of the
 229   calling CPU.
 230
 231   Invalidates the data cache lines specified by Address and Length. If Address
 232   is not aligned on a cache line boundary, then entire data cache line
 233   containing Address is invalidated. If Address + Length is not aligned on a
 234   cache line boundary, then the entire data cache line containing Address +
 235   Length -1 is invalidated. This function must never invalidate any cache lines
 236   outside the specified range. If Length is 0, the no data cache lines are
 237   invalidated. Address is returned. This function must be used with care
 238   because dirty cache lines are not written back to system memory. It is
 239   typically used for cache diagnostics. If the CPU does not support
 240   invalidation of a data cache range, then a write back and invalidate
 241   operation should be performed on the data cache range.
 242
 243   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 244
 245   @param  Address The base address of the data cache lines to invalidate. If
 246                   the CPU is in a physical addressing mode, then Address is a
 247                   physical address. If the CPU is in a virtual addressing mode,
 248                   then Address is a virtual address.
 249   @param  Length  The number of bytes to invalidate from the data cache.
 250
 251   @return Address.
 252
 253 **/
 254 VOID *
 255 EFIAPI
 256 InvalidateDataCacheRange (
 257   IN      VOID                      *Address,
 258   IN      UINTN                     Length
 259   )
 260 {
 261   //
 262   // Invalidation of a data cache range without writing back is not supported on
 263   // x86 architecture, so write back and invalidate operation is performed.
 264   //
 265   return WriteBackInvalidateDataCacheRange (Address, Length);
 266 }